JPS6310900B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a planar structure, and more particularly to increasing the withstand voltage using a channel stopper.

As shown in FIG. 1, an example of a semiconductor device with a planar structure includes a p-type region 12 formed with a p-type dopant on an n-type semiconductor substrate 11, an n ^++- type channel stopper 13 formed with an n-type dopant, Oxide film 14 as an insulating film, oxide film 14
It consists of Al wiring 15 existing above. In the figure, only a pn junction consisting of an n-type semiconductor substrate 11 and a p-type region 12 is shown.

In such a semiconductor device, when a voltage is applied as shown in the figure, a channel 16 is generated due to the electric field effect of the wiring 15, and the p-type region 12 and another region (not shown) are electrically connected and the influence of the potential is reduced. This made it difficult to obtain high withstand voltage. Therefore, in order to stop this channel, an n ⁺⁺ type region with a higher impurity concentration than the n type semiconductor substrate 11 (for example, a surface concentration
10 ¹⁸ atoms/cm ³ )13 was formed by diffusion to serve as a channel stopper. As a result, the p-type region 12
The depletion layer extending from the side (the region surrounded by the dotted line in the figure) is stopped within the n ⁺⁺ type channel stopper 13 and does not extend to the right side of the n ⁺⁺ type channel stopper 13 in the figure. The reason why the depletion layer extends more in the n-type semiconductor substrate 11 than in the p-type region 12 is that the impurity concentration is lower in the n-type semiconductor substrate 11 than in the p-type region 12. In this way the channel is stopped, but the electric field is concentrated within the n ⁺⁺ type channel stopper 13. FIG. 2 shows the lateral electric field intensity distribution on the surface of the above structure. Since the electric field strength increases rapidly within the n ⁺⁺ type channel stopper 13, avalanche breakdown occurs at a relatively low voltage, which has been an obstacle to increasing the breakdown voltage.

In order to improve the above-mentioned drawbacks, the oxide film 14 may be made thick enough to ignore the influence of the electric field effect caused by the wiring 15. However, this requires a thickness of 3.5 to 4.0 μm, which poses difficulties in the manufacturing method.

In addition, the oxide film 14 is thin and the electric field can be relaxed by lowering the impurity concentration of the n ⁺⁺ type channel stopper 13, but the channel cannot be stopped and the above-mentioned problem cannot be improved.

Therefore, an object of the present invention is to provide a semiconductor device that can achieve high breakdown voltage without causing manufacturing difficulties.

The present invention is characterized by providing at least one electric field relaxation region between the pn junction and the channel stopper, which has the same conductivity type as the channel stopper and has an impurity concentration lower than the impurity concentration of the channel stopper. The goal is to stop the channel reliably without concentrating the electric field.

FIG. 3 shows an embodiment of the present invention, which is an example applied to a semiconductor integrated circuit using a dielectric insulation isolation substrate.

In the figure, a semiconductor integrated circuit 20 is constructed by forming an inverted V-shaped groove 22 in an n-type semiconductor substrate 21 using an oxide film as a mask using an alkaline etchant, and by diffusing arsenic, antimony, phosphorus, etc. or by ion implantation ^. forming a shaped channel stopper 23;
Next, an oxide film 24 for dielectric isolation is formed, polycrystalline silicon 25 is formed by vapor phase growth, and polished from the upper surface of the figure, and then an n ⁺ region 26 for electric field relaxation,
Oxide film 27, p-type region 28, aluminum wiring 2
9.

The impurity concentration of the n-type semiconductor substrate 21 is
The surface impurity concentration of the n ⁺ region for electric field ^{relaxation is about 10 16 atoms} /cm ³ , ^and
The n ⁺⁺ type channel stopper has a surface impurity concentration of about 10 ¹⁸ atoms/cm ³ at the surface in contact with the oxide film 24 .

FIG. 4 shows the surface impurity concentration in the lateral direction near the electric field relaxation n ⁺ region of the semiconductor integrated circuit 20 of FIG. 3, and a to d on the horizontal axis correspond to positions a to d in FIG. 3.

In FIG. 3, wiring 2 is connected to an n-type semiconductor substrate 21.
When a voltage that becomes a positive potential is applied to 9, a depletion layer is formed in the region surrounded by the dotted line. The depletion layer is p
type region 28 and n ⁺ region 26 form n-type semiconductor substrate 21
The impurity concentration of the substrate 21 is
Since it is lower than the n ⁺ region 26, it spreads laterally due to the electric field effect of the wiring 29. Since there is a gradient in impurity concentration within the n ⁺ region 26 as shown in FIG. 4, the electric field becomes strong within this region. However, since the impurity concentration is not very high, it does not stop within this region 26, but stops within the n ⁺⁺ type channel stopper 23 where the impurity concentration is high. Since the electric field has once become stronger in the n ⁺ region 26, the n ⁺⁺ type channel stopper 23
Inside, the electric field is less concentrated and avalanche breakdown is less likely to occur.

FIG. 5 shows the oxide film 14 in FIGS. 1 and 3,
The breakdown voltage is shown when the thickness of No. 27 is 3 μm.

As shown in FIG. 5, according to the present invention, an improvement in breakdown voltage of about 80V was confirmed without increasing the thickness of the oxide film.

FIG. 6 is a top view of FIG. 3, and the oxide film 27 is omitted. This indicates that the electric field relaxing n ⁺ region 26 only needs to be located directly below the wiring 26 .

FIG. 7 shows another embodiment of the invention.

The difference from the embodiment shown in Figure 3 is that the electric field is relaxed.
The n ⁺ region 26 is separate and independent from the n ⁺⁺ type channel stopper 23.

FIG. 8 shows yet another embodiment of the invention.

This example is an example of a diode.

A p-type region 32 is formed in the center of an n-type semiconductor substrate 31 by diffusion, and around the p-type region 32, an electric field relaxing n ⁺ region 33 and an n ^++- type channel stopper 34 are formed in an annular shape by diffusion. A semiconductor oxide film 35 is formed on the upper main surface of the semiconductor substrate 31, and an electrode film 36 is in ohmic contact with the p-type region 32 through an opening provided in the oxide film 35, and an electrode film is also formed on the entire lower main surface. 37 is in ohmic contact. The electrode film 36 is formed not only on the p-type region 32 but also on the entire surface of the oxide film 35.

Such a diode structure is suitable for simultaneously obtaining a plurality of diode pellets from a large area semiconductor thin plate.

In the embodiments shown in FIGS. 7 and 8, the same effects as in the embodiment shown in FIG. 3 were obtained.

In the above embodiment, only one electric field relaxation region is shown, but there may be two or more.

Further, although the channel stopper and the electric field relaxation region are provided in the n-type region, they may be provided in the p-type region. In this case, the channel stopper and the electric field relaxation region are p-type.

Furthermore, the present invention can be applied to various semiconductor devices such as diodes, transistors, and thyristors.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of a conventional semiconductor device, FIG. 2 is a diagram showing the electric field strength of the semiconductor device shown in FIG. 1, and FIG. 3 is a partial diagram of a semiconductor integrated circuit showing an embodiment of the present invention. 4 is a diagram showing the surface impurity concentration of the semiconductor integrated circuit shown in FIG. 3, FIG. 5 is a diagram showing the withstand voltage of the semiconductor device shown in FIGS. 1 and 3, and FIG. The top view of the semiconductor integrated circuit shown in the figure, and FIGS. 7 and 8 are schematic cross-sectional views showing other embodiments of the present invention, respectively. 21...n type semiconductor substrate, 23...n ⁺⁺ type channel stopper, 26...n ⁺ region for electric field relaxation, 27...oxide film (insulating film), 28...p type region, 29... wiring.

Claims (1)

[Claims] 1. One p-n junction is exposed on one main surface of the semiconductor substrate, and the p-type or n-type
In a semiconductor device in which an electrode that is in ohmic contact with one region of the mold is present on another region that is not in ohmic contact with the one main surface via an insulating film, the electrode under the electrode film on the one main surface is above
A channel stopper is formed apart from the pn junction, and between this channel stopper and the pn junction there is an impurity concentration of the same conductivity type as the channel stopper, lower than the channel stopper, and higher impurity concentration than the other regions mentioned above. A semiconductor device in which at least one electric field relaxation region is formed away from the pn junction. 2. The semiconductor device according to claim 1, wherein the channel stopper and the electric field relaxation region are adjacent to each other. 3. The semiconductor device according to claim 1, wherein the channel stopper and the electric field relaxation region are separated.