JPS63133771U

JPS63133771U -

Info

Publication number: JPS63133771U
Application number: JP2442487U
Authority: JP
Priority date: 1987-02-20
Filing date: 1987-02-20
Publication date: 1988-09-01

Description

[Brief explanation of the drawing]

第１図は本考案の実施例に係る回路ブロツク図
、第２図は動作説明図、第３図はパルス発生回路
のブロツク図、第４図、第５図は第３図の動作波
形説明図を、それぞれ示す。９……第２データラツチ回路、１０……アドレ
スラツチ回路、６……ＲＡＭ、５……データセレ
クト回路、６……アドレスセレクト回路、２……
タイミングパルス発生回路、ＲＰ……読出パルス
、ＷＰ……書込パルス。 FIG. 1 is a circuit block diagram according to an embodiment of the present invention, FIG. 2 is an operation explanatory diagram, FIG. 3 is a block diagram of a pulse generation circuit, and FIGS. 4 and 5 are operation waveform explanatory diagrams of FIG. 3. are shown respectively. 9...Second data latch circuit, 10...Address latch circuit, 6...RAM, 5...Data select circuit, 6...Address select circuit, 2...
Timing pulse generation circuit, RP...Read pulse, WP...Write pulse.

Claims

[Claim for Utility Model Registration] Write data constituting a sub-screen video signal is stored in the write period of a write line specified at a ratio of 1 line for every n lines, and corresponds to the sub-screen insertion area of the main screen. In order to reduce the size of the child screen to 1/n in the main screen by reading data during the readout period of the readout line, the write data is stored each time a write address is specified during the write period, and the readout data is A dual port dynamic system that reads data line by line after the read start address in synchronization with the serial clock during the period, and a write address and write data in synchronization with the read pulse preceding the read period. selecting a read start address in synchronization with the read pulse; selecting an output of the latch means in synchronization with a write pulse issued during a write inhibit period in the write line; a select circuit that supplies an output to the dynamic circuit; and a missing data write circuit that is arranged for each of the select circuits.