JPS63553U

JPS63553U -

Info

Publication number: JPS63553U
Application number: JP9383186U
Authority: JP
Priority date: 1986-06-18
Filing date: 1986-06-18
Publication date: 1988-01-05

Description

[Brief explanation of drawings]

第１図は本考案の一実施例に含まれる出力画面
位置設定回路のブロツク図、第２図は前記出力画
面位置設定回路に含まれる主走査記録有効信号発
生回路および副走査記録有効信号発生回路のブロ
ツク図、第３図は前記出力画面位置設定回路に含
まれる記録開始位置選択回路のブロツク図、第４
図ａ，ｂおよびｃと、第５図ａ，ｂ，ｃ，ｄおよ
びｅは、前記出力画面位置設定回路における各部
の信号波形図である。図において、１……記録開始位置選択回路、２
……主走査記録有効信号発生回路、３……副走査
記録有効信号発生回路、４，５……論理和回路、
６，１０……微分回路、７，８，１１，１２……
カウンタ回路、９，１３……フリツプフロツプ、
１４〜１７……スイツチ、１８……選択回路。 FIG. 1 is a block diagram of an output screen position setting circuit included in an embodiment of the present invention, and FIG. 2 is a main scanning recording valid signal generation circuit and a sub-scanning recording valid signal generation circuit included in the output screen position setting circuit. 3 is a block diagram of the recording start position selection circuit included in the output screen position setting circuit, and FIG. 4 is a block diagram of the recording start position selection circuit included in the output screen position setting circuit.
Figures a, b, and c and Figures a, b, c, d, and e are signal waveform diagrams of each part in the output screen position setting circuit. In the figure, 1... Recording start position selection circuit, 2
...Main scanning recording valid signal generation circuit, 3...Sub-scanning recording valid signal generation circuit, 4, 5...OR circuit,
6, 10... Differential circuit, 7, 8, 11, 12...
Counter circuit, 9, 13... flip-flop,
14-17... switch, 18... selection circuit.

Claims

[Scope of utility model registration request]

Image signal data is once stored in a memory, and the stored data is read out from the memory at a predetermined clock by specifying output dimensions such as full-size recording or reduced recording;
In a facsimile receiving device that performs sub-scanning at a predetermined sub-scanning line density, a recording start signal in the main scanning direction is generated by counting readout clocks up to a set number as a phase signal trigger generated within the facsimile receiving device for each scan. A first counter circuit outputs a recording start signal in the sub-scanning direction by counting the phase signal up to a set number using the sub-scanning start signal as a trigger, and a second counter circuit outputs a recording start signal in the sub-scanning direction. input an output dimension selection signal, and via the output dimension selection signal,
A facsimile receiving apparatus comprising: a circuit that selects and outputs the values set in the first counter circuit and the second counter circuit from among preset values.