JPS6313519A - Pulse timing adjusting circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a pulse timing adjustment circuit that adjusts the timing between pulses and in-phase n to W4 with high resolution.

[Conventional technology].

For example, when testing a D/AW1 device, it is necessary to apply multiple bit pulse signals having the same frequency and the same duty ratio at the same timing.

Therefore, in conventional devices, for example, the average level of the exclusive OR output of two pulse signals whose timing is to be matched is detected in an analog manner, and one of the pulse signals is delayed so that the average level is minimized. , the timing of each pulse signal is made to match by sequentially applying pulse signals whose timing is to be matched to one comparator and strobe them at the same timing, gradually delaying each pulse signal so that the comparison output is inverted. It is being said.

[Problems to be solved by invention E] However, according to the former method, when the timings of the two pulse signals approach each other, the exclusive OR output becomes small, and even if an ECL circuit is used, for example, a minute timing error of less than Ins occurs. is difficult to detect. In addition, according to the latter method, by using a speed comparator, the number of
Although a timing error of approximately 0 ps can be detected, timing errors smaller than that are difficult to detect due to jitter in the response time of the comparator and the influence of noise.

The present invention has been made with attention to this point, and its purpose is to provide a pulse timing adjustment circuit that can detect minute timing errors with a relatively simple configuration and can perform timing adjustment of 6 m degrees. It is in.

``Means for Solving Problem E'' The present invention that achieves this purpose is based on two
a signal detection means for selectively detecting a signal component equal to the frequency of the pulse signal from the output signal of the comparison means; and an output signal level of the signal detection means. J, sea urchin comparison 1 where is the minimum
It is characterized by comprising a time adjustment means for adjusting the time relationship between the pulse signals applied to the stages.

[Example 1 Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a clock generator that generates a clock signal S with a period of T, and its output signal S1 is produced by a pulse adjustment circuit 2 that includes a differentiation circuit and a delay circuit and can arbitrarily adjust the pulse width and time relationship. .3 has been added. The output signals 82 and 83 of these pulse adjustment circuits 2 and 3 are applied to the object to be measured 4 and also to the exclusive OR gate 5. 6 is an amplifier for amplifying the output signal S4 of the exclusive OR gate 5;
5 is applied to a bandpass filter 7 having a Q as high as ioooo, which extracts the fundamental wave component (f-1/T>) of the clock signal S1. The rectifying detector 9 is an A/D converter that converts the analog signal S7 rectified by the detector 8 into a digital signal Se.The digital signal S8 converted and output from the A/D converter 9 is The calculation control unit 10 is added to a calculation control unit 10 such as a processor. Control signals CL1 and CL2 are output to the pulse adjustment circuit 2.3.

The operation of the circuit configured in this way will be explained using timing chart 1- in FIG. 2.

In FIG. 2, J3 is shown, and (a) is the clock generator 1 with period T.
The output signal S1 is shown. When testing a certain type of measurement object 4, the output signal S! from the pulse adjustment circuit 2 is as shown in (b). Valve switch R S2 with a delay Ill fat T d + and a pulse width of TW is output as a starting pulse with respect to the rising edge of -5
A pulse signal 83 having a delay time -rd2 with respect to the rising edge and having a pulse width TW equal to that of the pulse signal 82 is output as a slave pulse that takes in the output signal pulse of the measurement object 4.

On the other hand, if it is desired to match the rising edges of the pulse signals @S2.8a with the same 4f pulse width T w ffi with high precision, first the setting time of each delay circuit input to the pulse adjustment circuit 2.3 is Make it zero. As a result, a pulse signal S2 as shown in (d) from the pulse adjustment circuit 2 is applied to one input terminal of the exclusive OR gate 5, and a pulse signal @S3 as shown in (e) is applied from the pulse adjustment circuit 3. is applied to the other input terminal of exclusive OR gate 5.

As a result, the exclusive OR gate 5 outputs a pulse signal S4 as shown in (f>).

Here, focusing on the period of the pulse signal S4, it is equal to the period 2 of the output signal S1 of the clock generator 1, and the period component of the pulse signal S4 included in the pulse signal S4 is the output signal of the pulse adjustment circuits 2 and 3. S2. This is related to the difference in timing of S3. Therefore, the period T component of the output signal $1 of the clock generator 1 is reproduced from the output signal S4 of the agricultural OR gate 5 by the amplifier 6 and the bandpass filter 7. Then, this reproduced signal S6 is rectified into an analog DC signal S7 by a detector 8, and then converted into a digital signal (+J@S a) by an A/D converter 9 and applied to the ll# calculation control section 10. is the control signal OL+ for adjusting the delay time of each delay circuit outputted from the exclusive OR gate 5 (which is sent to the pulse adjustment circuit 2.33 to reduce the pulse width of fflQS4).
.

Output CL2.

In this way, the output signal S4 of the v1 passive OR gate 5
By adjusting the pulse width to the minimum (ideally zero), the pulse signal S2 output from the pulse adjustment circuit 2 and the pulse m No. 8 output from the pulse 11 adjustment circuit 1jIl path 3 are
It is possible to match the timing' of 3 with a height of 1!1m.

Note that the one stage for comparing the pulse widths is limited to an exclusive OR gate, and may be an AND gate or an OR gate.

Also, filters are useless using active filters and digital filters.

Further, by using a logarithmic detector constituted by a logarithmic amplifier as a wave detector, it is possible to detect a signal with minute amplitude, which is effective.

Furthermore, the timing adjustment means may be omitted and the circuit may be used as a timing detection circuit.

[Effects of the Invention] As explained above, according to the present invention, it is possible to realize a pulse timing adjustment circuit that can detect minute timing errors and adjust the timing of spermatozoa with a simple configuration of the comparison section 11, and is suitable for practical use. The effect is great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the invention, and FIG. 2 is a timing chart for explaining the invention in detail. DESCRIPTION OF SYMBOLS 1... Clock generator, 2.3... Pulse adjustment circuit, 4... Measurement object, 5... Exclusive OR gate,
6...Amplifier, 7...Band pass filter, 8...
- Detector, 9... A/D converter, 10... Arithmetic control unit.

Claims (1)

[Claims] Comparing means for comparing the time relationship between two pulse signals having the same frequency; signal detecting means for selectively detecting a signal component equal to the frequency of the pulse signal from the output signal of the comparing means; and an output of the signal detecting means. 1. A pulse timing adjustment circuit comprising: time adjustment means for adjusting the time relationship between pulse signals applied to the comparison means so that the signal level is minimized.