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JPS585478B2 - Yomitori Cairo - Google Patents
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JPS585478B2 - Yomitori Cairo - Google Patents

Yomitori Cairo

Info

Publication number
JPS585478B2
JPS585478B2 JP50009730A JP973075A JPS585478B2 JP S585478 B2 JPS585478 B2 JP S585478B2 JP 50009730 A JP50009730 A JP 50009730A JP 973075 A JP973075 A JP 973075A JP S585478 B2 JPS585478 B2 JP S585478B2
Authority
JP
Japan
Prior art keywords
signal
circuit
detected
noise
amplitude
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP50009730A
Other languages
Japanese (ja)
Other versions
JPS5185335A (en
Inventor
安藤哲哉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP50009730A priority Critical patent/JPS585478B2/en
Publication of JPS5185335A publication Critical patent/JPS5185335A/ja
Publication of JPS585478B2 publication Critical patent/JPS585478B2/en
Expired legal-status Critical Current

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  • Static Random-Access Memory (AREA)
  • Manipulation Of Pulses (AREA)

Description

【発明の詳細な説明】 本発明は記憶装置などの読取回路において、低い周波数
の雑音が重畳している入力信号から検出すべき信号の検
出が可能な読取回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reading circuit for a storage device or the like, which is capable of detecting a signal to be detected from an input signal on which low frequency noise is superimposed.

記憶装置の読取回路においては信号が雑音により誤って
読取られないようにすることが必要である。
In the reading circuit of a storage device, it is necessary to prevent signals from being read incorrectly due to noise.

雑音の振幅が信号の振幅より少さい場合は単に振幅弁別
回路により信号の検出が可能であるが、雑音の振幅が信
号の振幅より大きくかつ雑音の周波数が信号の周波数よ
り低い場合は直流再生回路を用いることにより信号の振
幅弁別を可能にする方法が従来性なわれていた第1図に
従来の方法による読取回路のブロック図を示す。
If the amplitude of the noise is smaller than the amplitude of the signal, the signal can be detected simply by an amplitude discrimination circuit, but if the amplitude of the noise is larger than the amplitude of the signal and the frequency of the noise is lower than the frequency of the signal, a DC regeneration circuit is used. FIG. 1 shows a block diagram of a reading circuit according to the conventional method.

同図で、1は入力端子、2は低周波を除去するための直
流再生回路、3は振幅弁別回路、4は直流再生回路を制
御するためのワイドストローブ信号の入力端子、5は振
幅弁別回路に与えるナローストローブ信号の入力端子で
ある。
In the figure, 1 is an input terminal, 2 is a DC regeneration circuit for removing low frequencies, 3 is an amplitude discrimination circuit, 4 is a wide strobe signal input terminal for controlling the DC reproduction circuit, and 5 is an amplitude discrimination circuit. This is the input terminal for the narrow strobe signal given to the .

第2図は第1図の説明用の動作波形図であり、同図を用
い第1図の動作を詳細に説明する。
FIG. 2 is an operational waveform diagram for explaining the operation shown in FIG. 1, and the operation shown in FIG. 1 will be explained in detail using this diagram.

aは振幅がVsの検出すべき信号波形であるが、入力端
子1にはbで示すように低い周波数の雑音が重畳した波
形が加わる。
Although a is a signal waveform with an amplitude of Vs to be detected, a waveform on which low frequency noise is superimposed is added to the input terminal 1 as shown by b.

ここで波形すの実線部、破線部はそれぞれ信号のあり、
なしの場合を示す(以下の波形も同様である)。
Here, the solid line part and the broken line part of the waveform are where the signal is, respectively.
This shows the case without (the following waveforms are similar).

Cのワイドストローブは信号の立上り位置から信号を十
分に含む時間位置まで印加し、直流再生回路2の出力は
dの波形となる。
The wide strobe C is applied from the rising position of the signal to the time position sufficiently containing the signal, and the output of the DC regeneration circuit 2 has a waveform d.

eのナローストローブはdの波形で信号対雑音比S/N
の最大となる装置に印加する。
The narrow strobe of e has the signal-to-noise ratio S/N in the waveform of d.
Apply to the device that produces the maximum.

このナローストローブ印加時の雑音レベルはVNはワイ
ドストローブCの立上り値からナローストローブeまで
の雑音波形の変化値となる。
The noise level VN when applying this narrow strobe is the change value of the noise waveform from the rising value of the wide strobe C to the narrow strobe e.

従って振幅弁別回路3の弁別レベルVT1をVNとVN
+Vsの間のレベルに決めればfの出力が得られる。
Therefore, the discrimination level VT1 of the amplitude discrimination circuit 3 is set to VN and VN.
If the level is set between +Vs, an output of f can be obtained.

しかし、雑音レベルVNは通常一定の値とは限らないの
で、その変動レベル幅が信号の振幅Vsより大きい場合
、弁別レベルVT1を雑音の大きさによって可変としな
い限り雑音と信号の区別が不可能となる欠点がある。
However, the noise level VN is usually not a constant value, so if the fluctuation level width is larger than the signal amplitude Vs, it is impossible to distinguish between the noise and the signal unless the discrimination level VT1 is varied depending on the noise level. There is a drawback.

本発明の目的は、上記した従来回路の欠点をなくし、信
号対雑音比の高い読取回路を提供するにある。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the conventional circuits described above and provide a reading circuit with a high signal-to-noise ratio.

第3図は本発明の一実施例である読取回路のブロック図
である。
FIG. 3 is a block diagram of a reading circuit which is an embodiment of the present invention.

同図で第1図と同一符号は同一部分を示し、7は信号立
上り時間から最大値までの時間Twの遅延時間をもつ遅
延素子、8は入力信号すと遅延紐出力gの差動をとる差
動増幅回路である。
In the figure, the same symbols as in Figure 1 indicate the same parts, 7 is a delay element with a delay time of time Tw from the signal rise time to the maximum value, and 8 takes the differential between the input signal and the delay string output g. It is a differential amplifier circuit.

第4図は第3図の説明のための波形図である。FIG. 4 is a waveform diagram for explaining FIG. 3.

第4図を用いて第3図の動作を詳細に説明する。The operation shown in FIG. 3 will be explained in detail using FIG. 4.

第3図と同一符号は同一部分の波形を示す。The same symbols as in FIG. 3 indicate waveforms of the same parts.

gは遅延素子7の出力波形であり、入力信号すの波形よ
りTwだけ遅れている。
g is the output waveform of the delay element 7, which lags behind the waveform of the input signal S by Tw.

hは差動増幅回路8の出力波形であり、入力信号すと遅
延信号gの差動をとることにより雑音レベルは減衰し信
号レベルは不変の波形となる。
h is the output waveform of the differential amplifier circuit 8, and by taking the differential between the input signal and the delayed signal g, the noise level is attenuated and the signal level remains unchanged.

hで示す差動増幅回路8の出力で直流再生回路2を動作
させれば、雑音レベルVNはほとんど0、即ち直流再生
回路2を通すことにより一読取る信号の直前の値を0V
に設定することができ、S/N比の向上を計ることがで
きる。
If the DC regeneration circuit 2 is operated with the output of the differential amplifier circuit 8 indicated by h, the noise level VN will be almost 0, that is, the value immediately before the signal to be read once through the DC regeneration circuit 2 will be 0V.
can be set to improve the S/N ratio.

そして振幅弁別回路3の弁別レベルVT2を信号レベル
のほぼ半分に設定すれば、信号の検出を安定に行なうこ
とができる。
If the discrimination level VT2 of the amplitude discrimination circuit 3 is set to approximately half the signal level, the signal can be detected stably.

なお、振幅弁別回路3の出力は第1図と同様であり省い
た。
Note that the output of the amplitude discrimination circuit 3 is the same as that shown in FIG. 1 and is therefore omitted.

さらに、第4図のワイドストローブCのタイミングを変
えることにより信号対雑音比S/Nの向上を計ることが
できる。
Furthermore, the signal-to-noise ratio can be improved by changing the timing of the wide strobe C shown in FIG.

すなわち第5図に示すようにワイドストローブCの立上
り位置を信号の立上り時間位置でなく、最大値の時間位
置とすることにより、dで示すように直流再生回路2の
出力信号の最大値は振幅vsの2倍とすることができ、
このときの弁別レベルVT3はほぼvsとすることがで
き、また雑音レベルVNは増加しないので信号対雑音比
S/Nのより一そうの向上が可能となる。
In other words, by setting the rising position of the wide strobe C to the time position of the maximum value, rather than the rising time position of the signal, as shown in FIG. It can be twice as much as vs.
At this time, the discrimination level VT3 can be set to approximately vs, and since the noise level VN does not increase, it is possible to further improve the signal-to-noise ratio S/N.

以上説明したように、本発明により振幅が大きくかつ低
い周波数の雑音が重畳した入力信号から検出すべき信号
の検出を安定に行なう読取回路が実現できる。
As described above, according to the present invention, it is possible to realize a reading circuit that stably detects a signal to be detected from an input signal on which noise of large amplitude and low frequency is superimposed.

本発明は、入力信号が上記特性を持つ磁気バブル記憶装
置の読取系に適用するに特に好適である。
The present invention is particularly suitable for application to a reading system of a magnetic bubble storage device whose input signal has the above characteristics.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の読取回路を示すブロック図、第2図は第
1図の説明用の波形図、第3図は本発明による読取回路
の一実施例を示すブロック図、第4図および第5図は第
3図の説明用の波形図である。 符号の説明、1……入力端子、2……直流再生回路、3
……振幅弁別回路、4……ワイドストローブ入力端子、
5……ナローストローブ入力端子、6……出力端子、7
……遅延素子、8……差動増幅回路。
FIG. 1 is a block diagram showing a conventional reading circuit, FIG. 2 is a waveform diagram for explaining FIG. 1, FIG. 3 is a block diagram showing an embodiment of the reading circuit according to the present invention, and FIGS. FIG. 5 is a waveform diagram for explaining FIG. 3. Explanation of symbols, 1...Input terminal, 2...DC regeneration circuit, 3
...Amplitude discrimination circuit, 4...Wide strobe input terminal,
5...Narrow strobe input terminal, 6...Output terminal, 7
...Delay element, 8...Differential amplifier circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 検出すべき信号の検出レベルより振幅が大きくかつ
低い周波数の雑音が含まれる入力信号から検出すべき信
号を読取る回路であって、前記検出すべき信号の立上り
位置から最大値または立下り位置から最少値までの時間
だけ入力信号を遅延させる遅延素子と、該遅延素子の出
力信号と前記入力信号との差動をとる差動増幅回路と、
該差動増幅回路の出力を入力とする直流再生回路とを備
え、該直流再生回路により読取る信号の直前の値を0V
に設定するように構成したことを特徴とする読取回路。
1 A circuit that reads a signal to be detected from an input signal containing noise with a frequency larger than the detection level of the signal to be detected and whose amplitude is larger than the detection level of the signal to be detected, the circuit reading the signal to be detected from the rising position of the signal to be detected to the maximum value or from the falling position of the signal to be detected. a delay element that delays an input signal by a time up to a minimum value; a differential amplifier circuit that takes a difference between an output signal of the delay element and the input signal;
and a DC regeneration circuit that receives the output of the differential amplifier circuit, and converts the value immediately before the signal read by the DC regeneration circuit to 0V.
A reading circuit characterized in that it is configured to set.
JP50009730A 1975-01-24 1975-01-24 Yomitori Cairo Expired JPS585478B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50009730A JPS585478B2 (en) 1975-01-24 1975-01-24 Yomitori Cairo

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50009730A JPS585478B2 (en) 1975-01-24 1975-01-24 Yomitori Cairo

Publications (2)

Publication Number Publication Date
JPS5185335A JPS5185335A (en) 1976-07-26
JPS585478B2 true JPS585478B2 (en) 1983-01-31

Family

ID=11728416

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50009730A Expired JPS585478B2 (en) 1975-01-24 1975-01-24 Yomitori Cairo

Country Status (1)

Country Link
JP (1) JPS585478B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5816549B2 (en) * 1977-04-13 1983-03-31 株式会社日立製作所 Read signal discrimination method for magnetic bubble storage device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3668532A (en) * 1971-01-25 1972-06-06 Sperry Rand Corp Peak detection system

Also Published As

Publication number Publication date
JPS5185335A (en) 1976-07-26

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