JPS6314871B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a resistive element in a gallium arsenide (GaAs) integrated circuit device.

(b) Prior Art and Problems In order to realize ultra-high-speed digital circuits or ultra-high frequency signal processing, integrated circuit devices using GaAs, which has mobility several times higher than silicon (Si), are being put into practical use.

In such a GaAs semiconductor device for ultra-high speed or ultra-high waves, transistors and resistance elements are formed in a very shallow surface layer of the surface of a GaAs crystal substrate. However
The surface layer of a GaAs substrate is strongly influenced by residual impurities in the GaAs substrate and by a surface depletion layer caused by surface states generated when a protective film is formed on the substrate surface. Resistance element is semi-insulating
It is usually formed by implanting n-type impurity silicon (Si) ions or the like into the surface of a GaAs substrate, but controlling the resistance value thereof is not necessarily easy due to the above-mentioned problems.

FIG. 1 is a cross-sectional view of a main part showing a conventional method for manufacturing a GaAs semiconductor device in the order of manufacturing steps. The above-mentioned problems will be explained below with reference to the same figure.

In the same figure a, 1 is a semi-insulating GaAs substrate, 2
is the first photoresist film. The GaAs substrate 1 is a semi-insulating substrate doped with chromium (Cr) to a concentration of approximately 0.1 [ppm]. Using the first photoresist film 2 as a mask, silicon (Si) ions are selectively implanted into this GaAs substrate 1 at an implantation energy of about 60 [KeV] and a dose of about 0.8 [cm ^-2 ]. 3 indicates the Si ion implantation region.

Next, as shown in FIG. 1B, a second photoresist film 4 is formed in place of the first photoresist film 2, and using this as a mask, Si ions are implanted again. In this step, the implantation energy is approximately 120 [KeV] and the dose is approximately 3×10 ¹² [cm ^-2 ]. 5 shows the Si ion implantation region in this step.

Next, as shown in Figure c, a shot gate electrode 6 made of tungsten silicide (WSi) is formed on the surface of the Si ion implanted region 3, and then
A silicon dioxide (SiO ₂ ) film 7 is formed to form openings in the Si ion implantation regions 3 and 5, and the SiO 2 film is re-injected using this and the shot gate electrode 6 as a mask.
Perform ion implantation. In this process, the implantation energy is approximately 200 [KeV] and the dose is approximately 2×10 ¹³ [cm
^-2 ]. 8 is a Si ion implantation region in this step.

Next, as shown in FIG. d, the SiO ₂ film 7 is removed and an aluminum nitride (AlN) film (not shown) is removed.
is formed, and this is used as a protective film to perform heat treatment for about 15 minutes at a temperature of about 800 [°C] to activate the Si ions implanted in the Si ion implanted regions 3, 5, and 8. ⁺ type source and drain regions 9;
9', an n-type active layer 10, an n ⁺ type contact region 11, and an n-type resistance layer 12 are formed.

Next, after removing the AlN film, source and drain electrodes 13 and 13' made of gold-germanium-gold (AuGe-Au) and resistor terminal electrodes 14, which form ohmic contact with the n-type GaAs crystal, are formed.
14' is formed by a lift-off method. Furthermore, a SiO ₂ film 15, for example, is deposited as an interlayer insulating film on the entire surface of the GaAs substrate 1 including the tops of each of the above electrodes, and this is selectively removed to open a contact window. A connecting upper wiring electrode 16 made of titanium-gold (Ti-Au) is selectively formed.

Although a GaAs integrated circuit device is manufactured by the method described above, the conventional manufacturing method described above does not provide sufficient controllability of the resistive layer 12. Second
The figure shows the relationship between the resistivity and the dose of the resistive layer 12 formed by implanting Si ions at an energy of 120 [KeV] using the conventional process described above. The horizontal axis of the figure shows the dose [×10 ¹² cm ^-2 ], and the vertical axis shows the sheet conductivity [KΩ□ ^-1 ] on the left and the sheet resistivity [KΩ□] on the right.

The electrical conductivity of the resistive layer 12 is originally proportional to the dose, and therefore the relationship between the two should be shown by a straight line passing through the origin in FIG. However, in reality, as shown by the solid line A in the figure, the extension of the straight line showing the relationship between the two deviates from the origin, and the resistivity takes a value much higher than the theoretical value when the dose is small. This is because apparent inactivation occurs during low-dose implantation due to the influence of residual impurities in the GaAs substrate, and because the interface between the SiO ₂ film 15 and GaAs substrate 1 shown in FIG. This is due to the formation of a surface depletion layer by the generated surface states.

For these reasons, conductivity becomes non-linear during low-dose implantation, and conductivity is exhibited only after a certain threshold value is exceeded [solid line A]. In addition, there are cases where the conductivity and the dose deviate from the linear relationship (dotted chain line B), and there are also cases where the constant of proportionality differs depending on the manufacturing lot (solid lines A and C).

As described above, in the conventional manufacturing method, the controllability and reproducibility of the resistivity of the resistive layer 12 is poor, and therefore it is not necessarily easy to manufacture a GaAs integrated circuit device having desired electrical characteristics. .

(c) Object of the Invention An object of the present invention is to solve the above-mentioned problems and provide a method for manufacturing a semiconductor device in which a desired resistance element can be stably and easily formed on a semi-insulating GaAs substrate.

(d) Structure of the Invention The present invention is characterized in that the peak of the concentration distribution is located in a desired region of a semi-insulating gallium/arsenic substrate at a depth of approximately 0.05 [μm] or less from the surface of the gallium/arsenic substrate. Like, silicon ion 0.5~1.0
A step of implanting at a dose of ×10 ¹² [cm ^-2 ] and a predetermined implantation step in which the peak of the concentration distribution is located at a depth of about 0.05 [μm] or more from the surface of the gallium/arsenic substrate in the desired region. The present invention includes a step of forming a resistor element including a step of implanting n-type impurity ions and a step of activating the implanted ions.

(e) Implementation sequence of the invention In view of the fact that the above conventional problems are caused by the influence of the surface of the GaAs substrate, the present invention was made as a result of various studies on the influence of this surface, and the influence of the GaAs substrate surface is reduced as much as possible. and by forming a conductive layer on unaffected areas of the surface.
This allows a resistor element to be formed on a GaAs substrate with good reproducibility and controllability.

Hereinafter, one embodiment of the present invention will be explained together with the above-mentioned study results with reference to the drawings.

FIG. 3 is a diagram showing the relationship between the implantation energy (that is, the formation depth of the conductive layer) and the variation in the conductivity of the obtained conductive layer when performing ion implantation for forming the conductive layer. The horizontal axis in the figure is the implantation energy [KeV]
The vertical axis represents the variation in conductivity, which is expressed as the ratio of the standard deviation σ to the average value x of the conductivity. Note that ion implantation for the sample shown in the figure was performed with the surface of the GaAs substrate exposed. Also, the ion species to be implanted are
Si was used at a dose of approximately 3×10 ¹² [cm ⁻² ].

As shown in the figure, the implantation energy is approximately 100
When it is more than [KeV], the variation becomes almost [%] or less. This means that the peak position Rp of the implanted ion concentration distribution is approximately 0.1 [μm] from the GaAs substrate surface.
Indicates that it is necessary to meet the above requirements. Conversely, this suggests that the depth at which the surface is affected is approximately 0.1 [μm] or less.

Figure 4 shows that in order to reduce the influence of the GaAs substrate surface, Si ions are implanted shallowly into the GaAs substrate surface (hereinafter referred to as base implantation), and then Si is implanted deeper (to control conductivity). 2 is a diagram showing the effect of injection (hereinafter referred to as controlled injection). The horizontal axis of the figure is approximately
The dose when the above-mentioned controlled implantation was performed with an energy of 120 [KeV] is shown, and the vertical axis shows the sheet conductivity [KΩ□ ^-1 ] of the obtained conductive layer.

As for the above-mentioned base implantation, since Si ions are implanted to a depth of approximately 0.1 [μm] from the results shown in Fig. 3, the implantation energy that makes Rp approximately 0.05 [μm] deep, that is, approximately 60 [KeV] Accordingly, implantation was performed at a dose of approximately 0.8×10 [cm ⁻² ]. Controlled implantation was performed on this sample with an implantation energy of approximately 120 [KeV], and as shown in the figure, the relationship between the Sina conductivity of the conductive layer obtained and the dose of controlled implantation was approximately a straight line passing through the origin. It became a relationship.

This means that by performing an appropriate base implantation on the surface of the GaAs substrate, the influence of the surface is almost absorbed, and that if a conductive layer is formed by controlled implantation at a deeper position in this state, this conductive layer can be It is suggested that the conductivity of the layer can be determined only by controlled implantation.

FIG. 5 is a diagram showing the relationship shown in FIG. 4 above with the dose amount of base implantation as a parameter, and curve A
is the same as in Figure 4 above, and the dose is 0.8×
10 ¹² [cm ^-2 ]. Furthermore, curves B, C, D, E,
F has a dose of 0.1×10 ¹² , 0.5×10 ¹² ,
The cases of 1.0×10 ¹² , 1.5×10 ¹² , and 2.0×10 ¹² [cm ^-2 ] are shown. As shown in these curves, if the dose is in the range of 0.5 to 1.0×10 ¹² [cm ^-2 ], the fluctuation in conductivity is small, but if the dose is less than the above range, the surface effect may occur. On the other hand, if there is too much compensation, it will be under-compensated, and if there is too much, it will be over-compensated. That is, as a result, if the above range is exceeded, the conductivity of the conductive layer will vary greatly depending on the dose of the base implantation, and controllability will be lost.

Furthermore, FIG. 6 is a diagram showing the relationship between the variation in sheet conductivity and the implantation energy (i.e., implantation depth) of basal implantation, where the horizontal axis is the implantation energy [KeV] and the vertical axis is the variation in sheet conductivity σ/
Indicates [%]. For the sample in the same figure, the base implantation dose was 0.8×10 ¹² [cm ^-2 ], and after the base implantation, the implantation energy was approximately 120 [KeV] and the dose was approximately 1×10 ¹² [cm -2 ]. ^-2 ] was carried out using a controlled injection.

As seen in the figure, as the implantation energy during base implantation increases, the variation in conductivity increases. Assuming that this variation is approximately 5% or less in practical terms, the implantation energy of the basal implantation must be approximately 60[KeV] or less. This is the basal injection
This means that it is necessary to suppress Rp to a depth of approximately 0.05 [μm] or less.

Based on the above study results, in the present invention, semi-insulating
On the GaAs substrate surface, the depth of the peak position Rp of the concentration distribution is about 0.05 [μm] or less, and the dose is about 0.5 ~
After implanting ions of 1.0 [cm ^-2 ], desired n-type impurity ions are implanted to a depth where the peak position Rp of the concentration distribution is approximately 0.05 [μm] or more.
It was concluded that the desired resistance element could be produced with good controllability and reproducibility.

FIG. 7 is a cross-sectional view of a main part of one embodiment of the present invention implemented based on the above conclusion, showing the manufacturing process in order. The present implementation sequence will be described below with reference to the same figure.

As shown in Figure 7a, the resistivity is approximately 10 ⁷ [Ωcm] with a dose of approximately 0.1 [ppm] of chromium (Cr).
A photoresist film 2 having a predetermined pattern of openings in areas where transistor elements and resistance elements are to be formed is formed on the surface of a semi-insulating GaAs substrate 1,
Using this as a mask, Si ions are implanted into the surface of the GaAs substrate to form ion implantation regions 2 and 5. In this process, the injection energy is approximately 60
[KeV], the dose of Si ions is approximately 0.8×10 ¹² [cm
^-2 ]. As a result, a concentration distribution in which the peak Rp of the distribution is located at a depth of approximately 0.05 [μm] is obtained.

The above ion implantation is performed for the purpose of forming an active layer for a transistor element, and for the above-mentioned base implantation for a resistor element. When creating an integrated circuit device having a FET and a resistance element on a GaAs substrate in this way, the conditions for base implantation for forming the resistance element in the present invention are the same as the ion implantation conditions for forming the active layer of the FET. In many cases, they are the same. Therefore, in such a case, both ion implantations can be performed in the same process. If the ion implantation for forming the active layer of the FET requires, for example, about 3×10 ¹² [cm ^-2 ] and does not satisfy the above-mentioned conditions for base implantation, the ion implantation for forming the active layer of the FET may be performed separately as in the conventional manufacturing method. Ion implantation may be performed in the step of.

After this, you can proceed according to the normal manufacturing process.
In other words, as shown in Figure b, after removing the photoresist film 2, an arsenide layer of a high melting point metal such as W--Si is selectively formed to improve the surface of the ion implantation layer 3. A shot gate electrode 6 is formed to make shot contact with the photoresist film 7, and a photoresist film 7 is formed again. Using both as a mask, Si ions are implanted at an implantation energy of approximately 200 [KeV].
selectively implant Si ions into the GaAs substrate surface,
Ion implantation regions 8 and 21 are formed. The relationship between the dose in this step and the sheet conductivity of the obtained conductive layer will be described later.

Next, as shown in Figure c, the SiO ₂ film 7 is removed and an aluminum nitride (AlN) film (not shown) is removed.
This is used as a protective film and heat-treated at a temperature of about 800 [°C] for about 15 minutes to activate the Si ions implanted in the Si ion implanted regions 3, 5, and 8, and to form n ⁺ type source and drain regions 9,
9', an n-type active layer 10, an n-type base implant 22, and an n ⁺ -type conductive layer 23 are formed.

Next, after removing the AlN film, source and drain electrodes 13 and 13' made of gold-germanium-gold (AuGe-Au) and resistor terminal electrodes 14, which form ohmic contact with the n-type GaAs crystal, are formed.
14' is formed by a lift-off method. Furthermore, a SiO ₂ film 15, for example, is deposited as an interlayer insulating film on the entire surface of the GaAs substrate 1 including the tops of each of the above electrodes, and this is selectively removed to open a contact window. A contacting upper wiring electrode 16 made of titanium-gold (Ti-Au) is selectively formed.

As shown in the figure, the resistance element R in this implementation row is
The base injection layer 22 formed in the shallow part of the surface of the GaAs substrate 1 and the n ⁺ type conductive layer formed in the deep part are formed as an integrated layer. As mentioned above, the base injection layer 22 is for absorbing the influence of the surface of the GaAs substrate 1, and this layer itself does not contribute to the conductivity of the resistive element R. Therefore, the resistance value of the resistance element R in this embodiment is substantially equal to that of the conductive layer 2.
It is determined by controlling the conductivity of 3.

FIG. 8 is a diagram showing the dependence of the sheet conductivity (that is, the reciprocal of the sheet resistivity) of the resistive element R in this embodiment on the dose of the conductive layer 23, where the vertical axis is the sheet conductivity of the resistive element R. The rate [KΩ□ ^-1 ] and the horizontal axis indicate the dose of the conductive layer 23 [×10 ¹² cm ^-2 ]. As can be seen in the figure, the conductivity of the resistive element R in this example row has a neat proportional relationship with the dose of the ion implantation if the ion implantation for forming the conductive layer 23 is performed at a constant energy. In addition, the variation is small and the reproducibility is good. Therefore, the controllability is extremely good, and the production of GaAs integrated circuit devices is facilitated.

Note that in the above example, an example was given in which Si is used as the ion species for both base implantation and controlled implantation, but of both, the ion species used for base implantation is difficult to diffuse within the GaAs substrate. However, controlled implantation need not be limited to Si, and commonly used n-type impurities such as selenium (Se) may also be used.

Furthermore, in the above embodiment, an example was explained in which _ions are implanted with the surface of the implanted region exposed during ion implantation. Of course, it's okay to grow old. In this case, the relationship between implantation energy and implantation depth is naturally different, and in order to implant to a predetermined depth, it is necessary to increase the implantation energy compared to the above embodiment.

Further, in the above embodiment, an example was shown in which the basal injection was followed by the control injection, but either of these may be performed first, and there is no need to particularly limit the order.

(f) Effects of the invention As explained above, according to the present invention, semi-insulating
It is possible to create a desired resistance element on a GaAs substrate with good controllability and reproducibility, and therefore it is possible to stably and easily manufacture GaAs integrated circuit devices with desired characteristics, and the manufacturing yield is also reduced. improves.

[Brief explanation of the drawing]

1 and 2 are diagrams for explaining problems in the conventional semiconductor device manufacturing method, in which FIG. 1 is a sectional view of a main part showing the manufacturing process, FIG. 2 is a curve diagram showing the problems, Figures 3 to 6 are curve diagrams showing the principle of the present invention, Figure 7 is a cross-sectional view of essential parts showing one embodiment of the present invention in the order of manufacturing steps, and Figure 8 shows the effect of the above-mentioned embodiment. It is a curve diagram. In the figure, 1 is a semi-insulating GaAs substrate, 3,
5, 8, and 21 are ion implantation layers, 9 is an n ⁺ type source and drain region, 22 is a base implantation layer, 23 is a control implantation layer, and R is a resistance element.

Claims (1)

[Claims] 1. Approximately 0.05% of the area from the surface of the semi-insulating gallium/arsenic substrate is applied to a desired area of the semi-insulating gallium/arsenic substrate.
Silicon ions are distributed at a depth of 0.5 to 1.0×10 ¹² [cm ^-2 ] so that the peak of the concentration distribution is located at a depth of less than [μm].
The step of implanting at a dose of approximately 0.05 m
It is characterized by comprising a step of forming a resistive element, which includes a step of implanting n-type impurity ions so that the peak of the concentration distribution is located at a depth of [μm] or more, and a step of activating the implanted ions. A method for manufacturing a semiconductor device.