JPS6315584B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a liquid crystal display driving circuit capable of obtaining three or more potential levels, such as a dynamic type (dynamic or scanning type) liquid crystal driving circuit.

In recent years, in various digital electronic devices such as electronic desktop calculators, electronic circuits have been integrated with so-called complementary circuit configurations formed using both P-type and N-channel MOS transistors, and have also been integrated as display devices. Liquid crystal (LC)
There is a strong demand for lower power consumption and smaller size of the set. For example, electronic wristwatches that do not require battery replacement for one to two years have been commercialized, and calculators that can be used for about 1000 hours and do not require battery replacement have been developed.

On the other hand, due to the chemical properties of this LC, which has excellent low power consumption, it is important to apply alternating voltage and reduce the integrated voltage component to zero in order to extend its life. By the way, one electrode of a plurality of LC segments is made common (for example, for each display digit), and the other electrode of the segment is made common among different segment groups in which the one electrode is made common. In a dynamic drive method that selectively scans each group of shared segments in a time-division manner, the response speed of the LC is extremely slow compared to other display devices, so when dynamically driving the LC, three or more voltages are normally required. A drive signal with a level is required. For this reason, this driving signal is obtained from outside the integrated circuit, but this circuit consumes a large amount of power, making it impossible to take full advantage of the excellent low power consumption characteristics of the LC display device.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a voltage dividing circuit suitable for reducing power consumption and integrating circuits.

Embodiments of the present invention will be described below with reference to the drawings. Figure 1 shows an example of wiring the LC display section using the 1/2 duty, 1/2 prebias method, which is the simplest of the conventional LC dynamic drive methods. The case where one digit consists of 8 segments (7 segments arranged in a Japanese character shape and 1 segment for a decimal point) is shown. Figures 2a and b show display data in bit serial format (bit serial).
This is a conventional example of various timing waveform diagrams when processing is performed using serial) or digital serial.

In FIG. 2a, φ ₂ is a clock pulse that separates bits when one-digit data is bit serial, and is usually a read pulse. φ ₁ is generated in a pair with pulse φ ₂ and is a data read pulse for flip-flops, shift registers, etc.

T ₁ , T ₂ , T ₄ , and T ₈ are bit pulses that specify bit positions when 1-digit data consists of 4 bits;
d ₁ to d _o are digital pulses that designate digit positions when the calculation cycle is n digits. Figure 2b is LC
The scanning signals H ₁ and H ₂ and the signals used to generate these signals are shown. d _i is a digital pulse of a certain digit, φ _LA is a pulse indicating one display period, and its period is about 0.2 to 10 msec. Therefore, when the pulse d _i corresponds to φ _LA , d _i can become φ _LA . The pulse d _i designating a certain calculation digit is frequency-divided to a predetermined frequency to generate a polarity switching signal for the AC drive and a scanning designation signal designating a display section for dynamic display. In this example, 1/
Since the duty is 2, there is a 1/2 frequency division relationship between these two signals, and if E ₁ is the scan designation signal, E ₂ and E ₃ , which are divided by 1/2, become polarity switching signals. . That is, _E2 is for switching the polarity of the drive data signal of the LC segment, and _E3 is for switching the polarity of the scanning signal. Scanning signals H ₁ and H ₂ each require three levels. In other words, when the central part of the calculator (CPU) operates between two potential levels of voltage 0 [V] and -3 [V], and the maximum voltage amplitude of LC drive is 3.0 [V], the signals H ₁ , H The three levels of ₂ are usually 0 [V],
-1.5 [V] and -0.3 [V] are used. in this case,
Levels at both ends of signals H ₁ and H ₂ ie 0 [V] and -3
[V] scans the part that is the display timing,
This position is specified by the signal E ₁ and the scanning signal H ₁
is -3.0 [V] (low level) of signal E ₁ , scanning signal H ₂
is specified by 0 [V] (high level) of the signal _E1 .
Then, the level polarity of the scanning signals H ₁ and H ₂ is switched by the signal E ₃ . During the period when the display timing is not specified, the levels of the signals H ₁ and H ₂ are at the intermediate level -
It becomes 1.5 [V]. A ₁ is a data signal for segment driving, and this signal corresponds to signals H ₁ and H ₂ and has a voltage of 0 [V].
Whether the liquid crystal display is enabled or not is determined by whether the voltage is -3 [V] or not.
Figure 2b is the rightmost segment of the first digit in Figure 1.
This shows a state in which segment SE ₁ can be displayed and segment SE ₅ , which is the fifth segment from the right, is not displayed. The frequency of the data side polarity switching signal _E2 is 20Hz to 1kHz.
That's about it.

FIG. 3 is a block diagram showing an embodiment of the present invention, showing the configuration of a display voltage supply section that controls the voltage applied to both ends of each liquid crystal shown in FIG. 1 in accordance with the content to be displayed. In the following explanation, the waveforms shown in Figures 1 and 2 will be used, and low level (-3.0V)
Negative logic is used in which the level) is set to logic "1", or set, and the high level (0V level) is set to logic "0", or reset. In Fig. 3, 11 is an integrated circuit part, 12, 13 is a DC power supply (3
[V]) 14 is a terminal for supplying power, 10 is a power switch, and 15 and 16 are inputs for inputting data or giving function commands to the arithmetic circuit (not shown) of the calculator formed in the integrated circuit 11. The identification of the input signals to the input terminals 15, 16 is carried out, for example, by means of resistors 17, 18. Reference numeral 19 is a register that holds display data. When the operation digit is n digits and one cycle is operated serially, the BCD code in which 1 digit is bit "1", "2", "4", "8" operates serially. A pair of clock pulses φ ₁ and φ ₂ generated for each bit unit are used as shift pulses to connect 4×n clock pulses in cascade, and the output of the final stage is fed back to the input of the first stage. 20 is a storage circuit for outputting serial data in the shift register 19 as a parallel signal. 21 is a decoder which inputs the four data signals output from this circuit 20 and derives a signal indicating whether each segment is displayed or not for each digit; in this case, the LC of FIG.
Since each digit of the display section has eight segments with the same content, there are a total of eight outputs corresponding to these segments SE ₁ to SE ₈ , respectively. 22 is a circuit that scans segments SE ₁ and SE 5 using a scanning designation signal E ₁ to dynamically display the LC display section; when signal E 1 is at a low level, the output for segment SE ₅ is output, and when signal _{E 1} is at a high level, the output for segment SE ₅ is output. When , the output for segment SE ₁ is switched and derived. Although not shown in this case, SE ₂ and SE ₆ , SE ₃ and SE ₇ , SE ₄ and SE ₈
You can think about it in the same way. 23 is LC
A lighting state switching circuit 24 of the display section is a circuit for alternating the voltage applied to both ends of the LC segment. 25 is a shift register that shifts the output from the circuit 24 digit by digit, and is a cascade circuit of seven shift registers in which φ ₂ and T ₈ φ ₁ are clock pulses for shifting, or _{8 1} and T ₈ φ ₁ are clock pulses. It is. Reference numeral 26 consists of eight memory circuits whose input ends are connected to each input end or output end of each register of this circuit 25, and each output is connected to a respective corresponding terminal in FIG.

27 is a digital pulse d _i that specifies the digit of the calculation.
28 is a circuit for obtaining, for example, a clock pulse φ _LA which is generated once every display cycle. 29 is a frequency dividing circuit that receives a signal having the same period as the display cycle, for example, the output of the circuit 27, and outputs a scanning designation signal _E1 ; 30 is a frequency dividing circuit that receives this signal _E1 and outputs a switching signal _E2 ;
Reference numeral 31 denotes a delay circuit which uses signals such as T ₈ φ ₁ and φ _LA as clock pulses to delay the signal E ₂ by one display cycle, and this circuit 31 outputs a polarity switching signal E ₃ . 32 receives the signal E ₁ and the inverted signal of the output of the circuit 44 in an OR circuit 47, and in the voltage supply circuit 32' receives the signal E ₃ in FETs 34 and 34 ₂ to generate a scanning signal H ₁ having three potential levels. This is a circuit that does this. The scanning signal H ₂ also has ₁ as a scanning designation signal and can be obtained from a circuit corresponding to the circuit 32. The circuit 32 has a scanning signal _H1 of 3.
Voltages corresponding to two levels are supplied, among which the highest potential 0 [V] and the lowest potential -3 [V] are
Via FET34 ₂ , 33 and FET34 ₁ , 35,
Output terminal 1 of scanning signal H ₁ (corresponds to H ₁ in Figure 1)
00 to the liquid crystal display element 101, and the intermediate potential of -1.5 [V] is output to the voltage supply circuit 36.
from the output terminal 100 of the scanning signal H ₁ through the FETs 57 and 58 to the liquid crystal display element 10
Output to 1. When the above -3.0 [V] is applied from terminal 102 to output terminal 100, FET3
The gate inputs of 4 ₁ and 35 are at a high level (0 [V]), but at this time, the output of the OR circuit 47 is at a low level (-3.0 [V]), and FETs 34 ₂ , 57, and 58 are off. When the above 0 [V] is applied from the ground terminal 103 to the output terminal 100, FET33,3
The gate input of ₄₂ is at a low level, but at this time the output of the inverter 82 is at a high level, and the FET34
₁ , 57, and 58 are off. Also, the above -1.5 [V]
When is applied to the terminal 100, a low level is applied to the FET 57 and a high level is applied to the gate input of the FET 58, but at this time, the FETs 35 and 33 are off. The voltage supply circuit 36 includes resistors R ₁ and R ₂ (R ₁ =
_R2 ) is provided between the -3V power supply terminal 102 and the ground terminal 103, and the resistor _R1 is connected between the connection point (output terminal 104) of the resistors R1 and _R2 and the power supply terminal ₁₀₂ .
Connect N-channel FET61 in series to output terminal 1.
04 and the ground terminal 103, a P channel FET 62 is connected in series to a resistor R ₂ . 70 is an output capacitor formed at the output terminal 104. FET6
1 and 62 are turned on by the output of the AND circuit 63, the divided potential of -1.5V obtained between the resistors R ₁ and R ₂ is as follows:
It is held by the output capacitance 70 and the capacitance of the liquid crystal display element 100 via FETs 57 and 58, and is
It is maintained dynamically even when 62 is turned off.

Conventionally, it was usual to obtain a voltage of -1.5 [V] from outside the integrated circuit via a voltage converter, but it can be seen that with this circuit, a signal having three levels can be obtained within the integrated circuit.

40 is a timing circuit for reducing power consumption in the voltage supply circuit 36, and is set for a set time after an input signal is introduced from the input terminal 15 or 16, or after a series of logical operations are completed by the input signal. state. Methods for this purpose include (a) sequentially dividing a certain pulse using a frequency divider circuit to obtain a pulse with the set time width, or (b) using a memory circuit connected in cascade with shift registers and a full adder or full adder. There are methods of measuring time by adding or subtracting data at regular intervals by combining subtractors and changing the contents of the memory circuit, but in Fig. 3, as shown in Fig. 4, the time is measured by 1/2. 1/2 with 11 stages of frequency divider circuits connected in cascade
A frequency dividing circuit 41 with a frequency division of 0.048 was used. This circuit 41
Since the switching signal _E2 has the longest period in the logic unit and LC drive circuit of the calculator, this signal was used as the input for convenience. The period of this E ₂ is generally about 1 to 50 m sec, but here
20m sec. Further, the setting time of the above-mentioned clock circuit 40 may be any time sufficient for a human being to read or write the data displayed on the LC display after executing a logical operation, and is set to about 20 seconds, for example. . 42 is a circuit that generates a signal instructing the clock circuit 41 to start timing, and is connected to the input terminal 15 or 16.
When an input signal is introduced from the circuit, an output may be generated in response to the input signal, but it may also be a circuit that outputs a constant pulse after executing a series of logical operations. That is, the circuit 42 sets all stages of the frequency divider 41 of 1/2048 frequency division. The signal E ₂ is supplied to the input of the circuit 41 via the input prohibition circuit 43 when the output of the circuit 41 is in the set state. This signal E ₂
has a period of 20 m sec, and since the output timing of the circuit 42 is uncertain within one period of the signal _E2 , the output of the counting circuit 41 is set by the output of the circuit 42, as shown in FIG. Then signal E ₂
It will be reset within 1024 cycles. That is, when input signals are input to input terminals 15 and 16, the output of circuit 41 is set for 20.46 to 20.48 seconds. Then, unless a new input is given to the input terminals 15, 16 again, the inhibition circuit 43 prohibits the frequency division input, so that the reset state is maintained until a new input signal is given to the terminals 15, 16. A circuit 44 delays the set state of the clock circuit 41 by one display period, and is composed of a shift register using T ₈ φ ₁ and φ _LA as clock pulses.

The output of the clock circuit 40 is inverted by an inverter 45, ORed with the output of the switching circuit 22, and introduced into the exclusive OR circuit 24. Therefore, when the output of the clock circuit 40 is reset, the input of the circuit 24 becomes a display state, that is, a low level, regardless of the output of the decoder 21 or the data content in the shift register 19, so all of the LC drive signals _A1 to _A8 are clocked. circuit 4
When 0 is reset, it becomes the same as the polarity switching signal _E3 within one display period, that is, within 5 msec.

Switching elements 61, 6 of voltage supply circuit 36
2 is supplied with the output of the delay circuit 44 via the AND circuit 63, the elements 61 and 62 are turned on, and a -1.5 [V] signal is derived from the output section of the potential supply circuit 36. During the ON period of these elements 61 and 62, the segment drive data signal is transmitted to the storage circuit 26.
The results of the arithmetic processing are output to the LC display section during this period.

The values of resistors R ₁ and R ₂ need to be set to large values in order to minimize the current consumption when FETs 61 and 62 are on. 10~
It is set to about 200kΩ. By operating the voltage supply circuit 36 only when it is desired to display the LC display device in this manner, the power consumption in this portion can be reduced significantly. In addition, since the alternating voltage can be properly applied to all segments during periods other than the LC display period, there is no problem with the LC lifespan. Furthermore, since the voltage supply circuit 36 is formed within the integrated circuit 11, it is also possible to reduce the number of individual components used outside the circuit. In addition, the circuit configuration of this embodiment can limit the power consumption in the circuit due to forgetting to turn off the power switch 10 to power consumption other than the voltage supply circuit 36, and also stops the operation of the equipment and turns off the power switch unless necessary. This is effective for the purpose of improving the reliability of devices such as calculators by omitting the power switch 10 by performing an action equivalent to shutting off the power switch.

Also, as mentioned above, segments SE ₂ and SE ₆ ,
If the segment drive signals for SE ₃ and SE ₇ and SE ₄ and SE ₈ are configured in the same manner as for segments SE ₁ and SE ₅ , all segments of the display section in FIG. can be left in the state.

In the above explanation of FIG. 3, we have used an example of displaying data after the execution of calculations on a calculator, etc. However, if you simply want to display the data of the shift register 19 without executing calculations, you can use the input terminal An input terminal similar to 15 or 16 may be provided to set the clock circuit 40 via the circuit 42 with a future input signal, or alternatively, as shown in FIG.
A specific timing pulse, for example, d _i , may be applied from , and the AND circuit 46 may inhibit only the timing of d _i among the signals introduced into the arithmetic circuit.

In the present invention, the values of the resistors R ₁ and R ₂ are not limited to those in the embodiment, and the present invention can be applied to various applications such as obtaining a voltage different from that in the embodiment by appropriately setting the ratio of these resistance values. is possible.

Therefore, according to the present invention, a liquid crystal drive signal having three levels can be obtained within the same integrated circuit. In addition, switching means is inserted in series with the resistor series circuit provided between the power supply terminals so that the means can be turned on and off, thereby reducing power consumption. Since the liquid crystal display driving circuit can be incorporated into an integrated circuit together with the circuit shown in FIG. Further, in the present invention, the divided potential generated by the first voltage supply circuit that performs voltage division is supplied to a large number of liquid crystal drive circuits, and power is supplied to each electrode of the liquid crystal through the drive circuits. Therefore, since the present invention drives a large number of liquid crystal electrodes with a small number of voltage dividing circuits,
Can be driven with a small number of voltage dividing circuits. Therefore, it is possible to particularly reduce power consumption. In addition, even when a divided potential is being generated, the DC current between the power supply and ground is limited to a certain period at the start of the display cycle, and the DC current is extremely small during other periods to reduce power consumption. There is. Therefore, it is possible to provide a liquid crystal display drive circuit that matches the low power consumption characteristics of liquid crystals.
Further, in the present invention, since a pair of switches are included in the first voltage supply circuit that performs voltage division using resistors, a large number of liquid crystal display sections can be driven by the pair of switches, and the number of elements used can be reduced. Furthermore, since the present invention operates the first voltage supply circuit itself that generates the divided potential intermittently, the power consumption is lower than in the conventional case where the voltage dividing circuit is left as is and each liquid crystal display itself is intermittently driven by a switch. is possible.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional LC display unit, Figure 2 is a signal waveform diagram used in a conventional LC display device,
FIG. 3 is a circuit diagram of one embodiment of the present invention, and FIG. 4 is a signal waveform diagram of the same circuit. R ₁ , R ₂ ... Resistor, 32', 36 ... Voltage supply circuit, 33, 34 ₁ , 34 ₂ , 35, 57, 58, 6
1, 62... Switching means, 47... OR circuit, 63... AND circuit, 70... Output capacity, 8
1-83...Inverter, 100...Liquid crystal drive voltage supply terminal, 101...Liquid crystal display element, 102,
103...Voltage supply terminal (power supply terminal), 104...
...Series connection point of R ₁ and R ₂ .

Claims (1)

[Claims] 1 A first resistor R 1 and a second resistor R ₂ connected in series between one voltage supply terminal (102 in FIG. 3) and the other voltage supply terminal ₁₀₃ , and the first resistor R ₁ and a first resistor R ₁ connected in series with the first resistor R ₁ between the series connection point 104 of the second low resistance R 2 and the one voltage supply terminal 102 and turned on and off periodically.
switching means 61 and said series connection point 10
4 and the other voltage supply terminal 103.
a second switching means 62 connected in series with the resistor R ₂ and turned on and off periodically;
When the switching means is on, the first and second switching means are turned on.
A capacitor 70 that holds the divided potential obtained between the resistors of
a first voltage supply circuit 36 having; third switching means 57, 58 having one end connected to the series connection point 104 and the other end connected to the liquid crystal drive voltage supply terminal 100; terminal 1
02 and the liquid crystal drive voltage supply terminal 100, fourth switching means 34 ₁ , 35;
a second voltage supply circuit 32' having fifth switching means 33, ₃₄₂ connected between the other voltage supply terminal 103 and the liquid crystal drive voltage supply terminal 100;
and a liquid crystal display element 101 connected to the display device 101, and when the third switching means 57, 58 and the fifth switching means 33, ₃₄₂ are off and the fourth switching means ₃₄₁ , 35 are on, the One voltage supply terminal 102 is connected to the liquid crystal display element 101.
voltage is supplied from the third switching means 57, 58 and the fourth switching means 34 ₁ ,
35 is off and the fifth switching means 33, 34
₂ is on, the voltage from the other voltage supply terminal 103 is supplied to the liquid crystal display element 101, the fourth and fifth switching means are turned off, and the third switching means 57 and 58 are turned on. When the first and second switching means are on, the potential from the first voltage supply circuit 36 is supplied to the liquid crystal display element 101, and even when the first and second switching means are off, the potential is supplied to the liquid crystal display element 101. The divided potentials are dynamically held in the capacitor 70 and the liquid crystal display element 101, and the first and second potentials are dynamically held.
voltage supply circuit and third switching means 5
Reference numerals 7 and 58 indicate liquid crystal display drive circuits, which are located within the same integrated circuit.