JPS63795B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a liquid crystal display device having an improved method of supplying voltage to a liquid crystal display portion having a large number of liquid crystal segments.

In recent years, in various digital electronic devices such as electronic desktop calculators, electronic circuits have been integrated with so-called complementary circuit configurations formed using both P-type and N-channel MOS transistors, and have also been integrated as display devices. Liquid crystal (LC)
There is a strong demand for lower power consumption and smaller size of the set. For example, electronic wristwatches that do not require battery replacement for one to two years have been developed, and calculators that do not require battery replacement for approximately 1000 hours have been developed.

However, in conventional calculators, etc., the power switch is closed when in use and opened when not in use, but this switch must be opened and closed manually, making it difficult to distinguish between the use of the device and the next use. There are cases in which power is wasted due to unnecessary efforts such as not having to open the switch between uses, or forgetting to open the switch even when not in use. In order to eliminate this problem, attempts have been made to stop the driving clock pulse after a certain period of time after using the device and perform an operation equivalent to turning off a switch. How to handle LC display remained a difficult problem.

Figure 1 is a circuit diagram showing a conventional LC display section, Figure 2
The figure shows the same timing chart, which will also be used in the embodiments of the present invention described later. Here, Figure 1a shows an example of wiring the LC display section using the 1/2 duty, 1/2 prebias method, which is the simplest of the LC dynamic drive methods. The case where one digit consists of 8 segments (7 segments arranged in the Japanese character shape and 1 segment for the decimal point) is shown. 1st
Figure b is an equivalent circuit diagram of the liquid crystal segment shown in figure a. Figure 2 a and b show display data in bit serial and digit serial format.
FIG. 4 is a diagram of various timing waveforms when processing is performed.

In FIG. 2a, φ ₂ is a clock pulse that separates bits when one-digit data is bit serial, and is usually a read pulse. _φ1
is generated in pairs with pulse φ ₂ , and the flip-flop,
This is a data read pulse for shift registers, etc.
T ₁ , T ₂ , T ₄ , and T ₈ are bit pulses that specify the bit position when 1-digit data consists of 4 bits, d ₁
~d _o is a digital pulse that specifies the digit position when the calculation cycle is n digits. FIG. 2b shows the LC scanning signals H ₁ , H ₂ and the signals used to generate these signals. d _i is a digital pulse of a certain digit, φ _LA is a pulse indicating one display period, and its period is about 0.2 to 10 msec. Therefore, the pulse d _i is φ _LA
When corresponding to , d _i can be made into φ _LA .
The pulse d _i designating a certain calculation digit is frequency-divided to a predetermined frequency to generate a polarity switching signal for the AC drive and a scanning designation signal designating a display section for dynamic display. In this example, the duty is 1/2, so the frequencies between these two signals have a relationship of 1/2 frequency division, and if E ₁ is the scan designation signal, E ₂ and E ₃ becomes the polarity switching signal. That is, _E2 is for switching the polarity of the drive data signal of the LC segment, and _E3 is for switching the polarity of the scanning signal. Scanning signals H ₁ and H ₂ each require three levels. In other words, the central CPU of the calculator has a voltage of 0.
When operating between two potential levels of [V] and -3 [V], and the maximum voltage amplitude of LC drive is 3.0 [V],
The three levels of signals H ₁ and H ₂ are normally 0 [V] and -1.5
[V], -3.0 [V] is used. In this case, the signal
Levels at both ends of H ₁ and H ₂ , i.e. 0 [V] and -3 [V]
This position is specified by the signal E ₁ , the scanning signal H ₁ is -3.0 [V] (low level) of the signal E ₁ , and the scanning signal H ₂ is the 0 of the signal E ₁ . It is specified by [V] (high level). Then, the level polarity of the scanning signals H ₁ and H ₂ is switched by the signal E ₃ . During the period when the display timing is not specified, the level of signals H ₁ and H ₂ is -1.5 of the intermediate level.
It becomes [V]. A ₁ is a data signal for segment driving, and this signal corresponds to signals H ₁ and H ₂ and has a voltage of 0 [V].
Whether the liquid crystal display is enabled or not is determined by whether the voltage is -3 [V] or not.
FIG. 2b shows a state in which the rightmost segment SE ₁ of the first digit in FIG. 1a can be displayed, and the fifth segment SE ₅ from the right is not displayed. The frequency of the data side polarity switching signal _E2 is 20Hz to 1k.
It is about Hz.

However, the present invention was made in view of the above-mentioned problems, and due to its chemical characteristics, the LC, which has excellent low power consumption, is applied with an alternating current voltage (alternating voltage) to eliminate the integrated voltage component. Focusing on the important point that increasing the lifespan of the LC is important for extending the life of the LC, the present invention aims to provide a liquid crystal display device that can extend the life of the LC while reducing the power consumption of the device.

An embodiment of the present invention will be described below with reference to the drawings. Although FIG. 3 is a circuit configuration diagram of the same embodiment, in the following explanation, the low level (-3.0V level) is assumed to be a logic "1" in correspondence with the waveform examples of FIGS. 1 and 2. That is, negative logic is used in which the set and high level (0V level) are logic "0", ie, reset. Third
In the figure, 11 is an integrated circuit part, 12 and 13 are terminals for supplying power to this integrated circuit from a DC power supply (3 [V]) 14, 10 is a power switch, 15,
Reference numeral 16 denotes an input terminal for supplying data input or function commands to an arithmetic circuit (not shown) of the calculator formed in the integrated circuit 11. As means for introducing input to these input terminals 15 and 16, each input There are two methods: via a switch placed between the terminal and the -3 [V] terminal, or by supplying digital pulses or bit pulses via a switch placed at the input terminal. For example, the input signals to the input terminals 15 and 16 are identified by resistor 1.
7, 18. Note that instead of the resistors 17 and 18, equivalent resistances using FETs may be used, or the FETs may be made conductive at regular intervals to dynamically set the level when there is no input signal. 19
is a register that holds display data, and the calculation digit is n
Each digit constitutes one period, and one digit is a bit “1”, “2”,
When “4” and “8” BCD codes operate serially, 4×n are connected in cascade using a pair of clock pulses φ ₁ and φ ₂ generated for each bit as shift pulses, and the final stage output is It is fed back to the first stage input. 20 latches the data shifted bit by bit in the shift register 19 once for each digit and outputs the serial data of "8" of "1", "2", and "4" as a parallel signal. It is a memory circuit for Reference numeral 21 denotes a decoder which receives the four data signals output from this circuit 20 and derives a signal indicating whether a segment is displayed or not for each digit. Since each digit has 8 segments with the same content,
It has a total of eight outputs corresponding to these segments SE ₁ to SE ₈ , respectively. It is assumed that a low level signal is derived as this output when display is desired. This decoder 21 introduces an inverted signal of the signal F that is set only during execution of a series of logical operations, and by disabling the decoder function, changes in data in the shift register 19 during execution of operations will not appear on the LC display section. Alternatively, all digits can be hidden. 22 indicates the segments SE ₁ and SE ₅ by the scanning designation signal E ₁ in order to dynamically display the LC display section.
When the signal _E1 is at a low level, the output for the segment _SE5 is switched, and when the signal _E1 is at a high level, the output for the segment _SE1 is switched and derived. Although not shown in this case, SE ₂ and SE ₆ ,
SE ₃ and SE ₇ and SE ₄ and SE ₈ can be considered in the same way. 23 is a lighting state switching circuit for the LC display section;
24 is a circuit for alternating the voltage applied to both ends of the LC segment. This alternating current (AC drive) circuit has a polarity switching signal E ₂ and circuits 22, 2.
Take the exclusive OR with the signal derived from 3 and obtain the signal
When the signal E ₂ is at a low level, the signal to be displayed is output as a high level signal, and when the signal E ₂ is at a high level, the signal to be displayed is output as a low level signal. 25 is a shift register that shifts the output from the circuit 24 digit by digit, and is a cascade circuit of seven shift registers in which φ ₂ and T ₈ φ ₁ are clock pulses for shifting, or _{8 1} and _{8 1} are clock pulses. . 26 is an 8 whose input terminal is connected to each input terminal or output terminal of each register of this circuit 25.
Each output is connected to a corresponding terminal in FIG. 1a. Each memory circuit of the circuit 26 stores the state outputted from the circuit 25 during the display cycle, for example, the final state of the period α ₁ , α ₂ , β ₁ , β ₂ in FIG. It performs LC drive while maintaining the same level.
The LC drive timing from circuit 26 and the operating state of circuits before circuit 26 or 25 differ by one display cycle period.

27 is a digital pulse d _i that specifies the digit of the calculation.
28 is a circuit for obtaining, for example, a clock pulse φ _LA which is generated once every display cycle. 29 is a frequency dividing circuit that receives a signal having the same period as the display cycle, for example, the output of the circuit 27, and outputs a scanning designation signal _E1 ; 30 is a frequency dividing circuit that receives this signal _E1 and outputs a switching signal _E2 ;
Reference numeral 31 denotes a delay circuit which uses signals such as T ₈ φ ₁ and φ _LA as clock pulses to delay the signal E ₂ by one display cycle, and this circuit 31 outputs a polarity switching signal E ₃ . 32' receives the signal E ₁ and also receives the signal E ₃
This is a circuit that receives the signal H1 in an OR circuit 47 and generates a scanning signal _H1 having three potential levels. Scanning signal H ₂
Also, ₁ is used as the scanning designation signal and the circuit 32
can be obtained from the corresponding circuit. circuit 32
are supplied with voltages corresponding to three levels of the scanning signal _H1 , among which the highest potential 0 [V] and the lowest potential -3 [V] are applied to FETs 32, 33 and 34, 3.
The intermediate potential -1.5 [V] is applied from the voltage divider circuit 36 and is outputted via FETs 37 and 38. The voltage divider circuit 36 is a resistor
The series circuit of R ₁ , R ₂ (R ₁ = R ₂ ) and the FET (switching element) 39 inserted in series with this are -3.0
[V] Provided between the power supply and ground, with the connection point of resistors R ₁ and R ₂ as the output terminal. Here, the FET 39 was arranged between the output end and the ground, so the FET channel type was used. When this FET 39 is placed between the -3 [V] power supply and the output terminal, it is preferable that the FET is an N-channel type. As a result of the above, conventionally it was normal to obtain a voltage of -1.5 [V] from outside the integrated circuit via a voltage converter, but with this circuit it is possible to obtain a signal with three levels within the integrated circuit. I understand.

40 is a timing circuit for reducing power consumption in the circuit 36, and is set to the set state for a set time after an input signal is introduced from the input terminal 15 or 16, or after a series of logical operations are completed by the input signal. becomes. Methods for this include (a) sequentially dividing a certain pulse using a frequency divider circuit to obtain a pulse with the set time width, or (b) using a memory circuit with cascaded shift registers and an adder or full subtraction. Combine instruments and add or subtract data at regular intervals,
There are methods of measuring time by changing the contents of the above-mentioned memory circuit, but in Fig. 3, 1/2048 frequency division is performed by cascading 11 stages of 1/2 frequency divider circuits as shown in Fig. 4. Circuit 41 was used. As the input to this circuit 41, the switching signal _E2 has the longest cycle in the logic operation section of the calculator and the LC drive circuit, so this signal was used for convenience. The period of this E ₂ is 1~50m
sec is common, but here it is set to 20 msec. Further, the setting time of the above-mentioned clock circuit 40 may be any time sufficient for a human being to read or write the data displayed on the LC display after executing a logical operation, and is set to about 20 seconds, for example. . 10th
The figure is an example of what was explained in section (b) above, and B ₁ ′ ~
B _o ' is a cascade circuit of shift registers, a is a full adder, and f is an R-S flip-flop circuit.
42 is a circuit that generates a signal instructing the clock circuit 41 to start timekeeping; when an input signal is introduced from the input terminal 15 or 16, an output may be generated in response to the input signal; A circuit that outputs a constant pulse after execution may be used. That is, the circuit 42 sets all stages of the frequency divider 41 of 1/2048 frequency division. When the output of the circuit 41 is set to the input of the circuit 41, the input prohibition circuit 43 is activated.
A signal E ₂ is supplied via. This signal E ₂ is 20
msec period, and since the output timing of the circuit 42 is undefined within one period of the signal _E2 , the output of the counting circuit 41 is as shown in FIG.
1024 of signal E ₂ after setting by the output of
It will be reset within the cycle. That is, when input signals are input to input terminals 15 and 16, the output of circuit 41 is set for 20.46 to 20.48 seconds. Then, unless a new input is given to the input terminals 15 and 16 again, the inhibition circuit 43 prohibits the frequency division input.
The reset state is maintained until a new input signal is received at terminals 15 and 16. 44 is the clock circuit 4
The set state of 1 is delayed by 1 display period and converted into a scanning signal.
This circuit synchronizes the signal supply timing with the LC drive signals A ₁ to A ₈ and is composed of a shift register using T ₈ φ ₁ and φ _LA as clock pulses.

The output of the clock circuit 40 is inverted by an inverter 45, ORed with the output of the switching circuit 22, and introduced into the exclusive OR circuit 24. Therefore, when the output of the clock circuit 40 is reset, the input of the circuit 24 becomes a display state, that is, a low level, regardless of the output of the decoder 21 or the data content in the shift register 19, so all of the LC drive signals _A1 to _A8 are clocked. circuit 4
When 0 is reset, it becomes the same as the polarity switching signal _E3 within one display period, that is, within 5 msec.

The output of the delay circuit 44 is supplied to the switching element 39 of the voltage dividing circuit 36, and when the element 39 is turned on, a -1.5 [V] signal is derived at the output section of the circuit 36. The on period of this element 39 coincides with the period during which the segment drive data signals are respectively derived from the storage circuit 26, and the result of the arithmetic processing is output to the LC display section during this period.
On the other hand, when the output of the delay circuit 44 is reset,
Since the switching element 39 is turned off, the dividing circuit 36 is cut off and its output _is -
It becomes 3 [V]. At this time, the designation signal E ₁ for the scanning signal H ₁ is logically determined by the inverted output of the circuit 44 and the OR circuit 47, so that the waveform of the scanning signal H ₁ is output as an inverted pulse of the signal E ₃ . Therefore, when the clock circuit 40 is reset, the scanning signal
H ₁ is the inverted signal of signal E ₃ , scanning signals A ₁ to _{A 8} are the signals
This becomes the same signal as _E3 , and all LC segments driven by this signal _A1 to _A8 enter the display state. The remaining LC segments can be considered similarly. Of course, at this time, since the polarity of the voltage applied to each LC segment is alternating, no matter how long the reset time of the clock circuit is, there will be no problem with the LC life.

The values of resistors R ₁ and R ₂ need to be set to large values in order to minimize the current consumption when FET 39 is on, but it is necessary to set them to large values, taking into account the parasitic capacitance of several tens of pF to 1000 pF that the LC display device has. 10~200kΩ
It is set to a certain degree. By operating the voltage dividing circuit 36 only when it is desired to display an image on the LC display device in this manner, the power consumption in this portion can be greatly reduced.
In addition, since the alternating voltage can be properly applied to all segments during periods other than the LC display period, there is no problem with the LC lifespan. Furthermore, since the voltage divider circuit 36 is formed within the integrated circuit 11, it is also possible to reduce the number of individual components used outside the circuit.
In addition, the circuit configuration of this embodiment is that of the power switch 10.
The power consumption in the circuit due to forgetting to turn off the voltage divider circuit 36 can be limited to the power consumption outside the voltage divider circuit 36, and the operation of the equipment can be stopped unless necessary, and the power can be turned off by shutting off the power switch. This is effective for the purpose of omitting the switch 10 and improving the reliability of devices such as calculators.

Also, as mentioned above, segments SE ₂ and SE ₆ ,
If the segment drive signals for SE ₃ and SE ₇ and SE ₄ and SE ₈ are configured in the same manner as for segments SE ₁ and SE ₅ , all segments of the display section in FIG. It can be left visible. On the other hand, the segment display control circuit 23
As shown in FIG. 5a, if the clock circuit 40 is replaced with a circuit that transmits the output of the circuit 22 to the circuit 24 only when it is set, and prohibits signal transmission at other times,
After resetting the clock circuit 40, all LCDs display the maximum -
Only a voltage of 1.5 [V] is applied, and therefore all liquid crystal segments can be put into a non-display state. Furthermore, as shown in FIG. 5b, when the circuit 40 is reset, the signal transmission from the circuit 22 to the circuit 24 is prohibited, and if, for example, the signal d _i is transmitted to the circuit 24 only in a specific segment, then after the circuit 40 is reset, Only specific segments, for example segments SE ₁ and SE ₅ , can be made visible. It is convenient to display all segments or only a specific segment after resetting the clock circuit 40 as described above, since it can be identified that power is being supplied to a device such as a calculator.

In addition, if you want to stop the operation of only the LC display device and make all segments invisible, use circuit 3 in Figure 3.
The output of the circuit 31 supplied to the delay circuit 44
By setting the output in the reset state,
The alternation of the LC drive signals is stopped and fixed to, for example, the ground level, and the segment signals A ₁ to A ₈ , B ₁ to
B ₈ , C ₁ -C ₈ , D ₁ -D ₈ can be obtained by resetting the memory circuit 26 in the reset state of the delay circuit 44, or by resetting the output of the memory circuit 25 in the reset state of the circuit 44. is applied to the circuit 26 to obtain each segment signal, these signals also stop alternating and become, for example, ground level, and all LC
Segments can be hidden. Further, as a method for this purpose, as shown in FIG. 6, if the output of the display control circuit 24 is inhibited by an AND circuit 51 during the reset period of the circuit 40, the segment drive signal can be easily fixed at the ground level. Furthermore, the alternation of the scanning signals H ₁ and H ₂ can be stopped by the OR circuit 52, and can be fixed at the ground level.

In addition, if a certain period of time elapses after a keystroke is made on a calculator, etc., the device will stop sequential arithmetic operations in part or all of the device until a new keystroke is made, or cut off the power supply to reduce power consumption. If you do so, stop alternating the LC drive signals and
Making the potential difference between both ends of the segment zero is
This is advantageous in terms of LC lifespan and low power consumption. In this case, the time measurement circuit 40 may be used as a time measurement circuit for obtaining a certain period of time after the key input. Then, in order to reset the clock circuit and stop the sequential operation in the circuit of FIG. 3 or 6, the shifting clock pulses may be fixed at one level or the power supply to the device may be stopped.
However, if the memory element to which this shift clock pulse is supplied is of a dynamic type, the seventh
In order to fix the potential of this storage element 53 as shown in FIG.
When a large number of the _above -mentioned memory elements are connected, as shown _{in FIG} . It may be given as a clock pulse for shifting the memory element. on the other hand,
If the power supply to the device is to be stopped by resetting the clock circuit 40, the power supply to the circuits 26, 32', 32'', etc. may be stopped.

In the above explanation of FIG. 3, we have used an example of displaying data after the execution of calculations on a calculator, etc. However, if you simply want to display the data of the shift register 19 without executing calculations, you can use the input terminal An input terminal similar to 15 or 16 may be provided to set the clock circuit 40 via the circuit 42 with a future input signal, or alternatively, as shown in FIG.
A specific timing pulse, for example, d _i , may be applied from , and the AND circuit 46 may inhibit only the timing of d _i among the signals introduced into the arithmetic circuit.

FIG. 8 shows a modification of the voltage dividing circuit 36, in which switch elements 61 and 62 are connected in series with resistors R ₁ and R ₂ . A circuit 44 is connected to the gate of element 62.
Since the inverted output is given to the element 61, the elements 61 and 62 are turned on only when the circuit 44 is set, and send out a -1.5 [V] output, and when the circuit 44 is reset, the -1.5 [V] output is output. becomes indeterminate. However, at the time of the above reset, the output potential of the circuit 44 is not used in the circuit 32, so there is no problem.

FIG. 9 is a modification of FIG. 8, in which an AND circuit 63 calculates the logic between the output of the circuit 44 and a clock pulse of a constant period, for example, _T1 . Therefore, a -1.5 [V] output is sent out only when these logics are established. Even if the pulse T ₁ is not established and the elements 61 and 62 are turned off, the LC connected through the circuit 32 is capacitive and its leak resistance is 1 to 200 MΩ or more, so the output is not output when T ₁ is established. -1.5 [V] of the output of the circuit 32 is dynamically held in the output capacitor, LC capacitor, of this circuit. With this circuit, power consumption is further reduced than in the case of FIG.

In each of the above embodiments, the case of 1/2 duty and 1/2 pre-bias is explained as the circuit for driving the LC, but it may also be 1/3 duty, 1/4 duty, etc. A potential different from that in the embodiment may be obtained by appropriately setting a resistance ratio such as _R1 and _R2 . Also, circuit 2 in Figure 3
The four outputs of the two parts are further converted into bit signals T ₁ , T ₂ ,
By scanning with T ₄ and T ₈ , the circuits 23 and 24
It can also be implemented in an LC drive circuit having a configuration in which the following are integrated into one.

As explained above, according to the present invention, after the set time of the timer circuit has elapsed, the operation of the liquid crystal drive voltage generation circuit is stopped and the LC is driven alternately.
It is possible to extend the lifespan of the LC and reduce power consumption, and the handling of the LC display is also possible when an operation equivalent to turning off the power switch is performed after a certain period of time after using a device such as a calculator. It becomes possible to implement it well. In addition, since a voltage level (for example, a pre-bias voltage level) between two voltages supplied from outside the integrated circuit is obtained within the integrated circuit chip, the number of external pins (terminals) of the integrated circuit can be reduced. It is.

[Brief explanation of the drawing]

Fig. 1a is a circuit diagram showing a conventional LC display section, Fig. 1b is an equivalent circuit diagram of the same part, Fig. 2a and b are the same timing chart, and Fig. 3 shows the configuration of an embodiment of the present invention. FIG. 4 is a timing chart of the same, and FIGS. 5 to 10 are circuit diagrams for explaining other embodiments of the present invention. SE ₁ to SE ₈ ...LC segment electrode, 23...Display state switching circuit, 24...AC drive circuit, 26
...Segment drive circuit, 32, 32'...Scanning signal generation circuit, 36...Voltage division circuit, 40...
Timing circuit, 41... Frequency dividing circuit.

Claims (1)

[Scope of Claims] 1. A liquid crystal display section including a large number of liquid crystal segments, and a third voltage level between the first voltage level and the second voltage level used for driving the liquid crystal display section. A series circuit of a plurality of resistors is provided between the supply terminals of the first and second voltages, and a switch element is inserted in series with the series circuit, since the voltage is generated by the voltage dividing resistor between the first and second voltage levels. a liquid crystal driving voltage generating circuit; a liquid crystal driving circuit that alternately drives the liquid crystal segments according to the content to be displayed using the first to third voltage levels; and a liquid crystal driving circuit that clocks a set time when a timing operation start signal is given. and means for turning off the switch element to stop the operation of the liquid crystal driving voltage generating circuit after a set time of the timing circuit has elapsed, and the liquid crystal driving voltage generating circuit and the liquid crystal driving circuit are integrated into the same integrated circuit. After the set time of the timer circuit has been counted, the switch element is turned off to stop the operation of the liquid crystal drive voltage generation circuit, and at the same time to turn off one of the two voltage levels supplied to the liquid crystal drive voltage generation circuit. 1. A liquid crystal display device comprising a configuration for continuing alternating driving of the liquid crystal after outputting the liquid crystal. 2. A liquid crystal display section provided with a large number of liquid crystal segments, and a third voltage level between the first voltage level and the second voltage level used for driving the liquid crystal display section. A liquid crystal drive voltage generating circuit comprising a series circuit of a plurality of resistors provided between the first and second voltage supply terminals and a switch element inserted in series thereto to generate a voltage at a voltage dividing resistor between voltage levels; , a liquid crystal driving circuit that alternately drives the liquid crystal segments according to the content to be displayed using the first to third voltage levels; a timing circuit that measures a set time when a timing operation start signal is applied; means for turning off the switch element to stop the operation of the liquid crystal drive voltage generation circuit after a set time of the timer circuit has elapsed, and the liquid crystal drive voltage generation circuit and the liquid crystal drive circuit are integrated in the same integrated circuit. , after measuring a set time of the timer circuit, the switch element is turned off to stop the operation of the liquid crystal drive voltage generation circuit, and the output of the liquid crystal drive voltage generation circuit is supplied to the liquid crystal drive voltage generation circuit at two voltage levels. 1. A liquid crystal display device, characterized in that the liquid crystal display device is configured to perform a specific display by applying alternating voltages having a phase shift of 180° to some of the opposing electrodes sandwiching the liquid crystal.