JPS631622B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to branch instructions that are most frequently used in electronic computer programs.

In order to create efficient programs in computer programs, parts that can be controlled in common perform the same processing, and parts that require different control are branched out to perform different processing.
There is a loop processing method that repeats the same process over and over again. The above two methods are the most effective and frequently used methods when creating programs for electronic computers, and branch instructions are often used in this case.
Therefore, it is no exaggeration to say that the function of branch instructions influences the function of electronic computers. Among branch instructions, there are instructions that branch freely to all addresses in the program memory, and instructions that branch within a limited range. The former has no restrictions on branch destinations, but requires multiple instruction codes, resulting in poor program efficiency. Although the latter has restrictions on branch destinations, it has the characteristic that the instruction code is generally only one word and program efficiency is good.

The frequency of branching over a wide range of program memory is relatively low, and branching over a narrow range is overwhelmingly the case, so the function of the latter branch instruction is very important.

One of conventional branch instructions with a limited branch range is an intra-page branch instruction. That is, the program memory address is divided into a plurality of small blocks, each block consisting of the same number of consecutive addresses. The small block is called a page, and the intra-page branch instruction is an instruction that branches to each address within the current page, and branching outside the page is not possible.

FIG. 1 shows the instruction code and program counter of the intra-page branch instruction. 1a is a part of the instruction code indicating an intra-page branch instruction, and when the electronic computer decodes the instruction part 1a, the address data part 1b of the instruction code is written to the address part 2b of the program counter. The page portion 2a of the program counter remains unchanged. Since the address data section 1b has 6 bits in this explanation, it is possible to branch in 64 ways, but even if the physical addresses are adjacent, there are cases where branching cannot be performed because the pages are different. FIG. 2 is a diagram explaining this.

Assuming page K of program memory 3, address 0. It is next to the current address (K-1)
Branching to page 63 address is not possible. In other words, even if the addresses are adjacent, if the pages are different, branching is not possible, which is a serious obstacle to programming.

As an instruction to compensate for the drawbacks of the intra-page branch, there is a relative branch instruction that specifies how many addresses away from the current address the branch should be made in the forward/backward direction. The relative branch instruction, which is generally called a relative branch instruction, has no page restrictions, but on the other hand, in order to perform the operation between the current address and the offset value in the arithmetic circuit, the data is transferred to the arithmetic unit and the arithmetic operation is performed. It also requires a process of writing the calculation result to the program counter, which has the drawback that the process takes a long time. Although the above-mentioned drawbacks can be overcome by adding a dedicated arithmetic circuit to the program counter in order to shorten the processing time, the program counter becomes complicated, which becomes a major obstacle to the integration of logic circuits.

SUMMARY OF THE INVENTION An object of the present invention is to provide a branch control method that takes advantage of the advantages of conventional intra-page branch instructions and relative branch instructions.

According to the present invention, a predetermined instruction word is retrieved using a program memory storing a collection of instruction words, which is a processing procedure, and a program counter that specifies an execution position in the program memory, and the above instruction word is decoded. , in a data processing device that performs processing corresponding to an instruction word, the program memory is divided into a plurality of small blocks, and the program memory is divided into a plurality of small blocks.
The counter is divided into a lower counter part corresponding to the address in the small block and an upper counter part corresponding to the number of the small block. A means for transferring data of a bit length corresponding to the bit length of the counter to a lower counter, and based on data in the instruction word that is different from the transfer data, the upper counter is moved to a relative position from the small block where the instruction word exists. A branch control scheme is obtained having means for modifying the corresponding values.

Next, the present invention will be explained.

In the following explanation, the branch instruction is a relative page branch instruction that can branch to each address between three pages before and after the current page.

FIG. 3 shows a branch instruction code and a program counter in the explanation of the present invention. 1a is a part that shows the relative page branch instruction code, 1b is an address part that shows the branch address in each page, and depending on the 2 bits of 1c, one of the three pages before and after including the current page is selected. This is the part that shows.
When the relative page branch instruction code part 1a is decoded, the address part 1b is written to the address part 2b of the program counter, and at the same time, the 2nd part of 1c is
When branching to the previous page depending on the bit, subtract 1 from the page part; when branching to the current page, add or subtract 0, or keep the previous value, and when branching to the next page, add 1 to the page part. do.

FIG. 4 is a conceptual diagram explaining this. As shown in the figure, branching is possible within three pages before and after the current page, increasing the degree of freedom of the program.

FIG. 5 is a block diagram of the program counter section explaining the relative page branch instruction of the present invention.

When the instruction code is decoded as a relative page branch instruction, the value of page section 10 of the program counter is subtracted by 1 for the previous page, or added or subtracted by 0 for the current page, or The previous value is held, and in the case of the next page, 1 is added. At the same time, the data in the address part of the instruction code passes through the transmission path 12 and is transferred to the address part 1 of the program counter.
1, and the data is written by the write signal.

FIGS. 6a, 6b, and 6c are diagrams showing the timing of processing operations for an intra-page branch instruction, a relative branch instruction, and a relative page branch instruction, respectively. An intrapage branch instruction decodes the instruction in the first cycle and writes address data to the address field of the program counter in the next cycle. In the relative branch instruction, the instruction is decoded in the first cycle, the value of the program counter is transmitted to the arithmetic unit in the next cycle, and the address data of the instruction code is operated on in the third cycle.
In the fourth cycle, the branch destination data is written to the program counter. A relative page branch instruction decodes the instruction in the first cycle and writes the address data of the instruction code to the address field of the program counter at the same time as +1, 0, -1 operations in the page field of the program counter in the second cycle. . In other words, the processing time is as short as the conventional intra-page branch instruction.

Page portion 10 of the program counter in FIG.
FIG. 7 is a block diagram showing the lowest part of the address section 11 and the highest part of the address section 11. When an instruction is not a branch instruction, the program counter increases in value by +1 each time the instruction is executed. A switching circuit 18 selects between the addition output signal of the addition circuit 15 and the data sent from the transmission line 21 according to a switching signal 26.
, data 21 from the transmission path at the time of this branch instruction
is selected, and in other cases, the addition output of the addition circuit 15 is selected. The signal selected by the switching circuit 18 is held until the latch circuit 17-1 is rewritten. The output of the latch circuit 17-1 is the adder circuit 1
5 and is added to the carry signal 20 at the previous stage. If there is a carry, it is transmitted to the OR gate 27. The control signal 25 ignores the carry signal from the address section 11 and controls addition and subtraction operations only in the page section 10. AND gate 16 ignores the output of OR gate 27 and prohibits addition/subtraction operation with control signal 2.
Controlled by 5. Addition/subtraction circuit 14 is latch circuit 1
Equivalent to the output of 7-2 and carry/down signal
Addition or subtraction is performed depending on the addition/subtraction control signal 23 using the output of the AND gate 16 as input. The results of addition and subtraction are input to the latch circuit 17-2, and the carry/carry down signal 22 is transmitted to the subsequent stage.

The operation of the relative page branch instruction of the present invention will be explained with reference to FIG.

When the instruction code is decoded and determined to be a relative page branch instruction, the address section 11 of the program counter outputs a switching signal 26, the output of the adder circuit 15 that had been selected up to that point is cut off, and the output from the transmission line 21 is cut off. The address part data of the received instruction code is selected by the selection circuit 18 and outputted to the latch circuit 17-1. A carry inhibit signal 25 is output to the page section 10 of the program counter, and a carry signal from the address section is inhibited by an OR gate 27. Furthermore, +1, 0, - of the page part of the instruction code
In the case of +1 operation, the control signal 24 is outputted by the part indicating 1 (1c in FIG. 3), and the AND gate 16 becomes "1". The addition/subtraction control signal 23 is also output at the same time, and the addition/subtraction circuit 14 outputs +1 only in the page section.
The determined value is output to the latch circuit 17-2. In the case of -1 operation of the page section, control signals 24 and 25
are the same, the addition/subtraction control signal 23 instructs subtraction, and the value subtracted by 1 only in the page portion by the addition/subtraction circuit 14 is output to the latch circuit 17-2. If the value of the page part does not change, the output of the AND gate 16 is controlled to "0" by the control signal 24, and the value of the page part does not change if addition and subtraction are performed. The relative page branching of the present invention can be performed by the above operations. The addition/subtraction circuit 14 in the page section of the present invention can be realized by simply adding a simple down-down circuit to the addition circuit built into the program counter.

Figure 8 shows the addition/subtraction circuit 14 and addition circuit 1 in Figure 7.
An embodiment of Embodiment 5 will be shown as a logic circuit, and parts common to the two circuits will be described using the same numbers.
AND gates 30 and 31 are “1” when the carry (or carry down) signal of the previous stage and the calculation input do not match.
The AND gate 30
and 31 are connected to the OR gate 32. The output of OR gate 32 therefore represents the result of addition and subtraction. The AND gate 33 is a signal for detecting carry, and the carry signal of the previous stage and the calculation input are connected.
AND gate 34 is a undercarriage detection circuit during subtraction;
AND gate 35 is a carry detection circuit during addition, and AND gates 34 and 35 are connected to OR gate 36, whose output outputs carry and carry down signals. By the way, the addition/subtraction circuit of the present invention does not require any special circuit; in other words, since the program counter has a built-in addition circuit, the addition/subtraction circuit can be constructed by simply adding a simple circuit to the program counter.

The relative page branch of the present invention is similar to that of conventional programs.
By adding a simple circuit to the counter, the degree of freedom in branching, which was a disadvantage of conventional intra-page branching, is increased, and the disadvantage of the long processing time of conventional relative branching is compensated for.This branching combines the advantages of each conventional branch. Processing is possible. Therefore, since the circuit configuration is extremely simple, it is extremely effective for integrating logic circuits, and in program development, it is easy to create programs because the degree of freedom of branch instructions, which are very frequently used, is increased. Therefore, the effectiveness of the present invention is extremely high.

Although the relative values of the page explained as an example of the present invention are set to +1, 0, and -1, it is also possible to modify them with a value of +2 or -2, and in that case, the relative value of the page is 2 from the lowest.
This can be achieved by inputting a carry or carry down signal to the th bit. Furthermore, although the program counter of this embodiment is a binary counter using an arithmetic circuit, in the case of a shift counter, relative modification of values can be achieved by controlling the shift direction.

That is, the type of counter does not matter as long as control is performed according to the counting operation of the program counter.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the instruction code and program address in the conventional example, FIG. 2 is a conceptual diagram explaining the conventional example, and FIG. 3 is an explanatory diagram of the instruction code and program address in the embodiment of the present invention. FIG. 4 is a conceptual diagram explaining an embodiment of the present invention, FIG. 5 is a block diagram of an embodiment of the present invention, and FIG. 7 is a detailed diagram of a part of an embodiment of the present invention, and FIG. 8 is a logic circuit diagram of an addition/subtraction circuit in the embodiment of the present invention.

Claims (1)

[Claims] 1. In a method of performing branch control using a program counter in which an upper counter section specifies a page and a lower counter section specifies an address within the page for a program memory divided into pages, the lower counter section is It has an adder circuit, a selection circuit that selects either the output data of the adder circuit or data input from the outside, and a first latch circuit that holds the selected data,
The upper counter section has an addition/subtraction circuit and a second latch circuit that holds the output of the addition/subtraction circuit,
A carry signal from the lower counter section is inputted to the addition/subtraction circuit of the upper counter section via a gate circuit, and when non-branching, the gate circuit is opened so that the carry signal can be applied to the upper counter section. The lower counter section and the upper counter section generate addresses that continuously increase by +1, and when branching, the gate circuit is closed and a signal designating the presence or absence of carry is given to the addition/subtraction circuit from the outside, and the addition and subtraction circuits are A branch control method characterized by instructing either subtraction and performing a branch operation beyond page boundaries.