JPS6316779B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention provides a data transfer speed that allows data writing between a CPU and multiple memories sharing the same data bus using a CPU-mediated method by adding a small amount of hardware (circuit). Concerning a data transfer method intended to increase speed.

In a general-purpose computer, after the power is turned on, the necessary interpreters and OS programs executed by the computer are stored in RAM (Random) as the main memory.
So-called IPL that is read by Access Memory)
(Initial Program Load) is required to be carried out efficiently.

Such IPL target programs include, for example, paper tape, magnetic tape, and ROM (Read Only
stored in a memory medium such as
There are programs that do not require a series of changes, such as FORTRAN and BASIC interpreter programs. Conventionally, in order to transfer a program from these media to the RAM, the CPU reads the data one byte at a time and stores it in the RAM, or the data is transferred using a DMA method.

FIG. 1 is an example of data transfer from ROM to RAM. In other words, the figure shows that when transferring a batch of data to RAM using the CPU-mediated method, each
An address data bus 1 and a data transfer bus 2 are provided so that RAM and ROM share the CPU.
By forming an address matching area where the RAMs match each other at addresses 1000H to 2FFF and by enabling the ROM and RAM alternately by the memory bank switching circuit 3, the CPU reads data from the ROM, switches banks, and stores the data in the RAM. Data is transferred by repeating these operations.

READ and WRITE in Figure 1 indicate that the CPU reads data from the ROM side (READ), and also that the CPU reads data from the ROM side.
Indicates that a command signal to write (WRITE) data to RAM is issued. However, such CPU-mediated data transfer involves alternating READ and WRITE operations, so the transfer speed is slow.

In order to improve this, the bank switching circuit is not used.
Data is transferred directly from ROM to RAM
This may be performed using a DMA (Direct Memory Access) method, but the DMA method requires complicated hardware. Furthermore, even if the ROM is provided in the I/O area for input/output control, it is inevitable that the hardware will become complicated, such as requiring a ROM access counter.

The object of the invention is to eliminate the above-mentioned disadvantages. To achieve the object, the present invention provides a main memory in which all or part of the ROM address matches a RAM address and the data bus also matches, in a computer that transfers data between a CPU and a memory via a data bus. Equipped with RAM,
A means for displaying a direct data transfer operation from ROM to RAM, a means for detecting an address matching area between ROM and RAM, and a command switching means for converting a read command from the CPU to ROM into a write command to RAM, As long as the output of the means for detecting address matching and the output of the display means are valid,
This makes it possible to write data to a RAM area with a matching address by issuing a read command from the CPU to the ROM.

Hereinafter, referring to the circuit shown in FIG. 2 which shows one embodiment of the present invention, a description will be given of the main constituent means for storing a ROM-stored program necessary for the arithmetic processing of the computer in the main memory RAM, for example, IPL. That is, as is clear from comparing Figure 2 with Figure 1, the ROM
With only a small addition of hardware, data transfer from the CPU to RAM requires fewer instructions from the CPU, and the transfer speed is more than double that of the conventional method. The ROM side data bus 2' of the bus 2 is disconnected.

In FIG. 2, the main memory RAM has a standard memory capacity of, for example, 64 kilobytes, and
8 corresponding to RAM address 1000H to 2FFFH
Kilobytes coexist with ROM. When performing an IPL operation within this coexisting address, the RAM
The READ and WRITE signals are fed through an AND-OR circuit shown at the bottom of the diagram. The input of the AND-OR circuit is based on the logic of the signal consisting of the READ signal of the CPU, the signal of the address detection circuit between ROM.RAM that detects the address matching area, and the ON signal of the F/F circuit. and
READ/WRITE in RAM is made to match or swap.

The flip-flop F/F is set to Q=1 during IPL operation, and set to Q=0 at other times. ROM and
The RAM address detection circuit determines the address from the operation code _A12 to _A15 of the example 1000 to 2FFF, and outputs 1 to the output side C in the address matching area, and C=0 for other addresses.
Consists of NOR and EXOR circuits.

In the data transfer means of the present invention, first, Q= of F/F
1 and read and write input to RAM.
Replace the WRITE signal and enable the ROM, then transfer addresses 1000 to 2FFF to the CPU.
Make it READ. Since this address is in the matching area, C=1 is output, and in the AND-OR circuit, the B side is valid, that is, the RAM is written (WRITE) regardless of the CPU read (READ).
Perform the action. At this time, the accessed address data is output from the ROM to the bus 2 and also supplied to the RAM. That is, data is transferred from ROM to RAM. In the conventional CPU-mediated method, ROM
A two-step operation is required, in which data is read from the RAM and then written to the RAM.
Since data is transferred to RAM only by operation, the data transfer speed is approximately double the speed.

By giving the output (or Q output) of the F/F as an ENABLE signal to the ROM.
The ROM is valid only during IPL operation, and when other than IPL operation, the F/F is cleared and the ROM becomes invalid.The same is true even if the ROM is separated in the memory space.
There is no influence at all.

In the explanation of the above embodiment, READ and WRITE
The logic circuit is shown separately from the and.
Although an OR circuit is shown, this circuit may be modified in various ways. Some models have only one READ and WRITE signal, but in this case, READ is high.
If it is at the L level, if it is forcibly lowered to the L level, the same inter-memory data transfer as described above will be executed.

As described above, according to the data transfer method of the present invention, the transfer speed can be nearly doubled with a simple hardware (circuit) configuration.
The effect is great if used in operations such as IPL.

[Brief explanation of the drawing]

FIG. 1 shows an example of a conventional data transfer circuit, and FIG. 2 shows a data transfer circuit diagram according to an embodiment of the present invention.

Claims (1)

[Claims] 1. In a computer that transfers data between the CPU and memory via a data bus, main memory whose ROM addresses, in whole or in part, match RAM addresses and whose data bus also matches.
A means for displaying a data transfer operation directly from the ROM to the RAM, a means for detecting an address matching area between the ROM and the RAM, and an output of the means for detecting the address matching area and the display means are both effective. In some cases, a takeover command from the CPU to ROM is used as a write command to RAM, and in other cases, a command switching means is provided to output read or write commands from the CPU as they are to RAM. A data transfer method characterized by making it possible to write data to a RAM area with a matching address using a read command.