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JPS6317564B2 - - Google Patents
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JPS6317564B2 - - Google Patents

Info

Publication number
JPS6317564B2
JPS6317564B2 JP24920684A JP24920684A JPS6317564B2 JP S6317564 B2 JPS6317564 B2 JP S6317564B2 JP 24920684 A JP24920684 A JP 24920684A JP 24920684 A JP24920684 A JP 24920684A JP S6317564 B2 JPS6317564 B2 JP S6317564B2
Authority
JP
Japan
Prior art keywords
hole
mark
marks
inner layer
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP24920684A
Other languages
Japanese (ja)
Other versions
JPS61125715A (en
Inventor
Shinji Okamoto
Toshinori Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP24920684A priority Critical patent/JPS61125715A/en
Publication of JPS61125715A publication Critical patent/JPS61125715A/en
Publication of JPS6317564B2 publication Critical patent/JPS6317564B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4638Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/0061Tools for holding the circuit boards during processing; handling transport of printed circuit boards

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Machine Tool Sensing Apparatuses (AREA)
  • Drilling And Boring (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】 〔技術分野〕 この発明は、多層印刷配線板の内層回路上に形
成されている孔穿設位置を示す孔マークの位置検
出法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for detecting the position of a hole mark that is formed on an inner layer circuit of a multilayer printed wiring board and indicates a hole drilling position.

〔背景技術〕[Background technology]

電子機器等に用いられる多層印刷配線板は、一
般に次のようにして製造されている。まず、内層
プリプレグの両面もしくは片面に金属箔を貼り着
け、これに内層回路を形成して内層回路板を作
る。上記内層回路板1枚またはそれを複数枚平面
的に並べたものに対して、上下に外層用のプリプ
レグを重ね合わせるとともに、さらにそれらの外
側に金属箔を重ね合わせ、加熱加圧成形を行う。
その後、内層回路板複数枚を並べたものに対して
は、内層回路ごとに荒切りをする。前記成形後に
出来た多層印刷配線板の中間品に対して、その内
層回路板表面に表示されている、基準孔穿設位置
を示す孔マークを最外層の金属箔側から探り出
す。孔マークのある個所を上側から座ぐりして前
記孔マークを露出させる。この孔マークの中心に
基準孔を明ける。そして、この基準孔を基準にし
て最外層の金属箔に外層回路を形成することによ
り、多層印刷配線板が出来上がるのである。
Multilayer printed wiring boards used in electronic devices and the like are generally manufactured as follows. First, metal foil is attached to both or one side of the inner layer prepreg, and an inner layer circuit is formed on this to create an inner layer circuit board. With respect to one inner layer circuit board or a plurality of inner layer circuit boards arranged in a plane, outer layer prepregs are stacked on top and bottom, metal foil is further stacked on the outside of these, and heat and pressure molding is performed.
After that, if a plurality of inner layer circuit boards are arranged side by side, rough cutting is performed for each inner layer circuit. For the intermediate product of the multilayer printed wiring board produced after the molding, the hole mark indicating the position of the reference hole, which is displayed on the surface of the inner layer circuit board, is detected from the outermost layer metal foil side. A spot with a hole mark is counterbored from above to expose the hole mark. Drill a reference hole in the center of this hole mark. Then, by forming an outer layer circuit on the outermost layer of metal foil using this reference hole as a reference, a multilayer printed wiring board is completed.

しかしながら、上記の製造方法には以下のよう
な問題点があつた。それは、内層回路板複数枚
が並べられてなる多層印刷配線板の中間品におい
ては、内層回路板が最外層の金属箔のために見え
なくなつているため、荒切り位置を判別しにくい
と言う点、孔マークを探り出すに当たり、孔マ
ークが最外層の金属箔に遮ぎられて見えないた
め、正確な位置がわからないという点、および
加熱加圧成形時に外層と内層回路板との間に位置
ずれが生じやすいため、孔マークの正確な位置が
ますますわかりにくくなつているという点であ
る。
However, the above manufacturing method has the following problems. This is because in intermediate products of multilayer printed wiring boards, which consist of multiple inner layer circuit boards arranged side by side, the inner layer circuit boards are hidden from view due to the outermost layer of metal foil, making it difficult to determine the rough cutting position. When searching for dots and hole marks, the hole marks are blocked by the outermost layer of metal foil and cannot be seen, so the exact position cannot be determined.Also, there is a problem of misalignment between the outer layer and the inner layer circuit board during hot press molding. The problem is that the exact position of the hole mark is becoming increasingly difficult to determine.

そこで、上記のような問題を解消するため、次
のような孔マークの検出方法が開発された。ひと
つは、第1図にみるように、内層プリプレグ2上
に内層回路1aおよび孔マーク1bを形成した
後、予め孔マーク1bの上にパツチ(ガイドマー
ク)3を貼つておいた状態で外層プリプレグ4,
4および金属箔5,5を重ね加熱加圧成形を行う
ようにする。出来上りの多層印刷配線板中間品6
が、パツチ3の厚み分だけ盛り上がり、その金属
箔5上の部分5aがわずかに光るのを目視で判別
する方法である。図中、1は内層回路板である。
もうひとつの方法は、多層印刷配線板にX線を照
射して内層回路を透視することにより孔マークの
位置を検出する方法である。ところが、上記2つ
の方法のうち、前者は、パツチを貼る工程が増え
る、孔マークの位置を目視で探り出すため、非常
に目が疲れる、金属箔の盛り上がり部分が光るの
を判別するのは機械では難しいため、自動化に適
さず、また、自動化にかかる費用が高すぎる等の
問題があつた。また、後者は、X線に対する安全
対策が必要となる、X線設備への投資額が高価で
あるため自動化しても採算が合わない等の問題が
あつた。
Therefore, in order to solve the above problems, the following hole mark detection method was developed. As shown in FIG. 1, after forming the inner layer circuit 1a and the hole mark 1b on the inner layer prepreg 2, the outer layer prepreg is attached with a patch (guide mark) 3 pasted on the hole mark 1b in advance. 4,
4 and metal foils 5, 5 are stacked and heated and press-molded. Finished multilayer printed wiring board intermediate product 6
However, this is a method of visually determining that the patch 3 is raised by the thickness of the patch 3 and that the portion 5a on the metal foil 5 shines slightly. In the figure, 1 is an inner layer circuit board.
Another method is to detect the position of the hole mark by irradiating the multilayer printed wiring board with X-rays and seeing through the inner layer circuits. However, of the above two methods, the former requires more steps to attach the patch, the position of the hole mark is detected visually, which is very tiring on the eyes, and it is not possible for a machine to distinguish when the raised part of the metal foil shines. Because it is difficult, it is not suitable for automation, and there are problems such as the cost of automation being too high. In addition, the latter method requires safety measures against X-rays, and the investment in X-ray equipment is expensive, making it unprofitable even when automated.

〔発明の目的〕[Purpose of the invention]

この発明は、上記のような問題を解消し、安価
に自動化し得る多層印刷配線板の孔マーク位置検
出法を提供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for detecting hole mark positions on a multilayer printed wiring board that solves the above-mentioned problems and can be automated at low cost.

〔発明の開示〕[Disclosure of the invention]

発明者らは、上記の目的を達成するために鋭意
検討を重ね、この発明を完成した。
In order to achieve the above object, the inventors conducted extensive studies and completed this invention.

この発明は、内層回路板上の適数個所に孔穿設
位置を示す孔マークが形成されている多層印刷配
線板の、前記孔マークの位置を検出する孔マーク
位置検出法であつて、予め内層回路板の回路パタ
ーンの周縁部複数個所に前記孔マークの座標を決
める基準となる金属製マークを回路パターンと同
時に形成しておき、外層金属箔表面の縁部からう
ず電流式センサを走査させるようにしてこのセン
サの出力変化に基づき前記複数の金属製マークの
位置を測定し、この測定結果に基づいて前記孔マ
ークの位置を検出することを特徴とする多層印刷
配線板の孔マーク位置検出法をその要旨とする。
以下、これを、その実施例をあらわす図面に基づ
いて詳しく説明する。
The present invention is a hole mark position detection method for detecting the position of hole marks in a multilayer printed wiring board in which hole marks indicating hole drilling positions are formed at a suitable number of locations on an inner layer circuit board. Metal marks that serve as a reference for determining the coordinates of the hole marks are formed at multiple locations on the periphery of the circuit pattern on the inner layer circuit board at the same time as the circuit pattern, and an eddy current sensor is scanned from the edge of the outer layer metal foil surface. A hole mark position detection method for a multilayer printed wiring board, characterized in that the positions of the plurality of metal marks are measured based on changes in the output of the sensor, and the positions of the hole marks are detected based on the measurement results. The law shall be its gist.
Hereinafter, this will be explained in detail based on drawings showing examples thereof.

この発明にかかる多層印刷配線板の孔マーク位
置検出法は、第2図および第3図にみるように、
従来と同様、内層回路板1上の3個所に、孔穿設
位置を示す孔マーク1bが形成されている多層印
刷配線板7において、前記孔マーク1bの位置を
検出する方法である。孔マーク1bは、外層金属
箔5に、内層回路と対応するよう回路を形成する
際の基準となる基準孔の穿設位置を示すものであ
る。なお、第3図では、孔マークは見えていな
い。予め内層回路板1の孔マーク1bを有する方
の回路パターン1aの周縁部3個所に、孔マーク
1b,1b,1bの座標を決める基準となる金属
製マーク8a,8b,8cを回路パターン1aと
同時にそれぞれ形成しておく。これら金属製マー
ク8a,8b,8cは、第4図にみるように、内
層回路板のxy座標軸を決めるためのものであり、
マーク8aとマーク8bの両中心点を通る直線を
y軸、y軸と直交し、マーク8cの中心点を通る
直線をx軸としている。これらxy座標軸に従つ
て各孔マーク1bの座標位置を確定しておく。前
記金属製マーク8a,8b,8cに対しては、第
3図にみるように、外層金属箔5表面の縁部から
金属箔5表面とは一定の距離を置きつつ内側方向
(矢印方向、第2図にも図示)にうず電流式セン
サ9を走査させるようにして、位置の測定がなさ
れる。うず電流式センサとは、高周波磁界を発生
し、その磁界により導電体に生じるうず電流損の
ためにセンサコイルのインピーダンスが変化する
ことを利用して、導電体を検知するものである。
この実施例では、外層金属箔によるうず電流損は
一定であるため、外層金属箔と金属製マークが重
なつた場合のうず電流損の変化分を検出するので
ある。第3図のグラフにみるように、外層金属箔
5表面を走査するうず電流式センサ9は、最初の
磁場変化がある金属製マーク8a,8b,8c上
に来た時に、そのセンサ出力が最初の波形ピーク
点Aを形成するようになつている。そこで、うず
電流式センサ9の、最初の波形ピーク点Aを形成
するという出力変化に基づき、前記複数の各金属
製マーク8a,8b,8cの位置を測定する。そ
して、この測定結果に基づき、前記内層回路板1
上に定められていたxy座標軸が、外層金属箔5
表面上に浮かび上がつてくる。したがつて、前記
xy座標軸に従つて予め座標確定されていた各孔
マーク1bの位置も外層金属箔5表面上において
知ることができるのである。
As shown in FIGS. 2 and 3, the method for detecting the position of hole marks on a multilayer printed wiring board according to the present invention is as follows.
Similar to the conventional method, this method detects the positions of hole marks 1b in a multilayer printed wiring board 7 in which hole marks 1b indicating hole drilling positions are formed at three locations on an inner layer circuit board 1. The hole mark 1b indicates the position of a reference hole that will be a reference when forming a circuit in the outer layer metal foil 5 to correspond to the inner layer circuit. Note that in FIG. 3, the hole mark is not visible. In advance, metal marks 8a, 8b, 8c, which serve as a reference for determining the coordinates of the hole marks 1b, 1b, 1b, are placed on three peripheral parts of the circuit pattern 1a of the inner layer circuit board 1, which has the hole marks 1b, on the circuit pattern 1a. Form each at the same time. These metal marks 8a, 8b, 8c are for determining the xy coordinate axes of the inner layer circuit board, as shown in FIG.
A straight line passing through the center point of mark 8a and mark 8b is defined as the y-axis, and is perpendicular to the y-axis, and a straight line passing through the center point of mark 8c is defined as the x-axis. The coordinate position of each hole mark 1b is determined in accordance with these xy coordinate axes. As shown in FIG. 3, the metal marks 8a, 8b, and 8c are placed in the inner direction (arrow direction, The position is measured by scanning the eddy current sensor 9 (also shown in FIG. 2). An eddy current sensor generates a high-frequency magnetic field and detects a conductor by utilizing the fact that the impedance of the sensor coil changes due to eddy current loss generated in the conductor due to the magnetic field.
In this embodiment, since the eddy current loss due to the outer layer metal foil is constant, the change in eddy current loss when the outer layer metal foil and the metal mark overlap is detected. As shown in the graph of FIG. 3, when the eddy current sensor 9 that scans the surface of the outer metal foil 5 comes over the metal marks 8a, 8b, and 8c where the first magnetic field change occurs, the sensor output first changes. A waveform peak point A is formed. Therefore, the positions of the plurality of metal marks 8a, 8b, and 8c are measured based on the output change of the eddy current sensor 9 that forms the first waveform peak point A. Based on this measurement result, the inner layer circuit board 1
The xy coordinate axes defined above are the outer layer metal foil 5.
It rises to the surface. Therefore, the above
The position of each hole mark 1b whose coordinates have been determined in advance according to the xy coordinate axes can also be known on the surface of the outer metal foil 5.

以上のように、この実施例にかかる多層印刷配
線板の孔マーク位置検出法は、内層回路板の回路
パターン形成と同時に孔マークの座標の基準とな
る金属製マークを形成しておき、安価なうず電流
式センサを用いて前記金属製マークの位置を測定
し、この測定結果に基づいて孔マークの位置を検
出するようになつており、うず電流式センサとい
うコストのかからない装置を用いて検出を行うの
で、安価に自動化が実現され得るのである。
As described above, the method for detecting the position of hole marks on a multilayer printed wiring board according to this embodiment involves forming a metal mark that serves as a reference for the coordinates of the hole marks at the same time as forming the circuit pattern on the inner layer circuit board. The position of the metal mark is measured using an eddy current sensor, and the position of the hole mark is detected based on the measurement result, and the detection is performed using an inexpensive device called an eddy current sensor. Because this process is performed automatically, automation can be achieved at low cost.

孔マークの位置が検出されると、つぎに、その
位置に外層回路形成時の基準となる基準孔を穿設
する。その穿設に当たり、孔マークの内層回路板
上におけるxy座標を外層金属箔上の対応位置に
演算処理等により自動的に置き換えるようにすれ
ば、基準孔の穿設作業についても自動化が実現さ
れ得る。
Once the position of the hole mark is detected, a reference hole is then drilled at that position to serve as a reference when forming the outer layer circuit. When drilling the reference hole, if the x and y coordinates of the hole mark on the inner layer circuit board are automatically replaced with the corresponding position on the outer layer metal foil through arithmetic processing, etc., the work of drilling the reference hole can also be automated. .

例えば、第4図にみるように、最外層を外層回
路形成用の金属箔とする荒切り後の多層印刷配線
板7の外形をあらわす外郭線上にXY座標軸を置
く。外形の一辺にX軸を取り、前記一辺と直交す
る片にY軸を取る。今、金属製マーク8a,8
b,8cのXY座標系上の各座標を、(Xa,Ya)、
(Xb,Yb)、(Xc,Yc)とすると、内層回路板1
のxy座標軸と多層印刷配線板7の外形との傾き
θは、下記の式で求められる。
For example, as shown in FIG. 4, the XY coordinate axes are placed on the outline representing the outer shape of the rough-cut multilayer printed wiring board 7 whose outermost layer is a metal foil for forming an outer layer circuit. The X-axis is taken on one side of the outer shape, and the Y-axis is taken on the side perpendicular to the side. Now, metal marks 8a, 8
Each coordinate on the XY coordinate system of b, 8c is (Xa, Ya),
(Xb, Yb), (Xc, Yc), inner layer circuit board 1
The inclination θ between the xy coordinate axes and the outer shape of the multilayer printed wiring board 7 is determined by the following formula.

θ=tan-1(Xb−Xa/Yb−Ya) …… また、内層回路板のxy座標の原点のXY座標系
上の座標(Xo,Yo)は、下記の式および式
で求められる。
θ=tan -1 (Xb-Xa/Yb-Ya) ... Also, the coordinates (Xo, Yo) on the XY coordinate system of the origin of the xy coordinates of the inner layer circuit board are determined by the following equations and formulas.

Xo=Xbcos2θ−Ybsinθcosθ +Xcsin2θ+Ycsinθcosθ …… Yo=−Xbsinθcosθ+Ybsin2θ +Xcsinθcosθ+Yccos2θ …… そこで、予め確定済みの孔マーク1bのxy座
標を(xi,yi)とすると、求めるべき孔マーク1
bのXY座標(Xi,Yi)は下記の式および式
で求められるのである。
Xo _ _
The XY coordinates (Xi, Yi) of b can be found using the following equations and expressions.

Xi=Xo+xicosθ+yisinθ …… Yi=Yo−xisinθ+yicosθ …… 以上のようにして求められた孔マークのXY座
標(Xi,Yi)をコンピユータに入力する。その
情報に基づき、XY座標に従つて移動するよう設
けられた孔穿設手段を制御することにより、基準
孔が外層金属箔上の正確な位置に自動的に形成さ
れるのである。
Xi=Xo+xisinθ+yisinθ...Yi=Yo−xisinθ+yicosθ...The XY coordinates (Xi, Yi) of the hole mark obtained in the above manner are input into the computer. Based on this information, a reference hole is automatically formed at a precise position on the outer layer metal foil by controlling a hole punching means provided to move according to the XY coordinates.

なお、第5図にみるように、複数の内層回路板
1,1,1が平面的に並べられた状態で同時に同
じ外層材(プリプレグおよび金属箔)10と一体
成形されて多層印刷配線板の中間品を形成してお
り、この中間品を内層回路板毎に荒切りする場合
にも上記〜式を適用することができる。すな
わち、荒切り時に切断線上の点となる複数個所の
xy座標を予め確定しておけば、金属製マーク8
a,8b,8cおよび内層回路1aを避けるよう
にして、鎖線で示すように、荒切りを行うことが
できるのである。外層材の外縁部は、成形の際に
変形する。そのため、荒切りによつて切り落され
るのである。
As shown in FIG. 5, a plurality of inner layer circuit boards 1, 1, 1 are arranged in a plane and are simultaneously molded integrally with the same outer layer material (prepreg and metal foil) 10 to form a multilayer printed wiring board. The above equations can also be applied when an intermediate product is formed and this intermediate product is roughly cut into each inner layer circuit board. In other words, multiple points on the cutting line during rough cutting
If the xy coordinates are determined in advance, the metal mark 8
As shown by the chain line, rough cutting can be performed while avoiding the parts a, 8b, 8c and the inner layer circuit 1a. The outer edge of the outer layer material is deformed during molding. Therefore, it is cut off by rough cutting.

この発明にかかる多層印刷配線板の孔マーク位
置検出法においては、うず電流式センサで孔マー
クを直接検出するのではなく、孔マークの座標を
決める基準となる別の金属製マークの位置を測定
するようにしている。これは、孔マークが内層回
路パターン内に設けられている場合があり、その
場合には内層回路パターンとの区別がつかないか
らである。しかも、実施例では、金属製マークを
用いて孔マークの座標の基準となるx軸とy軸を
定めているので、孔マークの座標が正確にわかる
ようになつている。
In the method for detecting the position of a hole mark on a multilayer printed wiring board according to the present invention, the eddy current sensor does not directly detect the hole mark, but instead measures the position of another metal mark that serves as a reference for determining the coordinates of the hole mark. I try to do that. This is because the hole mark may be provided within the inner layer circuit pattern, in which case it is difficult to distinguish it from the inner layer circuit pattern. Furthermore, in the embodiment, the x-axis and y-axis, which serve as the reference for the coordinates of the hole mark, are determined using metal marks, so that the coordinates of the hole mark can be determined accurately.

実施例では、うず電流式センサの出力の波形ピ
ーク点に基づいて金属製マークの位置を測定して
いた。これは、波形ピーク点に基づけば、プリプ
レグの厚み、金属箔の厚み、材質等の違いによる
検出感度の変化に関係なく、測定が可能であるか
らである。
In the embodiment, the position of the metal mark was measured based on the waveform peak point of the output of the eddy current sensor. This is because, based on the waveform peak point, measurement is possible regardless of changes in detection sensitivity due to differences in prepreg thickness, metal foil thickness, material, etc.

この発明にかかる多層印刷配線板の孔マーク位
置検出法により検出する孔マークは、実施例で
は、外層回路を形成するための基準孔の位置を示
すものであつた。しかし、これに限られるもので
はなく、例えば、スルーホールめつきをするため
の孔を示すものであつても良い。また、孔マーク
が形成される位置や数に特別の制限はない。金属
製マークについても同様である。したがつて、金
属製マークが必ずしもxy座標軸上に位置してい
なくとも良い。xy座標軸の決め方は自由である。
In the embodiment, the hole marks detected by the hole mark position detection method for a multilayer printed wiring board according to the present invention indicate the positions of reference holes for forming the outer layer circuit. However, the present invention is not limited to this, and for example, it may indicate a hole for through-hole plating. Further, there is no particular restriction on the position or number of hole marks formed. The same applies to metal marks. Therefore, the metal mark does not necessarily have to be located on the xy coordinate axes. The xy coordinate axes can be determined freely.

〔発明の効果〕〔Effect of the invention〕

この発明にかかる多層印刷配線板の孔マーク位
置検出法は、予め内層回路板の回路パターンの周
縁部複数個所に孔マークの座標を決める基準とな
る金属製マークを回路パターンと同時に形成して
おき、外層金属箔表面の縁部からうず電流式セン
サを走査させるようにしてこのセンサの出力変化
に基づき複数の金属製マークの位置を測定し、こ
の測定結果に基づいて前記孔マークの位置を検出
するようにしており、うず電流式センサというコ
ストのかからない装置を用いて検出を行うので、
安価に自動化が実現されることができるという効
果がもたらされるのである。
In the hole mark position detection method for a multilayer printed wiring board according to the present invention, metal marks are formed in advance at multiple locations on the periphery of the circuit pattern of the inner layer circuit board at the same time as the circuit pattern to serve as a reference for determining the coordinates of the hole marks. , an eddy current sensor is scanned from the edge of the surface of the outer metal foil to measure the positions of a plurality of metal marks based on changes in the output of this sensor, and the position of the hole mark is detected based on the measurement results. Since the detection is performed using an inexpensive device called an eddy current sensor,
The effect is that automation can be realized at low cost.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は多層印刷配線板の孔マーク位置検出法
の従来例を説明する断面図、第2図はこの発明に
かかる多層印刷配線板の孔マーク位置検出法に用
いられる内層回路板の一態様をモデル的にあらわ
す平面図、第3図はこの発明にかかる多層印刷配
線板の孔マーク位置検出法の一実施例を説明する
図面、第4図は第3図に示した多層印刷配線板の
孔マーク位置検出法によつて検出された孔マーク
位置を、外層金属箔上の位置に自動的に置き換え
る方法を説明する図面、第5図は多層印刷配線板
の中間品を第3図の孔マーク位置検出法の応用に
より荒切りを行う方法を説明する図面である。 1…内層回路板、1a…内層回路、1b…孔マ
ーク、5…外層金属箔、7…多層印刷配線板、8
a,8b,8c…金属製マーク、9…うず電流式
センサ。
FIG. 1 is a sectional view illustrating a conventional method for detecting hole mark positions on a multilayer printed wiring board, and FIG. 2 is an embodiment of an inner layer circuit board used in the method for detecting hole mark positions on a multilayer printed wiring board according to the present invention. FIG. 3 is a diagram illustrating an embodiment of the hole mark position detection method for a multilayer printed wiring board according to the present invention, and FIG. 4 is a plan view of the multilayer printed wiring board shown in FIG. A drawing explaining a method for automatically replacing the hole mark position detected by the hole mark position detection method with the position on the outer layer metal foil. 2 is a diagram illustrating a method for performing rough cutting by applying a mark position detection method. DESCRIPTION OF SYMBOLS 1... Inner layer circuit board, 1a... Inner layer circuit, 1b... Hole mark, 5... Outer layer metal foil, 7... Multilayer printed wiring board, 8
a, 8b, 8c...metal mark, 9...eddy current sensor.

Claims (1)

【特許請求の範囲】 1 内層回路板上の適数個所に孔穿設位置を示す
孔マークが形成されている多層印刷配線板の、前
記孔マークの位置を検出する孔マーク位置検出法
であつて、予め内層回路板の回路パターンの周縁
部複数個所に前記孔マークの座標を決める基準と
なる金属製マークを回路パターンと同時に形成し
ておき、外層金属箔表面の縁部からうず電流式セ
ンサを走査させるようにしてこのセンサの出力変
化に基づき前記複数の金属製マークの位置を測定
し、この測定結果に基づいて前記孔マークの位置
を検出することを特徴とする多層印刷配線板の孔
マーク位置検出法。 2 金属製マークが孔マークの座標の基準となる
xy座標軸を決めるためのものである特許請求の
範囲第1項記載の多層印刷配線板の孔マーク位置
検出法。
[Scope of Claims] 1. A hole mark position detection method for detecting the position of hole marks in a multilayer printed wiring board in which hole marks indicating hole drilling positions are formed at appropriate number of locations on an inner layer circuit board, At the same time as the circuit pattern, metal marks are formed in advance at multiple locations on the periphery of the circuit pattern on the inner layer circuit board to serve as a reference for determining the coordinates of the hole marks, and the eddy current sensor is inserted from the edge of the outer layer metal foil surface. A hole in a multilayer printed wiring board, characterized in that the positions of the plurality of metal marks are measured based on changes in the output of the sensor in a scanning manner, and the position of the hole mark is detected based on the measurement results. Mark position detection method. 2 The metal mark serves as the reference for the coordinates of the hole mark.
A method for detecting the position of a hole mark in a multilayer printed wiring board according to claim 1, which is for determining an xy coordinate axis.
JP24920684A 1984-11-26 1984-11-26 Method for detecting hole mark position on multi-layer printing wiring board Granted JPS61125715A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24920684A JPS61125715A (en) 1984-11-26 1984-11-26 Method for detecting hole mark position on multi-layer printing wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24920684A JPS61125715A (en) 1984-11-26 1984-11-26 Method for detecting hole mark position on multi-layer printing wiring board

Publications (2)

Publication Number Publication Date
JPS61125715A JPS61125715A (en) 1986-06-13
JPS6317564B2 true JPS6317564B2 (en) 1988-04-14

Family

ID=17189490

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24920684A Granted JPS61125715A (en) 1984-11-26 1984-11-26 Method for detecting hole mark position on multi-layer printing wiring board

Country Status (1)

Country Link
JP (1) JPS61125715A (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61274806A (en) * 1985-05-31 1986-12-05 Japan Steel Works Ltd:The Drilling machine for reference hole in printed substrate
US4899440A (en) * 1986-12-31 1990-02-13 Systems Analysis And Integration Method and apparatus for locating targets on a panel and performing work operations thereon
JP2777425B2 (en) * 1989-10-12 1998-07-16 日本ミクロン株式会社 Method of manufacturing pin grid array having multi-stage bonding terminal structure, apparatus for cutting out inner layer terminal thereof, and multilayer substrate for pin grid array
US7732732B2 (en) 1996-11-20 2010-06-08 Ibiden Co., Ltd. Laser machining apparatus, and apparatus and method for manufacturing a multilayered printed wiring board
DE69737991T2 (en) * 1996-11-20 2008-04-30 Ibiden Co., Ltd., Ogaki LASER PROCESSING DEVICE, METHOD AND DEVICE FOR PRODUCING A MULTILAYER PRINTED PCB
US6056008A (en) * 1997-09-22 2000-05-02 Fisher Controls International, Inc. Intelligent pressure regulator
US6367678B1 (en) * 2000-04-18 2002-04-09 Ballado Investments Inc. Process for stacking layers that form a multilayer printed circuit

Also Published As

Publication number Publication date
JPS61125715A (en) 1986-06-13

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