JPS6318779B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a multi-system comprising two computer systems each having a service processor, in which two service processors issue service requests to the same channel control device, and This invention relates to a conflict control method when conflicting requests occur.

Figure 1 shows an example of a multi-system, where MACA and MACB are main memory access control units, CPUA and CPUB are central processing units, and CHCA and CPUB are central processing units.
CHCB represents a channel controller, and SVPA and SVPB represent a service processor. Main memory access control device MACA, central processing unit
The CPUA, channel control device CHCA, and service processor SVPA constitute an A-system computer system, and the main memory access control device
MACB, central processing unit CPUB, channel control unit CHCB, and service processor SVPB are B
It constitutes the grid computer system. The central processing unit CPUA is the main memory access control unit MACB
The main storage device of the B system can be used via the channel control device CHCB, and the input/output device of the B system can be used via the channel control device CHCB. The central processing unit CPUB can also use the resources of the A system.

The service processor SVPA can not only service the channel control device CHCA of its own system, but also the channel control device CHCB of the B system. service·
The same applies to processor SVPB. In this case, the service refers to, for example, writing data to an arbitrary data register of a channel control device or reading the contents of an arbitrary data register of a channel control device for maintenance or failure recovery.

Service processors SVPA and SVPB may issue service requests to the same channel controller, for example CHCB. In such cases, racing of service requests occurs. In the prior art, channel control device
A priority selection mechanism was provided for each of CHCA and CHCB, and when a conflict of service requests occurred, one of the service requests was selected. Since the above priority selection mechanism is composed of hardware,
The drawback is that the channel control devices CHCA and CHCB are expensive.

The present invention is based on the above considerations, and includes:
The purpose of the present invention is to provide a contention control method in which a program is responsible for part of the control when service requests from a service processor conflict with a channel control device, thereby simplifying the hardware for contention control. It is said that Therefore, the competitive control method of the present invention includes two computer systems each having a service processor, and each of the service processors controls not only its own channel control device but also the other system's channel control device. In a multi-system, where one service processor (SVPA) is accessing, the access bit (ACBA) is set on when one service processor (SVPA) is accessing, and the status register (STRA) is set to state information. The access failure indicator bit (ACFA) is set to indicate that the other service processor (SVPB) is being accessed, and is set to on when the other service processor (SVPB) is being accessed.・Status register (STRB) in which bits (ACBB) and status information are set
It has an access failure indication bit (ACFB) installed inside the system to indicate that one service processor (SVPA) is currently accessing, and the contents of the access bit (ACBA) of one system are used for accessing the other system. A signal line is provided to transfer the contents of the access failure indication bit (ACFB) of the other system to the access failure indication bit (ACFA) of one system. and when each of the service processor (SVPA) and service processor (SVPB) accesses the channel control device, (a) blankly reads the register of the channel control device and uses the status information as the status of its own system. - Store in the register, (b) check the status register of the own system to see if the above empty read has failed, and (c) check if the status information in the status register of the own system does not indicate failure. (d) After turning on the access bit of the own system, the access failure indication bit of the other system is set to on. (e) As a result of the check in (d) above, if the access failure indication bit does not indicate failure, execute the access; (f) As a result of the check in (d) above, the access failure indication If the bit indicates a failure, turn off the access bit, if the number of failures exceeds a predetermined value, terminate abnormally, and if the number of failures is less than a predetermined value, set a waiting time. , after the end of the waiting time, repeats the process of turning on the access bit of the own system in (c) above. Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 2 is a diagram showing the configuration of hardware used in the present invention, and FIG. 3 is a flowchart explaining the processing of the present invention.

In Figure 2, DTR _{0 to o} are multiple data points.
Register, BUS is bus, ANDA and ANDB are
AND circuit, STRA and STRB are status registers, ADRA and ADRB are address registers,
SDBA and SDBB are address registers respectively.
own system/other system designation bits provided in ADRA and ADRB; ACFA and ACFB are access failure display bits provided in status registers STRA and STRB, respectively, to display the access status of the other system;
ACBA and ACBB are address registers respectively.
The access bits provided in ADRA and ADRB are shown respectively. service processor
The address register ADRA of SVPA specifies the desired register etc. to be accessed, and the own system/other system specification bit SDBA determines whether registers etc. of the own system or other system should be accessed. It is to be specified. service·
Data to be sent is set in data register DTRA of processor SVPA. service·
Processor SVPA status register STRA
In addition to the access failure display bit ACFA, various status information indicating events associated with the operation of the service processor SVPA is stored. Service processor SVPB address register
ADRB, own system/other system specification bit SDBB, data register DTRB, and status register
STRB has the same functions as those on the service processor SVPA side.

Figure 2B shows the relationship between status register STRA and address register ADRB, and the relationship between status register STRB and address register
It shows the relationship between ADRA. Access bit ACBB of address register ADRB and access failure bit of status register STRA
It is connected to ACFA by a signal line, and the access bit
When ACBB is set to "1", the access failure bit ACFA is also set to "1". status register
The access failure bit ACFB in STRB is
Connected to access bit ACBA of register ADRA.

FIG. 3 is a flowchart showing the operation of the present invention. Service processor SVPA and service processor
Since the operation of processor SVPB is the same, service processor SVPA will be described. Service processor SVPA is channel controller CHCA
Or perform the following operations when providing services to CHCB.

Empty read any data register DTR _o of the desired channel control device and write the data register
Sets the status information in DTR _o and stores it in status register STRA.

Check whether the status indicator bits including the access failure indicator bit ACFA in the status register STRA are on. If any of the status display bits in the status register STRA are on because the service processor SVPB is already performing service, etc.
The result is Yes, resulting in an abnormal termination. Further, the processing moves to the case where the answer is No.

By turning on the access bit ACBA, the access failure display bit ACFB is also turned on at the same time.

Check whether the access failure bit ACFA including the status display bit of the status register STRA is on. When the B system also accesses the same channel control device at the same time, the access failure bit ACFA is turned on. If Yes, perform the process; if No, perform the process below.

Turn off access bit ACBA.

Check the number of times the access bit ACBA was turned off and check whether it exceeds 2 times.

Set the wait time. Note that this wait time of the service processor SVPA is set to be different from that of the service processor SVPB.

Check whether the wait time has ended.
If Yes, perform the above processing.

Initiate access to the desired register of the channel control device.

Turn off access bit ACBA.

Read the status register STRA to see if the access failed. If Yes, the process ends abnormally, and if No, the process ends normally. Such processing is executed by a service processor program.

Immediately after the sequence ends due to an empty read of the service processor SVPA (the access bit ACBA is not turned on yet), the service
When processor SVPB requests an empty read, this request is executed successfully. As a result, both access bits ACBA and ACBB are turned on, but in service processor SVPA, access bit ACBA is turned off by processing , and similarly, in service processor SVPB,
By performing this process, the access bit ACBB is turned off. Therefore, both service processors SVPA and SVPB act as channel controllers at the same time.
It is possible to avoid situations where CHCA is accessed.

As is clear from the above description, according to the present invention, in a multi-system in which a service processor can provide services not only to its own channel control device but also to other channel control devices, The circuit configuration required for conflict control of service requests can be simplified.

[Brief explanation of the drawing]

Figure 1 shows an example of a multi-system, Figure 2 shows an example of a multi-system.
The figure shows the configuration of hardware used in the present invention, and FIG. 3 is a flowchart explaining the processing of the present invention. MACA and MACB...Main memory access control unit, CPUA and CPUB...Central processing unit, CHCA and
CHCB...Channel control device, SVPA and SVPB...
…Service processor, DTR _0-o …Multiple data registers, BUS…Bus, ANDA and
ANDB...AND circuit, STRA and STRB...Status register, ADRA and ADRB...Address register, SDBA and SDBB...Self system/other system designation bit, ACFA and ACFB...Access failure indication bit, ACBA and ACBB... …Access Bit.

Claims (1)

[Claims] 1. Each having a service processor.2
In a multi-system that is equipped with a network computer system and each of the above service processors can access not only its own channel control device but also the channel control devices of other systems, one of the service processors (SVPA) The access bit (ACBA) is set on when the other service processor (SVPB) is being accessed, and the status register (STRA) is set to state information to indicate that the other service processor (SVPB) is being accessed. an access failure indicator bit (ACFA) that is set when the other service processor (SVPB) is accessing; and a status register (STRB) that is set with status information. It has an access failure indication bit (ACFB) installed inside the system to indicate that one service processor (SVPA) is currently accessing, and the contents of the access bit (ACBA) of one system are used for accessing the other system. A signal line is provided to transfer the contents of the access failure indication bit (ACFB) of the other system to the access failure indication bit (ACFA) of one system. and when each of the service processor (SVPA) and service processor (SVPB) accesses the channel control device, (a) blankly reads the register of the channel control device and uses the status information as the status of its own system. - Store in the register, (b) check the status register of the own system to see if the above empty read has failed, and (c) check if the status information in the status register of the own system does not indicate failure. (d) After turning on the access bit of the own system, the access failure indication bit of the other system is set to on. (e) As a result of the check in (d) above, if the access failure indication bit does not indicate failure, execute the access; (f) As a result of the check in (d) above, the access failure indication If the bit indicates a failure, turn off the access bit, if the number of failures exceeds a predetermined value, terminate abnormally, and if the number of failures is less than a predetermined value, set a waiting time. , A contention control system characterized in that it is configured to have a function of repeating the process from turning on the access bit of the own system in (c) above after the end of the waiting time.