JPS6319091B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clip circuit for wave detection, and mainly provides a clip circuit that detects small signals with good distortion characteristics.

As a detection circuit for detecting a specific amplitude-modulated signal at a predetermined level or higher, for example, a clip circuit shown in FIG. 1 is used. In the circuit configuration shown in FIG. 1, 1 and 2 are input terminals, 3 is an output terminal, 4 is a driving power source, 5 is a constant current source circuit, 6,
7 is a pair of NPN transistors in a differential pair configuration for detection; 8 and 9 are a pair of PNP transistors in a differential pair configuration for correcting distortion; 10, 11, 12
13 is an input terminal for setting the clip level, and 14 is a detection OR transistor for regulating the output level. In this circuit, when a predetermined DC voltage is applied to input terminal 2 and input terminal 13 and an amplitude modulation signal is input to input terminal 1, a half-wave output signal clipped at a predetermined level is obtained. FIG. 2 is a characteristic diagram showing the relationship between the input signal I amplitude-modulated with a triangular wave and its detection output. That is, according to the circuit shown in FIG. 1, distortion is generated in the output signal O ₁ in a signal region where the input level is low, for example, in the range of V _D in FIG. 2.

Here, let's take a closer look at the distortion of the output signal that accompanies the operation of the circuit shown in FIG. As a prototype of the conventional circuit shown in FIG. 1, a general clip circuit is shown in FIG. 3, and an example of the operating characteristics of the circuit is shown in FIG. In the clip circuit shown in Fig. 3, when the input signal voltage at input terminal 1 is V ₁ , the DC input voltage at input terminal 2 is V ₂ , the output voltage at output terminal 3 is V ₀ , and V ₁ ≫ V ₂ The base-emitter potential of transistor Q ₁ is V _BE11 , V ₁ V ₂
The base-emitter potential of transistor Q ₁ when V ₁ is V 1 , V _BE20 is the base-emitter potential of transistor Q ₂ when V ₁ is V ₂ , and the base-emitter potential of transistor Q ₂ when V ₁ ≪ V ₂ is Emitter potential
V _BE21 and the input/output characteristics are as follows: When V ₁ ≫ V ₂ , V ₀ = V ₁ − V _BE11 ...(1) When V ₁ V ₂ , V ₀ = V ₁ − V _BE10 = V ₂ −V _BE20 ……(2) When V ₁ ≪V ₂ , it is expressed as V ₀ =V ₂ −V _BE21 ……(3). In equation (1) above, transistor Q ₁ is in the on state, transistor Q ₂ is in the off state, and (2)
In the equation, both transistors Q ₁ and Q ₂ are in the on state,
In equation (3), transistor Q ₁ is in the off state and transistor Q ₂ is in the on state. The ideal input/output characteristics are dV ₀ /dV ₁ =1 when V ₁ >V ₂ and dV ₀ /dV ₂ =1 when V ₁ <V ₂ . However, in the case of V ₁ V ₂ where the input levels of V ₁ and V ₂ are close to each other, changes in the base-emitter potential V _BE of transistors Q ₁ and Q ₂ deteriorate the linearity of the input/output characteristics, and the output This is a factor that causes distortion in the signal. The output region where the distortion occurs is the range of V _D in FIG. 2, and this can be expressed mathematically as shown in the following equation (4).

V _D = (V _BE11 −V _BE10 ) +V _BE21 −V _BE20 ) ...(4) On the other hand, the base-emitter potential V _BE is
(〓) and emitter current I _E , V _BE =
It is given by (kT/q)ln(I _E /I _S ). here,
I _S : Reverse saturation current, k: Boltzmann constant, q:
It is the elementary quantity of electricity. Constant current source circuit 5 in Fig. 2
If the amount of current is I _O , I _E = I _O , and to simplify the equation, if we set kT/q = V _T , the following relationship holds true.

When V ₁ ≫V ₂ or V ₁ ≪V ₂ , V _BE = V _T ln ( _IO / I _S ) = V _BE11 = V _BE21 ...(5) When V ₁ = V ₂ , V _BE = V _T ln [(I _O /2) / I _S ] = V _BE10 = V _BE20 ...(6) From equations (5) and (6) above, V _D in equation (4) above can be expressed as follows. Can be done.

V _D = 2V _T ln2 ...(7) In other words, in the circuit shown in Figure 3, the output signal is 2V _T
Distortion occurs when it is in the range of ln2.

FIG. 4 shows an example of the operating characteristics of the circuit shown in FIG. 3, obtained by applying an amplitude-modulated input signal V ₁ to terminal 1 and applying a predetermined DC potential V ₂ to terminal 2.
Distortion occurs in the output signal O ₂ within the range of V _D expressed by the above equation (7).

Figure 5 is proposed to reduce the output distortion in the circuit shown in Figure 3 above, and the input/output characteristics of this circuit are also shown by equations (1), (2), and (3). . However, according to this circuit, there is a slight change in the base-emitter potential V _BE , and depending on this, V _D also changes to some extent. That is, R ₁ = R ₃ ,
Assuming that the DC current amplification factor h _FE of the transistor is sufficiently large, when V ₁ ≫ V ₂ , V _BE11 = V _T ln (I _C11 / I _S ) ...(8) R ₁ I _C11 = R ₂ I _E31 +V _BE31 ...(9) I _O = I _C11 + I _E31 ...(10) The following relationships hold true. Here, I _C11 is the collector current of transistor Q ₁ when V ₁ ≫ V ₂ , and I _E31 is V ₁
≫Emitter current of transistor Q ₃ when V ₂ ,
V _BE31 is _the base-emitter potential of transistor _Q3 when _V1≫V2 . From the above equations (8) and (9), the following relationship is obtained: I _C11 = (R _{2 IO} + V _BE31 )/(R ₁ + R ₂ ) (11). On the other hand, transistor Q ₃ ,
Since Q ₄ has the same characteristics and R ₁ = R ₃ , V ₁
When ≪V ₂ , the same relationships as the above equations (8) and (11) are derived as follows.

V _BE21 = V _T ln (I _C21 / I _S ) = V _BE11 ... (12) I _C21 = (R ₂ I _O + V _BE41 ) / (R ₃ + R ₂ ) = I _C11 ... (13) However, I _C21 is a transistor when V ₁ ≪ V ₂
The collector current of Q ₂ , V _BE41 , is the base-emitter potential of transistor Q ₄ when V ₁ <<V ₂ .

Also, when V ₁ = V ₂ , V _BE = V _T ln (I _C10 / I _S ) = V _BE10 = V _BE20 ... (14) R ₁ I _C10 = R ₂ (I _E30 + I _E40 ) + V _BE30 ... …(15) I _O = I _C10 + I _C20 + I _E30 + I _E40 …(16) However, V _E30 and V _E40 are the base-emitter potentials of transistors Q ₃ and Q ₄ when V ₁ = V ₂ , I _C10 and I _C20 are the collector currents of transistors Q ₁ and Q ₂ respectively when V ₁ = V ₂ , and I _E30 and I _E40 are
Transistors Q ₃ and Q ₄ when V ₁ = V ₂ respectively
is the emitter current.

Here, since the characteristics of each transistor are equivalent to each other, there are relationships such that I _C10 = I _C20 and I _E30 = I _E40 . The range of V _D in this circuit is determined by the third
As in the case of the illustrated circuit, using the above equations (12) to (14) and calculating from the above equation (4), V _D = 2V _T ln (I _C11 /I _C10 ) ...(17) . Therefore, the conditions for this circuit to have smaller output distortion than the circuit shown in FIG. 3 are (7)
As can be seen by comparing equation (17), I _C11 /
When I _C10 <2. For this purpose, the following relationship must be satisfied using the relationships derived from the above equation (11) and the above equations (15) and (16).

I _C11 /I _C10 = (1 + R ₂ / R ₁ + R ₂ ) (1 + V _BE31 −V _BE30
/R ₂ I _O + V _BE30 ) < 2...(18) In other words, from the above equation (18), when selecting circuit constants to increase R ₁ > R ₂ and R ₂ I _O , the output distortion The range of region V _D can be made smaller. Figure 6 shows the amplitude modulation signal at input terminal 1.
This is an example of the operating characteristics when V ₁ and DC voltage V ₂ are applied to input terminal 2, and the half-wave detection output signal O ₃ appearing at output terminal 3 is as shown in Fig. 4 (the broken line in the figure indicates this). This indicates that the range of V _D is reduced compared to the corresponding

Now, if we go back to the conventional clip circuit shown in FIG.
A control transistor 14 having a third input terminal 13 is added to the illustrated circuit. In this circuit, the input voltage V ₃ applied to the input terminal 13 is V ₁
When ≫V ₃ and V ₂ ≫V ₃ , the transistor 14 is in an off state, so its operation is the same as that of the circuit shown in FIG. 5 above. Therefore, when looking at the input/output characteristics in the case of V ₁ ≫V ₂ and V ₂ ≪V ₃ under actual operating conditions, as in equations (1) to (3) above, when V ₁ ≫V ₃ , V ₀ = V ₁ − _{V BE11} ... (19) When V ₁ = V ₃ , V ₀ = V ₁ − V _BE10 = V ₃ − V _BE50 ... (20) When V ₁ ≪ V ₃ , V ₀ = V ₃ − _{V BE51} ...(21) However, V _BE50 and V _BE51 are V ₁ = V ₃ and
This is the base-emitter potential of the transistor 14 (Q ₅ ) when V ₁ <<V ₃ .

The V _D range has the following relationship as in equation (4) above.

V _D = (V _BE11 − V _BE10 ) + (V _BE51 − V _BE50 ) …(22) Also, V _BE11 , V _BE10 (=V _BE50 ) and V _BE51 (8)
Similarly to equations (14) and (12), it is given as follows.

When V ₁ ≫ _{V 3} , V _BE11 = V _T ln (I _C11 / I _S ) ...(23) When V ₁ = V ₃ , V _BE10 = V _BE50 = V _T ln (I _C10 / I _S ) ...(24) When V ₁ ≪V ₃ , V _BE51 = V _T ln (I _C51 /I _S ) ...(25) Here, I _C11 is the voltage of transistor 14 due to the relationship V ₁ ≫ V ₃ . Since it is in the off state, it is equivalent to the above equation (11). Furthermore, I _C51 is equal to I _O due to the relationships of V ₁ <<V ₃ and V ₂ <<V ₃ , and I _C51 =I _O. moreover,
Since the transistors in I _C10 that are in operation are Q ₁ Q ₃ and Q ₅ , the following relationship holds true as in equations (15) and (16).

I _C10 + I _C50 + I _E30 = I _O ......(26) R ₁ I _C10 = R ₂ I _E30 + V _BE30 ... (27) And from the condition of V ₁ = V ₃ , there is a relationship of I _C10 = I _C50 . , from both equations (26) and (27) above, I _C10 can also be expressed as follows.

I _C10 = I _C50 = (R ₂ I _O + V _BE30 ) / (R ₁ + 2R ₂ ) ...(28) Regarding V _D , the above (23) to (25) are added to the above equation (22).
Substituting the formula, V _D =V _T ln (I _C11 · I _C51 /I _C10 ² ), and furthermore, from the relationship I _C51 = I _O , V _D becomes as shown in the following formula.

V _D =V _T ln(I _C11・I _O /I _C10 ² ) ...(29) Comparing the above equation (29) with the above equation (17),
The difference ΔV _D [Equation (29) - Equation (17)] is ΔV _D =V _T ln(I _O /I _C11 )...(30). In other words, when transistor 14 is operated in the on state in the circuit shown in FIG.
Rather than in the case of the circuit shown in the figure, the output distortion area increases by an amount corresponding to equation (30) above. An example of this operating characteristic is shown in Figure 2, where V ₁ ≫V ₂ V ₁
≪This is when an amplitude modulation signal is added to V ₁ at V ₃ and DC potentials are applied as V ₂ and V ₃ .

The present invention realizes a circuit that reduces the output distortion area existing in the clip circuit shown in FIG. I will explain in detail.

The circuit configuration of FIG. 7 includes transistors 6 and 7 in a differential pair configuration having input terminals 1 and 2.
and a differential pair configuration common to each emitter and each collector consisting of transistors 8 and 9 that respond in the same phase as these two transistors are provided in parallel, and the clip level of the input signal to the input terminal 1 is set. A control transistor 14 exists between the common constant current source circuit output terminal 3 of the differential pair transistors and the driving power supply terminal 4, and is controlled according to the current of the control transistor 14. A transistor 15 is connected in parallel to the transistors 8 and 9. That is, in this circuit, by providing the transistor 15, it has become possible to correct the output distortion when the above-mentioned transistor 14 is in the operating state.
Looking at the operation of this circuit, transistor 1
The collector resistor 16 of No. 4 is a current detection means for operating the transistor 15, and R ₁ =R ₄ .

First, if V ₁ ≫V ₃ and V ₂ ≫V ₃ , then V ₁ ≫V ₂
and if V ₂ ≪V ₃ and V ₁ ≪V ₂ and V ₁ ≪
For each case of V ₃ , either the side of transistors 7 and 9 or the side of transistors 14 and 15 is off, and therefore exhibits input/output characteristics equivalent to the circuit of FIG. The area increase of output distortion as shown in the above equation (30) in the circuit shown in the figure does not occur. In other words, the range of the output distortion area V _D in these cases is the same as in equation (17) above,
Looking at the characteristics of the output signal O ₄ , as shown by the solid line in FIG. 8, the clipping characteristics of half-wave detection are suppressed to a small V _D range, similar to the characteristics in FIG. 6. In addition,
V ₁ ' in FIG. 8 is an input signal, and the broken line is a similar characteristic example in the circuit of FIG. 1.

Next, considering the case of V ₁ = V ₂ = V ₃ ,
The base-emitter potential V _BE of each of the input transistors 6, 7, and 14 has the relationship of equation (14) above, that is, the same as in the case of the circuit shown in Figure 5, and V _BE =V _T ln (I _C10 /I _S ) ...(31) And I _C10 at this time is the fifth
Similar to the analysis using the illustrated circuit, it is obtained from the relationships of the following equations.

R ₁ I _C10 = R ₂ (I _E30 + I _E40 + I _E60 ) +V _BE30 …(32) I _C10 +I _C20 +I _C50 +I _E30 +I _E40 +I _E60 =I _O …(33) I _C10 =I _C20 =I _C50 ...(34) From the above relationship, (I _E30 + I _E40 + I _E60 ) = I _O -3I _C10 ... (35) Therefore, I _C10 = (R ₂ I _O + V _BE30 ) / (R ₁ + 3R ₂ ) ...(36) In the case of V ₁ ≫V ₂ and V ₁ ≫V ₃ , the state is the same as V ₁ ≫V ₂ in the circuit of Figure 5, so Equations (8) to (11)
Using the same analysis method as the equation, the following relationship is derived: I _C11 = (R _{2 IO} + V _BE31 )/(R ₁ + R ₂ )...(37). This is completely equivalent to the above equation (11).

On the other hand, when V ₁ <<V ₂ , V ₁ <<V ₃ , in the circuit shown in FIG. 7, each transistor Q ₂ , Q ₄ , Q ₅ and Q _{6 is V2}
The situation is the same as in the case of , and therefore, the same relational expressions as the above-mentioned equations (14), (15), and (16) are obtained.
From these relational expressions, the following equation (38) is derived.

I _C21 = I _C51 = (R ₂ I _O + V _BE40 )/(R ₁ +2R ₂ ) ...(38) And at this time, the distortion caused by V _BE is (4)
Since it is equivalent to that expressed by the following expression (39), it is expressed by the following expression (39).

V _D = V _T ln (I _C11 / I _C10 ) + V _T ln (I _C21 / I _C10 ) = V _T ln (I _C11 × I _C21 / I _C10 ² ) ...(39) Therefore, this formula can be changed to the above ( 7) or the above (17)
As can be seen from the comparison with the equation (39), if the condition I _C11 ·I _C21 /I _C10 ² <4 is satisfied in the above equation (39), the improvement in output distortion by V _BE51 is not lost. To find this condition, I _C11・I _C21 /I _C10 ² = (R ₂ I _O + V _BE31 ) (R ₂ I _O + V _BE41
)(R ₁ +3R ₂ ) ² /(R ₁ +R ₂ )(R ₁ +2R ₂ )(R ₂ I _O +V _BE30
) ² = (1+R ₂ /R ₁ +2R ₂ ) (1+2R ₂ /R ₁ +R ₂ ) (1+V _BE31 −V _BE30 /R ₂ I _O +V _BE30 )(1+V _BE41 −
V _BE40 /R ₂ I _O +V _BE30 )<4...(40). As is clear from this, R ₁ = R ₃ = R ₄ ,
By setting R ₂ and I _O to satisfy the above equation (40), the output distortion region can be improved even when the inputs of V ₁ , V ₂ , and V ₃ are close to each other. will not be lost.

[Brief explanation of the drawing]

1 and 2 are clip circuit diagrams of conventional circuits and their characteristic diagrams, FIGS. 3 and 5 are exploded circuit diagrams for explaining the operating principles of the above conventional example and the circuit of the present invention, and FIG. 4 , Figure 6 is Figure 3, Figure 5
7 and 8 are clip circuit diagrams and waveform diagrams of embodiments of the present invention. 1...Signal input terminal, 2...DC voltage input terminal, 3...Output terminal, 4...Drive power supply terminal, 5
...Constant current source circuit, 6,7...NPN transistor, 8,9...PNP transistor, 10,11,
12...Resistor, 13...Control voltage input terminal, 1
4...NPN transistor, PNP...PNP transistor, 16...Resistor.

Claims (1)

[Claims] 1 Each emitter and each collector consists of first and second transistors of a first differential pair configuration having first and second input terminals, and third and fourth transistors that respond in the same phase as these two transistors. A fifth control transistor is provided in parallel with a common second differential pair configuration, and sets a clip level of the input signal to the first input terminal. A sixth transistor located between the circuit output terminal and the drive power source and controlled according to the current of the fifth transistor is connected in parallel to both transistors of the second differential pair. A clip circuit characterized by: