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JPS6320086B2 - - Google Patents
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JPS6320086B2 - - Google Patents

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Publication number
JPS6320086B2
JPS6320086B2 JP54134222A JP13422279A JPS6320086B2 JP S6320086 B2 JPS6320086 B2 JP S6320086B2 JP 54134222 A JP54134222 A JP 54134222A JP 13422279 A JP13422279 A JP 13422279A JP S6320086 B2 JPS6320086 B2 JP S6320086B2
Authority
JP
Japan
Prior art keywords
input
power supply
voltage
output
overvoltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54134222A
Other languages
Japanese (ja)
Other versions
JPS5658727A (en
Inventor
Kikuo Tomita
Yasuharu Kamata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13422279A priority Critical patent/JPS5658727A/en
Publication of JPS5658727A publication Critical patent/JPS5658727A/en
Publication of JPS6320086B2 publication Critical patent/JPS6320086B2/ja
Granted legal-status Critical Current

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  • Emergency Protection Circuit Devices (AREA)

Description

【発明の詳細な説明】 本発明は、入力多重化電源装置に関する。[Detailed description of the invention] The present invention relates to input multiplexed power supplies.

二つの交流入力を整流して出力を合流させ、そ
の結果として電源電圧を得る従来の入力2重化電
源装置の構成図を第1図に示す。図で、10,2
0はそれぞれ別系統の交流電源に接続される入力
端子、30,31は上記入力端子10,20を介
して得られる交流電圧を整流する整流回路であ
り、この2つの整流回路出力を合流させて、出力
端子40から直流電源電圧を取り出すようにして
いる。整流回路30,30はそれぞれダイオード
11,12,13,14,15,16,21,2
2,23,24,25,26をもつて構成されて
いる。更に、入力電圧の不足、しや断による負荷
の動作停止を防ぐために実開昭53−161231号公報
に示されているごとく、2つ以上の入力源に対し
て各々直流制御電源(AVR)を介して安定させ
たあと、ダイオードを介してつきあわせて多重化
を図る多重直流電源の保護装置があるがAVRの
出力電位がダイオードでの電圧降下を無視できな
い様な低電圧の場合、つき合わせ後の出力電圧の
安定度が計れないという欠点を有する。上記欠点
をなくすためには、AVRの前段で入力の多重化
を計る必要がある。
FIG. 1 shows a configuration diagram of a conventional dual-input power supply device that rectifies two AC inputs and combines the outputs to obtain a power supply voltage as a result. In the figure, 10,2
0 is an input terminal connected to an AC power source of a separate system, 30 and 31 are rectifier circuits that rectify the AC voltage obtained through the input terminals 10 and 20, and the outputs of these two rectifier circuits are combined. , the DC power supply voltage is taken out from the output terminal 40. The rectifier circuits 30, 30 include diodes 11, 12, 13, 14, 15, 16, 21, 2, respectively.
2, 23, 24, 25, and 26. Furthermore, in order to prevent the load from stopping due to insufficient input voltage or failure, as shown in Japanese Utility Model Application No. 53-161231, a DC control power source (AVR) is connected to each of two or more input sources. There is a protection device for multiple DC power supplies that attempts to multiplex the DC power supply by stabilizing it through a diode and then combining it through a diode. The disadvantage is that the stability of the output voltage cannot be measured. In order to eliminate the above drawbacks, it is necessary to multiplex the inputs before the AVR.

以上の構成の電源装置に対する入力端子10,
20に接続する交流電源の一例を第2図に示す。
この図で、交流電源50,51は中央接地形のス
ター結線の電源である。かかる構成の交流電源5
0,51の事例では、出力端子40からは比較的
安定した直流出力電圧が得られることが確認され
ている。具体的には十分に実用にたえうるピーク
電圧は、入力電圧の実効電圧Eの√2倍なる整流
電圧となる。然るに、現場での実装条件や回路条
件等によつては、デルタ結線の交流電源を入力端
子10,20に交流電源として接続する事例があ
る。このデルタ結線の交流電源を使用する従来例
を第3図に示す。この図はデルタ結線の交流電源
60,61を入力端子10,20に接続させた構
成としている。然るに、交流電源60,61は中
点接地されていないため、入力電源の2系統以上
の1線又は1線以上に接地インピーダンス80,
81が存在すると、出力端子40から異常に高い
出力電圧が発生することがあつた。尚、図で70
はダミー抵抗であり、異常電圧が発生した場合、
この異常電圧に伴う過電流を該抵抗70を介して
流すことによつて、異常電圧をある程度抑制する
働きをなす。しかしながら、ダミー抵抗70を設
けても、本質的に異常電圧の解消は不可能であつ
た。以上の異常電圧発生経過を以下、詳述する。
Input terminal 10 for the power supply device configured as above,
An example of an AC power supply connected to 20 is shown in FIG.
In this figure, AC power supplies 50 and 51 are star-connected power supplies with a central ground plane. AC power supply 5 having such a configuration
In the case of 0.51, it has been confirmed that a relatively stable DC output voltage can be obtained from the output terminal 40. Specifically, a peak voltage that is sufficiently practical is a rectified voltage that is √2 times the effective voltage E of the input voltage. However, depending on on-site mounting conditions, circuit conditions, etc., there are cases where a delta-connected AC power source is connected to the input terminals 10 and 20 as an AC power source. A conventional example using this delta-connected AC power source is shown in FIG. This figure shows a configuration in which delta-connected AC power supplies 60 and 61 are connected to input terminals 10 and 20. However, since the AC power supplies 60 and 61 are not grounded at the center, the ground impedance 80,
81, an abnormally high output voltage may be generated from the output terminal 40. In addition, 70 in the figure
is a dummy resistor, and when abnormal voltage occurs,
By causing the overcurrent associated with this abnormal voltage to flow through the resistor 70, the abnormal voltage is suppressed to some extent. However, even with the provision of the dummy resistor 70, it was essentially impossible to eliminate the abnormal voltage. The above abnormal voltage generation process will be described in detail below.

交流電源60,61の接地インピーダンス8
0,81の値をZ〓c、Z〓c′とし、交流電源60での
ca,ab,bcの線間電圧E〓ca,E〓ab,E〓bcとし、交流電源61でのc′a′,a′b′,b′c′の線間

圧E〓ca′,E〓ab′,E〓bc′を とする。
Grounding impedance 8 of AC power supplies 60 and 61
Let the values of 0.81 be Z〓 c and Z〓 c ′, and
Line voltage E〓 ca , E〓 ab , E〓 bc of ca, ab , bc Then, the line voltages of c′a′, a′b ′, b′c at AC power supply 61 are shall be.

説明の都合上、E〓ca,E〓ca′の各相を取り出して
等価回路を示したものが第4図である。
For convenience of explanation, FIG. 4 shows an equivalent circuit for each phase of E〓 ca and E〓 ca ′.

今、VZc>E〓ca′の時 となり、VZc<E〓ca′の時、 VD=E〓ca ………(4) となる。但し、R〓Lはダミー抵抗70の値である。
(3)式の最大値VDnaxは、(2)式のθ=πの時であり、 となる。以上の(4)、(5)式をグラフで示したものが
第5図である。この図から明らかなように、整流
出力ピーク電圧VDnaxが√2Eとなる時のインピ
ーダンスをZ〓とする時、接地インピーダンス8
0,81の和(Z〓c+Z〓c′)が上記インピーダンスZ

と比べて大きいか小さいかによつて、ピーク電圧
VDnaxの大きさが大きく変つてくる。即ち、Z〓c
Z〓c′<Z〓の時には、√2Eより大となり、最大で
は2√2Eにも達し、過大な出力電圧が発生する
ことになる。以上の関係は2重化以上の多重化に
もあてはまる。なお、実開昭53−161231号公報に
示されるような一系統の多重直流電源では上記の
ような接地異常による過電圧の問題は発生しな
い。
Now, when V Zc > E〓 ca When V Zc <E〓 ca ′, V D =E〓 ca ………(4). However, R〓 L is the value of the dummy resistor 70.
The maximum value V Dnax in equation (3) is when θ=π in equation (2), becomes. FIG. 5 is a graph showing the above equations (4) and (5). As is clear from this figure, when the impedance when the rectified output peak voltage V Dnax is √2E is Z〓, the ground impedance is 8
The sum of 0,81 (Z〓 c +Z〓 c ′) is the above impedance Z

Peak voltage depending on whether it is larger or smaller than
The size of V DNAx changes greatly. That is, Z〓 c +
When Z〓 c ′<Z〓, it becomes larger than √2E, reaching 2√2E at the maximum, and an excessive output voltage is generated. The above relationship also applies to duplication or multiplexing. Incidentally, in a single system multiple DC power supply as shown in Japanese Utility Model Application Publication No. 53-161231, the above-mentioned problem of overvoltage due to ground abnormality does not occur.

本発明の目的は、出力の過電圧発生時にはこれ
を検出して負荷であるAVR等の装置保護を行わ
しめるようにした入力多重化電源装置を提供しよ
うとするものである。
SUMMARY OF THE INVENTION An object of the present invention is to provide an input multiplex power supply device that detects when an output overvoltage occurs and protects a device such as an AVR that is a load.

本発明の要旨は、出力の過電圧を検出し、この
検出結果に基づき多重化された交流電源入力の該
当入力を遮断せしめるようにした点にある。以
下、図面により本発明を詳述する。
The gist of the present invention is to detect an output overvoltage and, based on the detection result, to shut off the corresponding input of multiplexed AC power supply inputs. Hereinafter, the present invention will be explained in detail with reference to the drawings.

第6図は本発明の実施例を示す図である。本実
施例の特徴は、各入力電源側に遮断器97,98
を設けたこと、及び出力電圧が過大になつたこと
を検出する過電圧検出回路90を設けたこと、更
にこの過電圧検出回路90で過電圧検出を行つた
場合、各遮断器97,98に遮断指令を与えて交
流電源の入力を遮断させる遮断回路95,96を
設けたことにある。
FIG. 6 is a diagram showing an embodiment of the present invention. The feature of this embodiment is that circuit breakers 97 and 98 are installed on each input power supply side.
and an overvoltage detection circuit 90 that detects when the output voltage has become excessive.Furthermore, when the overvoltage detection circuit 90 detects an overvoltage, it issues a shutdown command to each circuit breaker 97, 98. The reason is that cut-off circuits 95 and 96 are provided to cut off the input of AC power.

かかる構成で過電圧を過電圧検出器90で検出
した時には、過電圧検出信号91,92が発生
し、遮断回路95,96を作動させ、対応する遮
断器97,98を遮断させる。これによつて、出
力から過電圧が発生することを防止でき、出力側
の負荷への悪影響を防止できた。尚、過電圧検出
時には、必ずしも両交流電源入力をロツクする必
要はない。これは、完全に電源停止になることを
防止するためであり、また、一方の電源入力停止
のみで異常電圧の発生を防止できるからである。
ダミー抵抗70の値としては、入力交流電圧
200V、2入力の規定接地インピーダンスを日本
電子工業技術基準ACZ002の接地電流15mA、即
ち接地抵抗13.4KΩにすると、RL>20KΩにてダ
ミー抵抗本来の機能である過電圧防止が可能とな
る。
When an overvoltage is detected by the overvoltage detector 90 in such a configuration, overvoltage detection signals 91 and 92 are generated, and the interrupting circuits 95 and 96 are activated to interrupt the corresponding circuit breakers 97 and 98. This made it possible to prevent overvoltage from being generated from the output, thereby preventing any adverse effects on the load on the output side. Note that it is not always necessary to lock both AC power supply inputs when overvoltage is detected. This is to prevent the power supply from being completely stopped, and also because the generation of abnormal voltage can be prevented by stopping only one power supply input.
The value of the dummy resistor 70 is the input AC voltage
If the specified grounding impedance of 200V and 2 inputs is set to the grounding current of 15mA according to Japan Electronics Industry Technical Standard ACZ002, that is, the grounding resistance is 13.4KΩ, overvoltage prevention, which is the original function of the dummy resistor, becomes possible when R L >20KΩ.

本実施例では三相入力について述べたが相数が
1以上であれば全てに応用できる。また、二重化
入力について述べたが三重化以上の多重について
も応用できる。
In this embodiment, three-phase input has been described, but the present invention can be applied to any case where the number of phases is one or more. Further, although the description has been made regarding duplex input, the present invention can also be applied to triple or higher multiplexing.

本発明によれば中点接地でない入力電源を受電
し二重化入力を行うことができ内部に絶縁トラン
ス不要の軽量で安価な二重化入力電源を得ること
ができる。
According to the present invention, an input power source that is not grounded at the center point can be received and redundant input can be performed, and a lightweight and inexpensive redundant input power source that does not require an internal insulation transformer can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は入力2重化電源の構成図、第2図、第
3図はその具体例図、第4図は等価回路図、第5
図は接地インピーダンスと整流出力ピーク電圧と
の関係図、第6図は本発明の実施例図である。 30,31……整流回路、90……過電圧検出
回路、95,96……遮断器遮断回路、97,9
8……遮断器。
Figure 1 is a configuration diagram of a redundant input power supply, Figures 2 and 3 are specific examples thereof, Figure 4 is an equivalent circuit diagram, and Figure 5 is a diagram of an equivalent circuit.
The figure is a relationship between ground impedance and rectified output peak voltage, and FIG. 6 is a diagram showing an embodiment of the present invention. 30, 31... Rectifier circuit, 90... Overvoltage detection circuit, 95, 96... Circuit breaker breaking circuit, 97, 9
8... Circuit breaker.

Claims (1)

【特許請求の範囲】[Claims] 1 2系統以上の交流入力を個別整流する手段
と、該個別整流された各整流電圧をつき合わせて
整流出力を得る手段と、該整流出力を入力とし直
流安定化出力を得る直流制御手段と、上記各系統
の交流入力の1線以上が同時に接地された際の上
記整流出力の過大電圧を検出する過電圧検出器
と、該過電圧検出器で過電圧を検出した時に該検
出器の出力によつて上記各系統からの少なくとも
一方の入力を遮断させる入力遮断手段を有するこ
とを特徴とした入力多重化電源装置。
1. means for individually rectifying two or more systems of alternating current input; means for combining the individually rectified rectified voltages to obtain a rectified output; and direct current control means for obtaining a stabilized direct current output using the rectified output as input; an overvoltage detector that detects overvoltage of the rectified output when one or more AC input wires of each of the above systems are grounded at the same time; An input multiplexing power supply device comprising an input cutoff means for cutting off at least one input from each system.
JP13422279A 1979-10-19 1979-10-19 Input multiplexing power source Granted JPS5658727A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13422279A JPS5658727A (en) 1979-10-19 1979-10-19 Input multiplexing power source

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13422279A JPS5658727A (en) 1979-10-19 1979-10-19 Input multiplexing power source

Publications (2)

Publication Number Publication Date
JPS5658727A JPS5658727A (en) 1981-05-21
JPS6320086B2 true JPS6320086B2 (en) 1988-04-26

Family

ID=15123266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13422279A Granted JPS5658727A (en) 1979-10-19 1979-10-19 Input multiplexing power source

Country Status (1)

Country Link
JP (1) JPS5658727A (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53161231U (en) * 1977-05-26 1978-12-16

Also Published As

Publication number Publication date
JPS5658727A (en) 1981-05-21

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