JPS632154B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to an input gate protection device thereof.

In a conventional input gate protection device composed of a resistive element and a capacitive element, polysilicon containing impurities of one conductivity type, a diffusion layer, and the like are used as materials for forming both elements. In general, the input gate protection breakdown voltage increases as the values of the resistive element and capacitive element of the input gate protection device increase, and the area of the layout pattern also increases accordingly.

Furthermore, in recent years, layout patterns have become smaller, diffusion layers have become shallower in the wafer manufacturing process, and polysilicon film thickness has been reduced, with the aim of achieving higher density integration and improving electrical characteristics. The problem is that it is not only difficult to maintain input gate protection breakdown voltage for the resistive elements and capacitive elements that constitute current input protection devices, but also increases the layout pattern area. In other words, aluminum penetrates into the diffusion layer due to shallowing of the diffusion layer,
Efforts must be made to prevent the occurrence of so-called alloy spikes, and by reducing the thickness of the polysilicon film, the area of the layout pattern inevitably increases in order to obtain a predetermined resistance value. Therefore,
Even with recent improvements in manufacturing processes for high-density integration and improved electrical characteristics, input gate protection devices not only maintain a specified protection voltage, but also have a layout pattern area that is lower than that of conventional protection devices. We have to make it even smaller than the device itself.

The present invention has performance equivalent to or better than conventional protection voltage, and the area occupied by the layout pattern is smaller than that of conventional protection devices, making higher density integration possible. It is.

According to the present invention, a buried layer of an opposite conductivity type provided on a semiconductor substrate of one conductivity type is ohmicly connected to an input bonding pad and an input gate, respectively, and a buried layer is provided in the semiconductor substrate and the buried layer. Thus, an input gate protection device having a structure in which the semiconductor substrate and the diffusion layer containing impurities of the same conductivity type are ohmicly connected can be obtained.

The present invention will be explained with reference to the drawings, taking as an example an input gate protection device in a complementary MOS structure using a P-type buried layer on an N-type semiconductor substrate and comparing it with a conventional device.

FIG. 1a shows an example of a layout pattern of a conventionally implemented input gate protection device.
1b and 1c respectively show an equivalent circuit of FIG. 1a and a sectional view taken along line a--b in FIG. 1a. In FIGS. 1a, b, and c, an input bonding pad 11 is ohmicly connected to one end of a polysilicon resistor 12 containing N-type impurities. Next, the other end of the polysilicon resistor 12 is connected to the P-type buried layer 1.
It is ohmic-connected via an N-type diffusion layer 14 provided on 3 and an aluminum wiring 15, and further communicates with an input gate. Next, the P-type buried layer 13
is ohmicly connected to the aluminum wiring 17 of the GND power source via a P-type diffusion layer 16 containing a high concentration of P-type impurity. The operation of this protection device is to connect the bonding pad 1 to the GND electrode 17.
To explain the case where positive noise is applied to 1,
The applied noise current flows through the polysilicon resistor 12
The current flows through the diode 18 formed between the P-type buried layer 13 and the N-type diffusion layer 14 . This noise current is a reverse current when viewed from the diode 18, but the withstand voltage of this diode is usually 1.
Since it is approximately 5V, if noise higher than this voltage is applied, this diode becomes a sufficient current path to absorb the noise voltage and fulfill the function of protecting the input gate. However, in such a conventional input gate protection device, when the V-type diffusion layer is made shallow, aluminum penetrates into the N-type diffusion layer, and the N-type diffusion layer and P-type buried layer are separated. becomes completely conductive. Further, reducing the value of polysilicon resistance for the purpose of high-density integration makes the above-mentioned aluminum penetration more likely to occur.

In the present invention, attention is paid to the fact that the depth of the buried layer is deeper than that of the diffusion layer, so that aluminum penetration does not occur. Furthermore, the present invention provides an input gate protection device that can sufficiently satisfy a predetermined protection voltage even when high-density integration is achieved by omitting a polysilicon resistor.

FIG. 2a shows the layout pattern of an embodiment employing the present invention, and FIGS. 2b and 2c show the equivalent circuit of FIG. 2a and the layout pattern of FIG. 2a, respectively.
A cross-sectional view taken along a′-b′ is shown. In FIGS. 2a, b, and c, the input bonding pad 21 is electrically connected via a P-type buried layer 23 and a P-type diffusion layer 26 containing a high concentration of P-type impurity provided on the P-type buried layer 23. It is connected. Next, the wiring to the input gate is connected to the top of the P-type buried layer 23 and the N-type semiconductor substrate, which is ohmic-connected by an aluminum wiring 25 after obtaining a resistor 29 formed by the P-type buried layer 23 and the P-type diffusion layer 26. An N-type diffusion layer 24 containing a high concentration of N-type impurity is provided thereon, and is ohmicly connected to an aluminum wiring 27 of the Vc.c. power source. With this structure, even if high voltage noise is applied to the input bonding pad, the depth of the P-type buried layer is deeper than that of the diffusion layer, so the alloy spikes can prevent the P-type buried layer from being connected to the N-type substrate. conduction can be prevented. Here, the reason why the N-type diffusion layer is provided on the P-type buried layer is that it becomes effective when negative high voltage noise is applied to the input bonding pad. That is, the breakdown voltage of the diode 30 formed between the P-type buried layer and the N-type substrate is usually 100V.
If left as is, the input gate will be destroyed and the gate protection function will not be fulfilled. Therefore, an N-type diffusion layer containing a high concentration of impurities is provided on the P-type buried layer, and a diode with a low breakdown voltage is used. By forming 28, the gate protection function is ensured.

Although the embodiments of the present invention have been described using a P-type buried layer on an N-type substrate, the effects of the present invention can also be obtained when an N-type buried layer is used on a P-type substrate. It is possible.

[Brief explanation of the drawing]

FIG. 1a shows a layout pattern of a conventional input gate protection device, and FIG. 1b shows an equivalent circuit of FIG. 1a. Figure 1c is a-b of Figure 1a.
FIG. FIG. 2a shows a layout pattern of an input gate protection device according to the present invention, and FIG. 2b shows an equivalent circuit of FIG. 2a. FIG. 2c is a sectional view taken along line a'-b' of FIG. 2a. In the figure, 11, 21... bonding pad for input, 12... polysilicon resistor containing N-type impurity, 13, 23... P-type buried layer, 14, 2
4...N-type diffusion layer, 15, 25, 17, 27...
...Aluminum wiring, 16,26...P-type diffusion layer, 18,28,30...diode, 29...
It is resistance.

Claims (1)

[Claims] 1 A buried layer of an opposite conductivity type provided on a semiconductor substrate of one conductivity type is ohmicly connected to an input bonding pad and an input gate, and is further provided in the semiconductor substrate and the buried layer and is the same as the semiconductor substrate. A complementary insulated gate field effect semiconductor integrated circuit device characterized in that a diffusion layer containing a conductive type impurity is ohmicly connected.