JPH028462B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wiring method for semiconductor integrated circuits.

One method for increasing the density of semiconductor integrated circuits is to miniaturize patterns, and it is now becoming possible to form submicron patterns at the laboratory level. Another method is multilayer wiring.
When a large number of elements are integrated into a semiconductor integrated circuit, the amount of wiring connecting the elements increases in proportion to the number of integrated elements, so a large space must be provided for the wiring. In particular, since integrated circuits are basically planar circuits, the same wiring layers are never allowed to intersect. For this reason, the wiring becomes long, and the area required only for the wiring tends to become large. In order to prevent this increase in area, multilayer wiring technologies have been developed and are commercially available, such as a two-layer wiring structure of polycrystalline silicon wiring and aluminum wiring, and furthermore, using two layers of polycrystalline silicon or two layers of aluminum wiring. It is also used in products.

However, when using such multilayer wiring technology,
Since it is necessary to establish a connection between each wiring layer, the contact area for this purpose also becomes wider as the number of wiring layers increases. FIG. 1 shows an example of a conventional multilayer wiring, where a shows the cross-sectional structure and b shows the planar shape. forming a first polycrystalline silicon layer 3 on an insulating film 2 on the surface of a semiconductor substrate 1;
Second polycrystalline silicon layer 5 via interlayer insulating film 4
form. In this first polycrystalline silicon 3, impurities such as boron and phosphorus are diffused into the second polycrystalline silicon 5 as necessary to obtain a desired sheet resistance value. Next, after an insulating film 6 is deposited on the entire surface, contact holes 8 and 9 are formed to expose the surfaces of the polycrystalline silicon 3 and 5, and an aluminum wiring 7 is formed to form the first polycrystalline silicon 3. and the second polycrystalline silicon 5 are electrically connected. When such a multilayer wiring structure is constructed, as shown in plan view b, both wiring patterns must be made large in the contact area in order to make contact between aluminum and polycrystalline silicon. Even though the polycrystalline silicon 3 and 5 are connected, extra space is required for the aluminum wiring 7. Furthermore, as can be easily seen from FIG. 1a showing the cross-sectional structure, when forming the contact hole in the insulating film, the contact hole 8 only needs to be etched in the insulating film 6, whereas the contact hole 8 only needs to be etched in the insulating film 6. In this case, an unreasonable situation arises in that the insulating films 4 and 6 must be etched together.

Therefore, in recent years, after first forming a first polycrystalline silicon wiring, a second polycrystalline silicon wiring is formed via an interlayer insulating film.
A wiring structure has been proposed in which polycrystalline silicon wiring is formed and both layers are bonded through a contact hole provided in an interlayer insulating film.

FIGS. 2a and 2b show the above-mentioned proposal and are diagrams for explaining the present invention. In the figure, a represents the cross-sectional structure, and b represents the planar shape. First polycrystalline silicon 12 is formed on insulating film 11 formed on the surface of semiconductor substrate 10 . This polycrystalline silicon can be diffused with impurities as necessary to obtain a desired sheet resistance. Furthermore, after forming an insulating film 13 as an interlayer insulating film, a contact hole 16 is opened in this insulating film 13 to expose polycrystalline silicon 12. A second polycrystalline silicon layer 14 is then deposited and brought into contact with the first polycrystalline silicon 12 at contact holes 16 . At this time, the second polycrystalline silicon 14 is formed without impurities and then pre-deposited, or it is formed with polycrystalline silicon containing impurities and then annealed at, for example, 1000°C.
By introducing the same impurity as the first polycrystalline silicon 1, it is possible to establish ohmic contact between both polycrystalline silicones 12 and 14. Next, if necessary, an insulating film 15 is deposited on the entire surface,
Protect the second polycrystalline silicon layer 14. This eliminates the need to use other wiring such as aluminum for electrical contact between the first polycrystalline silicon 12 and the second polycrystalline silicon 14, and also eliminates the need for extra space. has. Furthermore, when etching contact holes, there is no unreasonable need to etch insulating films of different thicknesses at the same time as in the conventional method.

However, this alone cannot be said to have sufficiently achieved high integration of semiconductor integrated circuits.

Therefore, the present invention aims to reduce the number of resistors formed in the substrate by introducing resistance into the wiring in a semiconductor structure having a multilayer wiring structure, thereby achieving efficient high integration of semiconductor devices. It is something that we try to do.

FIG. 3 shows an embodiment of the present invention, in which a shows the cross-sectional structure and b shows the planar shape. An insulating film 18 is formed on the surface of a semiconductor substrate 17, and a first polycrystalline silicon 19 is formed thereon. This first polycrystalline silicon 19
An impurity exhibiting the first conductivity type is diffused into. Next, an interlayer insulating film 20 is deposited, and a contact hole 23 is formed.
A hole is opened to expose polycrystalline silicon 19. Next, polycrystalline silicon 21 in which impurities are not diffused
and polycrystalline silicon 22 containing impurities are formed at the same time. The polycrystalline silicon 21 at this time is
The pattern formation is performed simultaneously with the polycrystalline silicon 22 to form the same shape.
Further, the conductivity type of the impurity contained in the polycrystalline silicon 22 may be the above-mentioned first conductivity type, or may be the opposite conductivity type. Since polycrystalline silicon 21 containing no impurities has high electrical resistance,
First polycrystalline silicon 19 and polycrystalline silicon 2
2 is the same as a high-resistance connected circuit, and a high-resistance element is configured in the contact 23 area. Polycrystalline silicon 21 containing no impurities may be formed on the surface of polycrystalline silicon 19 before forming the insulating film 20, and this is considered to be the first polycrystalline silicon, and 22 is considered to be the second polycrystalline silicon. .
Furthermore, without forming this polycrystalline silicon 21,
It is also possible to form a high resistance element by directly contacting polycrystalline silicon 19 and polycrystalline silicon 22 through contact hole 23, and in this case, the impurity diffused into polycrystalline silicon 22 is of the first conductivity type. It must have a conductivity type opposite to that of the When forming polycrystalline silicon 21 that does not contain impurities, it need not be the same shape as polycrystalline silicon 19 or 22, and it goes without saying that it is sufficient that it is formed to at least cover contact hole 23.

As described above, the first polycrystalline silicon layer and the second polycrystalline silicon layer can be brought into direct contact via a contact hole at a desired position of the insulating film that insulates them, thereby forming a multilayer wiring structure. It improves the integration of semiconductor integrated circuits by eliminating extra space, and eliminates the conventional unreasonableness of contact hole etching.
Furthermore, the present invention has many excellent features, such as the ability to form very fine high resistance elements made of polycrystalline silicon. With the above configuration, the following effects can be obtained.

That is, (a) since a polycrystalline silicon layer into which no impurities have been introduced has high electrical resistance, the first polycrystalline silicon layer and the second polycrystalline silicon layer are connected to each other with high resistance. This makes it possible to effectively form a resistive element such as an additional resistor for SRAM.

(b) When two wires of different conductivity types are directly connected, a diode characteristic occurs at the connection of the wires, and a rectification effect occurs that causes current to flow in only one direction. By interposing the wires, it becomes possible to connect wires of different conductivity types.

This is extremely important for recent semiconductor integrated circuits, which use P-type impurity wiring for Pch transistors and N-type impurity wiring for Nch transistors, in order to make direct contact with the diffusion layer of the substrate using polycrystalline silicon wiring. This is effective and can be connected regardless of the impurity characteristics of the wiring by interposing the P-type impurity wiring drawn out from the diffusion layer of the substrate and the polycrystalline silicon into which no impurities have been introduced.

(c) Since the high-resistance portion of the polycrystalline silicon wiring into which impurities have been introduced and the high-resistance portion of polycrystalline silicon into which no impurities have been introduced are made of the same material, there is good compatibility between the wiring and the resistor, and cracks at the connection portions are less likely to occur.

(d) By forming a resistor in the wiring instead of forming a resistor in the substrate as in the past, it becomes possible to increase the degree of integration of semiconductor integrated circuits.

(E) As shown in FIG. 3a of the present application, since the resistive layer of the present invention only needs to be formed to cover at least the contact hole, the second wiring layer and the resistive layer are formed by the same etching and are etched in the same manner. It is possible to make it into a shape.

The semiconductor substrates shown in the embodiments of the present invention are not necessarily limited to those using the same, and the gist of the present invention does not change even if an insulating substrate, a conductive substrate, etc. are used.

[Brief explanation of drawings]

FIGS. 1a and 1b show examples of conventional multilayer wiring. Further, FIGS. 2a and 2b are shown for explaining the present invention. Figures 3a and 3b show an embodiment of the present invention. 1, 10, 17... semiconductor substrate, 2, 4, 6,
11, 13, 15, 18, 20...Insulating film, 3,
12, 19...first polycrystalline silicon, 5, 14
... second polycrystalline silicon, 21 ... polycrystalline silicon not containing impurities, 22 ... polycrystalline silicon into which impurities have been introduced, 7 ... aluminum, 8,
9, 16, 23...Contact hole.

Claims (1)

[Claims] 1. A step of forming a first insulating film on a substrate, a step of forming a first semiconductor wiring layer into which impurities of a first conductivity type are introduced on the first insulating film, and a step of forming a first semiconductor wiring layer on the first insulating film.
forming a second insulating film on the semiconductor wiring layer; forming a contact hole in the second insulating film; forming a semiconductor layer into which impurities are not introduced over the contact hole and the second insulating film; forming a second semiconductor wiring layer doped with a second conductivity type impurity on the semiconductor layer formed over the contact hole; etching the second semiconductor wiring layer and the semiconductor layer; 1. A method of manufacturing a semiconductor device, comprising the step of: