JPS6321997B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an associative memory circuit, and more specifically to an associative memory circuit that can store ternary signals, read the stored contents associatively using binary signals, and constitute a programmable logic array. The present invention relates to a three-state associative memory circuit that is suitable for memory cells.

A programmable logic array (hereinafter abbreviated as PLA) basically consists of two diode matrices called an AND array and an OR array, and can create any logic by selecting the arrangement of these diodes. It is a general-purpose logic integrated circuit that can realize functions. It can be said that it is a semiconductor memory device that can express logical expressions in sum-of-products form and store them in that form, and is characterized by its memory structure for efficiently storing logical expressions.

The AND array that stores product terms is an associative memory device. Moreover, the unit of storage is a ternary signal that logically represents three states, either 0 or 1 or 0 or 1, and this ternary signal is stored using two diodes. It is formed by a combination of

Generally, storage devices include fixed storage and writable storage. Commercially available PLA is of fixed memory type. In particular, in one example of what is called a field PLA, a diode matrix of an AND array or an OR array is provided with a fuse connected in series to each diode, and these fuses can be arbitrarily selected and blown. A special writing device is required to blow out the fuse, but with this, an appropriate arrangement and combination of diodes can be determined, and the desired logical formula can be permanently stored.

These fuses can be replaced with flip-flops and gate circuits that serve the same purpose, allowing the PLA to have a writable memory. Storing a ternary signal in this manner requires a combination of two diodes, as mentioned above, and therefore two flip-flops to control them. Considering that two flip-flops can typically store four states, this is a redundant and inefficient storage method for AND arrays. It can be said that there is waste in the circuit configuration.

Originally, PLA is an element with a structure suitable for integration. However, with conventional technology, it is possible to write
When PLA is configured, the circuit scale increases for the reasons mentioned above, making large-scale integration impossible.

In view of the above-mentioned circumstances, an object of the present invention is to efficiently store and associatively read out ternary signals, to configure a relatively small amount of circuitry, and to provide a three-state signal suitable for storage elements constituting PLA and the like. The purpose is to provide an associative memory circuit.

According to the present invention, there is provided a memory circuit which has three stable states and stores a ternary write input signal inputted under the control of a write control signal in correspondence with the stable state, and receives a binary logic input signal. and, depending on each of the three stable states of the memory circuit,
an associative circuit that outputs an affirmative signal of the logic input signal in a first state, a negative signal of the logic input signal in a second state, and a logic 1 signal in a third state; A three-state associative memory circuit is obtained which can store value signals and read them out associatively with binary signals.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. 1 is a memory circuit, NAND gate 11,
12..., 16. The three binary write input signals A, B, and C represent a ternary signal by their combination, and the input signal lines 101, 102, 103
The signal is supplied to NAND gates 11, 12, and 13 through. At this time, the write control signal W supplied onto the control signal line 104 is transmitted to the NAND gates 11 and 1.
Binary write input signals A, B, C via 2, 13
control input. NAND gate 14, 15,
16 input other output signals Y ₁ , Y ₂ , Y ₃ to each other to form a feedback loop, and at the same time each inputs the output signals of the corresponding NAND gates 11 , 12 , 13 . The feedback loop thus configured creates three stable states identified by the combination of output signals Y ₁ , Y ₂ , Y ₃ . That is Y ₁ , Y ₂ , Y ₃
is (1, 1, 0), (1, 0, 1) or (0, 1,
1).

Referring to FIG. 2a, the ternary signals "1", "X",
The relationship between “0”, the corresponding combination of input signals, and the internal state is shown. X indicates a good state, either 1 or 0. The input signals A, B, and C of the memory circuit 1 are limited to the combinations shown in the figure.

The operation of the memory circuit 1 is such that if the input signals A, B, and C are set to one of the above combinations and the write control signal W is set to 1, the input signals are transmitted as they are to the output signals Y ₁ , Y ₂ , and Y ₃ . It will be done. This corresponds to a stable state, and if W is set to 0 at this time, then
The values of Y ₁ , Y ₂ , and Y ₃ are retained as they are. Writing is performed in this manner.

2 is an associative circuit, with NAND gates 17, 1
Consisting of 8 and 19. A binary logic input signal is provided by an affirmative signal X ₁ on input signal line 201 and a negative signal X ₁ on input signal line 202 .
FIG. 2b shows the relationship between the input and output signals. The figure shows, for example, when (Y ₁ , Y ₂ , Y ₃ )=(1, 1, 0), if X ₁ =1, the output signal Z=1, and X ₁
When Z=0, Z=0, and this is the rule when reading "1" from a ternary signal.

According to this rule, the associative circuit 2 receives the logic input signal
X ₁ is the content of memory circuit 1 and 1 and “1” or 0
When there is a match such as “0”, the output signal Z is set to 1.
When there is a mismatch, Z is set to 0. In other words, associative reading is performed.

This rule also indicates that if the content of the storage circuit 1 is "1", Z=X ₁ , if it is "0", Z= ₁ , and if it is "X", Z=1. The ability to arbitrarily control the affirmation or negation of a logic input signal or the output signal that always becomes logic 1 means that any product term for a plurality of logic input signals can be expressed.

FIG. 3 is a circuit diagram showing another embodiment of the associative circuit 2. In FIG. 20 and 21 are OR gates. The input signals are the same as in FIG. 1, but the output signals are two output signals Z ₁ and Z ₂ of the output signal lines 203-1 and 203-2. Output signal Z ₁ is memory circuit 1
When the state of "1" is stored in the "1" state, _X1 is transmitted, and otherwise it is always set to "1". Output signal _Z2 is ₁ when the memory content is “0”,
If Z ₁ and Z ₂ are always 1, Z can be obtained by ANDing them, but when used as a memory cell in an AND array, the output signals of each memory cell will be ANDed again. Therefore, here
The AND operation is omitted and Z ₁ and Z ₂ are directly output. This allows the number of gates to be reduced.

As explained above, the three-state associative memory circuit according to the present invention is configured to store three-value signals extremely efficiently, and is particularly suitable as a basic element of a logic circuit.
This makes it suitable for storage cells in PLA AND arrays.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
Figure a shows the correspondence between the combinations of ternary signals and binary signals in the memory circuit 1, and Figure 2 b shows the associative circuit 2.
FIG. 3 is a diagram showing another embodiment of the associative circuit 2. In the same figure, 1...memory circuit, 2...associative circuit, 11,...,19
...NAND gate, 20, 21...OR gate.

Claims (1)

[Claims] 1 It has three stable states maintained by a feedback loop consisting of three gate circuits that input other output signals to each other, and is controlled by a write control signal and is input to a set of three binary signals. a memory circuit that stores a ternary write input signal represented by an associative circuit that outputs an affirmative signal of the logic input signal when it is in a state, a negative signal of the logic input signal when it is in a second state, and a logic 1 signal when it is in a third state, and outputs a ternary signal. A three-state associative memory circuit that can store and associatively read out data using binary signals.