JPS6322063B2 - - Google Patents
Info
- Publication number
- JPS6322063B2 JPS6322063B2 JP55116656A JP11665680A JPS6322063B2 JP S6322063 B2 JPS6322063 B2 JP S6322063B2 JP 55116656 A JP55116656 A JP 55116656A JP 11665680 A JP11665680 A JP 11665680A JP S6322063 B2 JPS6322063 B2 JP S6322063B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- bonding pad
- bonding
- lead wire
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
- H10W72/923—Bond pads having multiple stacked layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
- H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/981—Auxiliary members, e.g. spacers
- H10W72/983—Reinforcing structures, e.g. collars
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は半導体素子上に形成した金属配線に設
けたボンデイング用の金属電極の構成に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a metal electrode for bonding provided on a metal wiring formed on a semiconductor element.
半導体装置は一般にステム上に半導体素子をボ
ンデイングし、該素子に設けたアルミニウムから
なる金属電極(以下ボンデイングパツドという)
とステムの電極端子とを金(Au)等からなるリ
ード線で接続している。 Semiconductor devices generally have a semiconductor element bonded onto a stem, and a metal electrode (hereinafter referred to as a bonding pad) made of aluminum provided on the element.
and the electrode terminal of the stem are connected with a lead wire made of gold (Au) or the like.
上記ボンデイングパツドとリード線のリードボ
ンデイングには周知のネイルヘツド方式による金
線の熱圧着ボンデイングを用いている。この熱圧
着ボンデイングは接続部を加熱しておいてボンデ
イングパツドのアルミニウム(Al)にリード線
のAuを強く押しつけて接続する。この場合、接
続部は異種金属が共存し、しかもある程度温度が
上がると金属間化合物が生成され、この化合物は
半導体装置が稼動中にボンデイング部の表面から
下面に向かつて進行し、下地のSiO2層にまで達
する。この化合物層は脆弱なため、小さな力が加
わつただけで金線が電極から剥離するという欠点
を有している。 For the lead bonding between the bonding pad and the lead wire, thermocompression bonding of gold wire using the well-known nail head method is used. In this thermocompression bonding, the connection is made by heating the connection part and strongly pressing the Au lead wire against the aluminum (Al) bonding pad. In this case, dissimilar metals coexist in the bonding area, and when the temperature rises to a certain degree, intermetallic compounds are generated, and while the semiconductor device is in operation, these compounds progress from the surface to the bottom of the bonding area, and the underlying SiO 2 reaching the layers. Since this compound layer is brittle, it has the disadvantage that the gold wire will peel off from the electrode even if a small force is applied.
本発明は上記欠点を除去するもので、前記
SiO2上に形成したボンデイングパツド部を第1
のAl層と第2のAl層で形成し、この第1と第2
のアルミニウム層の間に金属間化合物の進行を抑
止する所定形状の抑上層を設けたことを特徴とす
るもので、この抑上層にはAlを酸化して網目状
または島状のAl2O3層を形成する。なおAl2O3の
抑止層の代りにTi、Cr、Mo等の層を形成しても
その効果を有する。 The present invention eliminates the above drawbacks and
The bonding pad formed on SiO 2 is
formed by an Al layer and a second Al layer, and the first and second
It is characterized by providing an upper layer with a predetermined shape to suppress the progress of intermetallic compounds between the aluminum layers, and this upper layer has a mesh-like or island-like Al 2 O 3 formed by oxidizing Al. form a layer. Note that forming a layer of Ti, Cr, Mo, etc. instead of the Al 2 O 3 inhibiting layer also has the same effect.
以下第1図〜第3図を用いて本発明の1実施例
である抑止層にAl2O3を形成するものについて説
明する。なお各図において同一機能部には同一符
号を付して説明する。 Hereinafter, one embodiment of the present invention in which Al 2 O 3 is formed in the inhibiting layer will be described with reference to FIGS. 1 to 3. In each figure, the same functional parts are given the same reference numerals and explained.
第1図は半導体素子のボンデイングパツド部の
断面を示したもので、1はSi基板、2はSiO2層、
3はリンガラス(PSG)、4は第1のAl層、5は
第2のAl層、6はAuリード線、7は金属間化合
物(層)、8は網状のAl2O3からなる金属間化合
物成長抑止層を示す。 Figure 1 shows a cross section of the bonding pad part of a semiconductor device, where 1 is a Si substrate, 2 is a SiO 2 layer,
3 is phosphor glass (PSG), 4 is the first Al layer, 5 is the second Al layer, 6 is the Au lead wire, 7 is the intermetallic compound (layer), and 8 is the metal made of reticulated Al 2 O 3 1 shows an interlayer compound growth inhibiting layer.
上記構成のボンデイングパツド部を製造するに
はSiO2上に素子電極(図示しない)につながる
第2図の9に示したAl配線と同時に第1のAl層
4となるAlを約1〜1.5μm厚蒸着して、これをパ
ターニングし、つぎにホトレジスト膜を半導体素
子全面に被覆後、ボンデイングパツド部20の前
記網状のAl2O3形成部のみを露光開口して、開口
部のAlを陽極酸化、プラズマ酸化、酸素イオン
注入等の方法により酸化してAl2O3よりなる抑止
層を形成する。このAl2O3層の膜厚は約5000Å程
度形成すればよい。その後前記ボンデイングパツ
ド部20のレジスト膜を除去してその上面に第2
のAl層を約1〜1.5μm蒸着し、その後PSG膜3
を形成して後Auリード線6の熱圧着ボンデイン
グを施し、半導体装置を完成するが、このような
構成の半導体装置では上記半導体素子のボンデイ
ングパツド部での熱圧着ボンデイング時又は半導
体装置の稼動中に素子が昇温して金属間化合物層
7が基板側のSiO2層2側に向かつて進行するが、
上記Al2O3層によつて、この化合物7の進行が抑
止され、ボンデイングパツド部20でのAl層と
Auリード線6材(Au)との金属間化合物がSiO2
層に達するまでの時間を長くでき、装置の寿命を
長くすることができる。 To manufacture the bonding pad section having the above structure, at the same time as the Al wiring shown in 9 of FIG. This is deposited to a thickness of μm, patterned, and then the entire surface of the semiconductor element is covered with a photoresist film. Only the network-shaped Al 2 O 3 forming portion of the bonding pad portion 20 is exposed to an opening, and the Al in the opening is exposed. A suppression layer made of Al 2 O 3 is formed by oxidation by a method such as anodic oxidation, plasma oxidation, oxygen ion implantation, or the like. The thickness of this Al 2 O 3 layer may be approximately 5000 Å. Thereafter, the resist film on the bonding pad portion 20 is removed and a second resist film is placed on the upper surface thereof.
An Al layer of approximately 1 to 1.5 μm is deposited, and then a PSG film 3 is deposited.
After that, thermocompression bonding of the Au lead wire 6 is performed to complete the semiconductor device. However, in a semiconductor device with such a configuration, there is no need for thermocompression bonding at the bonding pad portion of the semiconductor element or during operation of the semiconductor device. During the process, the temperature of the device increases and the intermetallic compound layer 7 advances toward the SiO 2 layer 2 on the substrate side.
The Al 2 O 3 layer prevents the compound 7 from progressing, and the Al layer in the bonding pad portion 20
The intermetallic compound with Au lead wire 6 material (Au) is SiO 2
The time it takes to reach the layer can be extended, and the life of the device can be extended.
第2図は第1図の上面図で9は半導体素子の電
極から導出された配線を示しており、この上面に
はPSG膜3が被覆してある。 FIG. 2 is a top view of FIG. 1, and numeral 9 indicates wiring led out from the electrodes of the semiconductor element, the upper surface of which is covered with a PSG film 3.
第3図はボンデイングパツド部20の第1の
Al層4に網目状のAl2O3層からなる抑止層8を形
成した状態を示した上面図で、10は第1のAl
層4と第2のAl層5とが接続する部分で、この
部分で電気的導通を有している。 FIG. 3 shows the first bonding pad portion 20.
This is a top view showing a state in which an inhibition layer 8 made of a mesh-like Al 2 O 3 layer is formed on the Al layer 4, and 10 is a first Al
The layer 4 and the second Al layer 5 are connected to each other, and have electrical continuity at this portion.
このAl2O3の抑止層8は絶縁物であるため、通
常のボンデイングパツドの面積が100μm×100μ
m程度の場合、この部分での接続部10の面積を
1/2〜2/3に、抑止層の面積を1/2〜1/3に形成して
電極部の電気的導通を十分取るとともに金属間化
合物が進行するのを抑止する効果を兼ねそなえた
構成としている。 Since this Al 2 O 3 suppression layer 8 is an insulator, the area of a typical bonding pad is 100 μm x 100 μm.
m, the area of the connecting part 10 in this part is reduced to 1/2 to 2/3, and the area of the suppression layer is reduced to 1/2 to 1/3 to ensure sufficient electrical continuity of the electrode part. The structure has the effect of inhibiting the progress of intermetallic compounds.
以上説明したようなボンデイングパツド部の構
成にすることによつて半導体装置の信頼性を大き
く向上することができる。 By configuring the bonding pad portion as described above, the reliability of the semiconductor device can be greatly improved.
第1図は半導体素子のボンデイングパツド部の
断面図、第2図は第1図の上面図、第3図はボン
デイングパツド部20の第1のAl層に網目状の
Al2O3からなる抑止層8を形成した状態を示す上
面図、1:Si基板、2:SiO2層、3:PSG膜、
4:第1のAl層、5:第2のAl層、6:Auリー
ド線、7:金属間化合物、8:Al2O3からなる抑
止層、9:配線、10:第1と第2のAl層の電
気的導通を取る部分、20:ボンデイングパツド
部。
FIG. 1 is a cross-sectional view of the bonding pad portion of a semiconductor element, FIG. 2 is a top view of FIG. 1, and FIG.
A top view showing a state in which a suppression layer 8 made of Al 2 O 3 is formed, 1: Si substrate, 2: SiO 2 layer, 3: PSG film,
4: First Al layer, 5: Second Al layer, 6: Au lead wire, 7: Intermetallic compound, 8: Inhibition layer made of Al 2 O 3 , 9: Wiring, 10: First and second 20: Bonding pad portion.
Claims (1)
ボンデイングする金属電極をそなえてなる半導体
装置において、該金属電極を第1のアルミニウム
層と第2のアルミニウム層で構成し、該第1およ
び第2のアルミニウム層の間に前記リード線材と
アルミニウムとの合金が成長するのを抑止する網
目形状の合金成長抑止層を形成したことを特徴と
する半導体装置。1. In a semiconductor device comprising a metal electrode for bonding a lead wire to a metal wiring portion provided in a semiconductor element, the metal electrode is composed of a first aluminum layer and a second aluminum layer, and the first and second A semiconductor device characterized in that a mesh-shaped alloy growth inhibiting layer is formed between the aluminum layers to inhibit the growth of an alloy of the lead wire and aluminum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55116656A JPS5740944A (en) | 1980-08-25 | 1980-08-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55116656A JPS5740944A (en) | 1980-08-25 | 1980-08-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5740944A JPS5740944A (en) | 1982-03-06 |
| JPS6322063B2 true JPS6322063B2 (en) | 1988-05-10 |
Family
ID=14692630
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55116656A Granted JPS5740944A (en) | 1980-08-25 | 1980-08-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5740944A (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5119968A (en) * | 1974-08-12 | 1976-02-17 | Hitachi Ltd |
-
1980
- 1980-08-25 JP JP55116656A patent/JPS5740944A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5740944A (en) | 1982-03-06 |
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