JPS6322108B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error signal processing device for evaluating data transmission quality in a data transmission system.

For example, since the quality of digital data, that is, encoded information, is ultimately evaluated by the error rate, the transmission characteristics of the digital data transmission system that transmits the digital data are also specified by the error rate. . Conventionally, in order to measure the error rate of a digital data transmission system, it is necessary to determine whether each bit of data transmitted during a predetermined measurement time is correct or incorrect, regardless of the length of the error occurrence.
By adding up the number of times these errors occur, the cumulative length of error occurrence is calculated, and the ratio of the cumulative length of error occurrence to the total number of bits of data transmitted during the measurement time, that is, the average bit error. An error rate measuring device is used to calculate the error rate.

By the way, the measurement results using the conventional error rate measuring device as described above do not allow evaluation of the transmission characteristics of a digital data transmission system with good transmission characteristics in which only relatively short random errors such as single bit errors occur. However, it is not possible to sufficiently evaluate the transmission characteristics of digital data transmission systems with poor transmission characteristics, such as magnetic recording/reproducing devices, where long errors occur relatively frequently. In other words, the conventional error rate measuring device simply measures how many bits are erroneous during a predetermined measurement period _t1 to _t0 .
For example, as shown in Figure 1, the number of error occurrences ρ ₁ (t)
The length of _each error occurrence is _to 〓 It is determined by ^t=t1 ρ ₁ (t) _to 〓 ^t=t1 ρ ₂ (t), and measurements are performed to calculate the same error rate even though the transmission characteristics are originally different.

That is, in a data transmission system such as a magnetic recording/reproduction system that is likely to include data dropouts due to damage to the magnetic tape, for example, the dropout of a data signal recorded on a magnetic tape is detected from the envelope of the data signal. In the case where _a dropout detection signal of length l ₀ as shown in FIG. 3 divided into length l ₁ , length l ₂ , length l ₃
There may be times when an error occurs, but 3
It can be said that determining that one error of length _l4 has occurred reflects the physical properties of the magnetic tape more than determining that an error of length l4 has occurred once. Note that dropout refers to a decrease in the level of a reproduced signal, and does not mean a loss of digital data obtained from the reproduced signal. In other words, even if the playback signal level decreases, the logic is "0".
binary data is obtained. However, whether or not this data is correct is another matter, and a case where the above data is incorrect is called an error.

Therefore, the present invention treats any N bits as one unit of data, and if an error occurs in even one bit among the N bits, it is determined that all of the n bits are erroneous. An object of the present invention is to provide an error signal processing device that can more accurately evaluate the occurrence of errors in a transmission system.

That is, to explain the operation of the error signal processing device according to the present invention in principle, for example, when a data signal including a dropout of length L ₀ is transmitted as shown in FIG. Regarding the data signal, the error detection signal is determined in units of N bits (3 bits in this example) using a clock signal as shown in FIG. 4B.
When an error occurs in L ₁ and L ₂ as shown in , each unit S ₁ , where the error occurs
The entirety of S ₂ , S ₃ , and S ₄ is determined as one error of length L ₃ . The error signal processing using N bits as one unit is hereinafter referred to as N-bit resolution processing.

EMBODIMENT OF THE INVENTION Hereinafter, one embodiment to which the present invention is applied will be described in detail with reference to the drawings.

FIG. 5 shows a block diagram of an embodiment in which the present invention is applied to a data transmission characteristic measuring device 10 for evaluating the transmission characteristics of the digital magnetic recording and reproducing system 1 as a data transmission system. In this embodiment, the digital magnetic recording and reproducing system 1 includes a magnetic tape 2 as a recording medium, as shown in FIG.
Recording tracks 3 formed in parallel with an inclination to
A pseudo-random signal is digitally recorded as a data signal in a tape format as shown in FIG. is supplied to. In addition, the above 7th
In the tape format shown in Figure A, preamble sections PRA are provided at the beginning and end of the data block DBL, and these preamble sections PRA
The postamble section PSA is arranged to read out data in synchronization with the recording basic clock signal ORCK as shown in FIG. 7B.
Further, a frame clock section FRA is provided adjacent to the preamble section PRA, and a frame clock signal FRCK as shown in FIG. 7C is recorded in this frame clock section FRA. Further, the data block DBL is divided, for example, into four by a block clock section BLA in which a block clock signal BLCK is recorded as shown in FIG. 7D, thereby providing four data sections DTA.
In the data section DTA, the pseudorandom signals described above are sequentially digitally recorded using the sampling clock signal SPCK as shown in FIG. 7E.

The reproduced data signal REDS obtained by reproducing the pseudorandom signal digitally recorded in the tape format as described above is sent to the error detection circuit 11 along with the frame clock signal FRCK, block clock signal BLCK, and sampling clock signal SPCK. is supplied to.

In the data transmission characteristic measuring device 10 of this embodiment, the error detection circuit 11 outputs the reference signal INRF, which is sequentially read out bit by bit from the reference memory 12 at the same speed as the clock of the reproduced data signal REDS, and the reproduced data signal REDS. data signal
It compares each bit with REDS to determine whether it is correct or not, and outputs an error detection signal ERDS. In addition,
The reference memory 12 is made of, for example, a random access memory, and has previously written therein a reality signal INRF having the same information content as the data signal digitally recorded on the magnetic tape 2. Error detection signal ERDS from the above error detection circuit 11
is supplied to the first counter circuit 13. This first counter circuit 13 adds and counts the error clock signal ERCK while the error judgment signal ERDT obtained by performing the resolution processing as shown in FIG. Find the length and get the error judgment signal ERDT
Each time the graph memory 14 is interrupted, for example, a 16-bit count output signal indicating error length data is supplied to the address input terminal of the graph memory 14 as an address signal ADRS. Note that when the output of the error determination signal ERDT is interrupted, the first counting circuit 13 performs the addition operation from "0" again, and the counting output signal is sent to the second counter circuit 15. We also supply This second counter circuit 15 calculates the cumulative error length by sequentially integrating the error occurrence length data given by the counting output, and counts one time each time the counting output signal is supplied. The total number of error occurrences is calculated by performing the addition operation.

Further, the graph memory 14 to which the count output signal from the first counter circuit 13 is supplied as the address signal ADRS receives the data at the storage location specified by the address signal every time the address signal is supplied. The signal is read out, added to the data signal by one count in one count adder 16, and written back to the original memory location. Note that this graph memory 14 is cleared from the above address signal ADRS after all data is cleared at the start of measurement.
Regarding the data signal of the storage location specified in 1
Addition is performed count by count. That is, in the graph memory 14, the number of occurrences of an error of the error occurrence length is written in a storage location designated by the error occurrence length indicated by the count output signal from the first counter circuit 13. It is becoming more and more crowded.

Next, regarding a specific circuit configuration example of the error detection circuit 11 and the first counter circuit 13,
A circuit configuration diagram thereof is shown in FIG. 8, and a time chart showing its operation is shown in FIG. 9.

In this specific example, the reproduced data signal REDS is supplied to one input terminal of the exclusive OR circuit 21 constituting the error detection circuit 11 via the first signal selector 22, and the reference signal
INRF is supplied to the other input terminal of the exclusive OR circuit 21 via the second signal selector 23,
The exclusive OR circuit 21 compares the reproduced data signal REDS and the reference signal INRF to obtain an error detection signal ERDS. The first and second signal selectors 22 and 23 each have a control signal
When error detection is performed using the reference signal INRF from the reference memory 12, the reference signal INRF and the reproduced data signal REDS are controlled by the INCT to be supplied to the exclusive OR circuit 21. It's getting old. Note that when using the external reference signal EXRF, the reproduced data signal REDS is delayed by a predetermined amount in the delay circuit 24 and then supplied to the exclusive OR circuit 21 via the first signal selector 22. It's becoming like that. Further, this error detection circuit 11 detects the first error detection circuit according to the control signal INCT.
and third and fourth signal selectors 25, 2 which are switched and controlled together with the second signal selectors 22, 23.
6 are provided, and fifth and sixth signals are switched and controlled by the control signal DGCT depending on whether the data signal transmitted by the data transmission device under test is a digital signal or an analog signal. Signal selectors 27, 28 are provided. The frame clock signal FRCK is sent to the third signal selector 2.
5 of the first counter circuit 13.
It is supplied to the set input terminal of the SR flip-flop 31. Also, the sampling clock signal
SPCK is supplied to the fifth signal selector 27 via the fourth signal selector 26, and the internal sampling signal INCK and the sampling signal SPCK are supplied via the fifth signal selector 27 to the fifth signal selector 27. The clock is supplied to each clock input terminal of the first D flip-flop 32 and the first counter 33 of the first counter circuit 13, and is supplied to the first RS flip-flop 3 through the first AND gate 34.
1 reset input terminal. Further, the sixth signal selector 28 receives the error detection signal EDRS obtained via the exclusive OR circuit 21 or the dropout detection signal of the reproduced data signal supplied when the reproduced data signal is an analog signal. ANDS is selectively supplied to the first D flip-flop 32 of the first counter circuit 13.

Here, error detection circuit 1 in this specific example
1 is obtained by comparing the reproduced data signal REDS from the above-described digital magnetic recording/reproducing device 1 as the data transmission system to be measured and the reference signal INRF from the reference memory 12 in an exclusive OR circuit 21. It is assumed that the operation is set so that the error detection signal ERDS is outputted via the sixth signal selector 28.

Next, in this specific example, the first counter circuit 13 includes a resolution block 30 that includes a first counter 33 and performs N-bit resolution processing, and a second counter 41 that measures the error occurrence length. and a calculation block 40 for calculating.

The first counter 33 of the resolution block 30 consists of a preset counter that can preset an arbitrary number N of bits in the resolution process, and the bit data signal RBDS indicating the number N of bits is shown in FIG. 9A. It is repeatedly initialized by being loaded in synchronization with the frame clock signal FRCK, and performs an N-ary counting operation with respect to the sampling clock signal SPCK shown in FIG. 9B. That is, the first counter 33 is connected to the first RS flip-flop 3 whose set input terminal is supplied with the frame clock signal FRCK from the error detection circuit 11.
₁ is supplied to its preset control terminal via the second AND gate 35, and a bit data signal RBDS indicating an arbitrary number of bits N for resolution processing is supplied to the first AND gate 35.
The negative output signal from the RS flip-flop 31 of
It is loaded by RSFQ ₁ , and a numerical value N is initialized in synchronization with each frame clock signal FRCK. Note that the counting operation period of the first counter 33 is controlled by a control signal EXCS indicating that the measurement operation is in progress. In addition, the above first
A first AND gate 34 disposed on the reset input terminal side of the RS flip-flop 31
Positive output signal RSFQ ₁ of RS flip-flop 31
gated by. This first RS flip-flop 31 enters the set operation state at timing t ₁ of the rising edge of the frame clock signal FRCK, and thereafter at timing t 1 of the first falling edge of the sampling signal SPCK supplied to the first AND gate 34 . ₂ , it enters the reset operating state and outputs a negative output signal ₁ as shown in FIG. 9C. The first counter 33 operates at a timing synchronized with the frame clock signal FRCK.
The bit gate signal RBDS is loaded every t ₂ and the numerical value N (N
=4), and by performing quaternary counting on the sampling clock signal SPCK, a borrow negation output signal as shown in FIG. 9D is output.

Note that the second AND gate 35 provided on the preset control terminal side of the first counter 33
It is gate-controlled by the borrow negation output signal from the counter 33.

The borrow NOT output signal ₁ from the first counter 33 is supplied to the data input terminal of the second D flip-flop 36, and
The clock input terminal of a third D flip-flop 38 is supplied through a NOR gate 37. The second D flip-flop 36 has its clock input terminal supplied with the sampling clock signal SPCK from the error detection circuit 11.
The borrow output signal from the first counter 33 is synchronized with the sampling clock signal SPCK.
Performs inversion operation according to the logic value of BORS ₁ . The ninth D flip-flop obtained from this second D flip-flop 37
The negative output signal ₂ as shown in Figure E is the second
The clock input terminal of the RS flip-flop 39 is supplied. The second RS flip-flop 39 consists of an RS flip-flop with a data input terminal, the set input terminal of which is supplied with the affirmative output signal DFFQ ₁ from the first D flip-flop 32, and the reset input terminal of which is supplied with the measurement output signal DFFQ1. Stop command signal indicating the stopped state of operation
STPS is supplied, and a logic "L" data signal is always supplied to the data input terminal.

Here, the first D flip-flop 32
is the error detection signal from the error detection circuit 11
For example, by using ERDS as a data signal and inverting operation synchronized with sampling clock signal SPCK,
Each period T ₁ , T ₂ , T ₃ , T ₄ as shown in FIG. 9F
It is assumed that an affirmative output signal DFFQ ₁ , which becomes logic "H", is outputted. That is, the reproduced data signal REDS reproduced by the digital magnetic recording and reproducing apparatus 1 includes the B _a bit, B _b bit, and B _c of the sampling clock signal SPCK shown in FIG. 9B.
Assume that an error has occurred in the data of each bit corresponding to bit, B _d bit, B _e bit, B _f bit, and B _g bit. Further, the second RS flip-flop 39 performs an inversion operation by the data signal of logic "L" to the second D flip-flop 3.
It has a function of performing the negative output signal ₂ from 6 as a clock signal, and gives priority to the set/reset operation by each signal supplied to the set input terminal and the reset input terminal than the inversion operation by the data signal. It has functions such as This second RS flip-flop 39
are the rising _timings t _a , t _b , t _c ,
The timing of the first rise of the negative output signal ₂ of the second D flip-flop 36 after the negative output signal ₁ falls after being triggered to the set operation state every t _d , t _a ′, t _b ′, t _c ′ Each time it is triggered to the reset operation state, it outputs a positive output signal _RSFQ2 as shown in FIG. 9G, and this positive output signal
RSFQ ₂ is applied to the data input terminal of the third D flip-flop 38. This third D flip-flop 38 uses the borrow negative output signal from the first counter 33 as a clock signal, and performs an inversion operation according to the logic value of the affirmative output signal _RSFQ2 from the second RS flip-flop 39. The error judgment output signal ERDT as shown in FIG. 9H is obtained by performing 4-bit resolution processing.
Output.

The error determination output signal ERDT obtained from the resolution block 30 treats the reproduced data signal REDS as one unit for every 4 bits, and the period T _A corresponding to the second unit S ₂ , the fourth and the fifth The period T _B corresponding to each of the th units S ₄ and S ₅ and the period corresponding to each of the 8th and 9th units
T _C becomes logic “H” and the above reproduced data signal
During REDS, there is one unit length error, two
This indicates the determination that an error of the unit length is included twice.

Resolution block 3 with this configuration
0, the error determination signal ERDT obtained from the third D flip-flop 38 is sent to the seventh signal selector 3.
9A to the operation control input terminal of the second counter 41 constituting the calculation block 40, and the borrow negative output signal from the first counter 33 is supplied to the operation control input terminal of the second counter 41 through the eighth signal selector 39B. and supplies it to the clock input terminal of the second counter 41.

Note that the seventh and eighth signal selectors 39A and 39B disposed on the output side of the resolution block 30 select signals via the seventh signal selector 38A during 1-bit resolution processing operation. The control signal ERCT outputs the affirmative output signal ₁ from the first D flip-flop 32 as the error determination signal ERDT, and outputs the sampling clock SPCK signal via the eighth signal selector 39B. Operation is controlled.

The calculation block 40 also includes a control signal.
AND gates 42 and 43, which are opened only during the measurement operation period by EXCS, are arranged on each input terminal side of the second counter 41, respectively.
The second counter 41 outputs a borrow negation output signal as a clock signal during a period in which the error determination signal ERDT supplied from the resolution block 30 to its operation control terminal is at logic "H".
After counting BORS, as shown in Figure 9,
The error occurrence length is calculated and the counted output signal is sent to the graph memory 1 mentioned above via the buffer amplifier 44.
4 as the address signal ADRS. Also,
The error determination signal ERDT and the borrow negative output signal supplied to the second counter 41 are as follows:
The signals are supplied to the second counter circuit 15 via NOR gates 45 and 46, respectively.

In the embodiments described above, the number of bits N for resolution processing is set appropriately according to the coding system of the transmitted data and the occurrence of dropout, thereby controlling the physical properties of the transmission characteristics of the data transmission system under test. can be accurately represented by an error determination signal.

As is clear from the description of the above-mentioned embodiments, according to the present invention, there is provided an error detection circuit that detects a data error every predetermined number of bits in a transmission data signal and outputs an error detection signal; The presence or absence of the error detection signal is determined for each unit of the transmission data signal in units of N bits (N is a positive integer), and all of the transmission data signals in the unit in which the error detection signal exists are determined. By having a determination circuit that outputs an error determination signal for each unit as containing an error, it is possible to eliminate burst errors from multiple random errors for data transmission systems where burst errors are likely to occur. By forming an error judgment signal that indicates a single burst error rather than treating it as a set, continuous errors that cannot accurately determine the transmission characteristics of a data transmission system can be detected by error judgment for each bit. It is also possible to obtain an error determination signal that correctly reflects the physical properties of the transmission characteristics of the data transmission system, and the intended purpose can be fully achieved.

[Brief explanation of the drawing]

Figures 1 and 2 are characteristic diagrams showing the status of error occurrence in a data transmission system. Figure 1 shows a case where the error occurrence is approximately uniform, and Figure 2 shows a case where the error occurrence is concentrated. It shows a case. FIG. 3 is a time chart showing a general error determination method in a data transmission system having transmission characteristics as shown in FIG. 2 above. FIG. 4 is a time chart for explaining the principle operation of the present invention. FIG. 5 is a block diagram showing an embodiment of a data transmission characteristic measuring device constructed by applying the present invention. FIG. 6 is a schematic diagram showing a pattern of recording tracks formed on a magnetic tape used in the digital magnetic recording/reproducing apparatus in the above embodiment. FIG. 7 is an explanatory diagram for explaining the tape format of the magnetic tape in the above embodiment. 8th
The figure is a circuit diagram showing a specific configuration of the error detection circuit and the first counter circuit in the above embodiment. FIG. 9 is a time chart for explaining the operation of the above specific example. DESCRIPTION OF SYMBOLS 1... Digital magnetic recording/reproducing device, 2... Magnetic tape, 3... Recording track, 10... Data transmission characteristic measuring device, 11... Error detection circuit, 12
...Reference memory, 13, 15... Counter circuit, 14... Graph memory, 21... Exclusive OR circuit, 30... Resolution block, 31, 39... RS flip-flop, 32,
36, 38...D flip-flop, 33, 41
...Counter, 40...Arithmetic block.

Claims (1)

[Claims] 1. An error detection circuit that detects a data error every predetermined number of bits in a transmission data signal and outputs an error detection signal; A determination circuit that determines the presence or absence of the error detection signal for each unit in the signal, and outputs an error determination signal for each unit assuming that all the transmission data signals in the unit in which the error detection signal exists include errors. An error signal processing device comprising: