JPS6019693B2 - Bit error rate measuring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bit error rate measuring device used as an index for evaluating the transmission quality of digital signals, and in particular to measuring the performance of a receiver that receives and demodulates burst signals that are often used in the field of satellite communications. The present invention relates to a bit-by-bit bit error rate measuring device for evaluating.

A digital signal is a sequence of codes that have only two states, "0" and "1", and is a sequence of codes that have only two states, "0" and "1",
It is used to transmit CM-encoded audio, image signals, etc.

In this case, one code transmits one bit of information. One of the features of signal transmission using digital signals, that is, digital communication, is that the receiver correctly demodulates each received code into "0" or "1", thereby eliminating distortion and noise received during transmission. The effect can be completely eliminated.

However, if the influence of distortion and noise in the transmission path increases, the probability of making an erroneous determination during reception demodulation increases.

Therefore, to evaluate the transmission quality of a digital signal, the ratio M/M of the number of codes demodulated erroneously during reception demodulation, M', or M bits, to the number of transmitted codes, or M bits, is calculated as "bits". This is defined as "error rate" and used.

To measure the bit error rate, a code sequence whose contents are known in advance is transmitted as a transmission signal, and the code sequence demodulated by the receiver is compared for each corresponding code. If a mismatch is detected, the code sequence is The sign is incorrect. i.e. 1
It is determined that there is a bit error. Since it is desired that the code sequence used for measurement has “1” and “0” arranged as randomly as possible, PN (PseudoN
oise) code sequences are commonly used. In digital communication using terrestrial transmission channels, digital signals are often transmitted continuously, and in this case, the bit error rate is considered to be uniform over time, so measurement is easy. However, in digital communication systems used in the field of satellite communication, signals are often transmitted intermittently.

This allows each station to share the satellite repeater in a time-division manner (in the case of TDMA), or to effectively utilize the power of the repeater, so each station transmits only when there is a signal that it truly needs to transmit. (in the case of SCPC/FDMA). Such intermittent signals are called bursts.
A receiver that handles such burst-like signals has to evaluate not only the bit error rate when receiving continuous signals as mentioned above, but also the performance in the transient state immediately after receiving the burst-like signal. It becomes a big problem.

An object of the present invention is to easily determine the transient characteristics of a receiver since it handles such burst signals. Hereinafter, this will be explained in detail using figures. FIG. 1A shows such a burst signal waveform, in which a pre-fake signal (Preamble Word) is generated before the data signal 1 to be transmitted.
It is common to attach special signals 2 and 3 called .

That is, a CR/BTR signal to facilitate carrier wave extraction and data clock phase extraction in a reception demodulator (generally a PSK demodulator), and a SYNC signal (UniqueWord) to synchronize the subsequent data signal 1.
) 3 is added. Figure 1B shows an example of how the bit error rate changes when such a burst signal is received and demodulated.The vertical axis represents the bit error rate, and the horizontal axis represents time, and the measured bit error rate is plotted. This results in a curve like 4 or 5 depending on the characteristics of the demodulator.

Of course, it is preferable that the bit error rate is small, so characteristic 4
is a more desirable characteristic, and in the case of characteristic 5, the adjustment of the demodulator is significantly deviated, indicating that the carrier wave or clock extraction characteristics are degraded. That is, the transmission quality of a burst signal or the performance of a receiver can be clearly known by measuring the temporal change in the bit error rate as shown in FIG. 1B.

However, a drawback of performing such measurements is that they require a large amount of time. The purpose of the present invention is to measure the effective temporal change characteristics of the bit error rate in a short time as described above. The adjustment time can be significantly shortened by using the method for adjusting equipment, and the maintenance at the site of use or the inspection efficiency at the manufacturing factory can be significantly improved.

Before explaining the present invention, a conventional measuring method will be explained first.

FIG. 6 is an explanatory diagram of the principle of bit error measurement. A clock generator 10 is an oscillator that generates a clock at a frequency corresponding to the actual transmission rate of digital signals, and a PN generator 2.
0 is driven by the aforementioned clock generator output, and “1”
This is a circuit that generates the aforementioned PN code sequence (hereinafter referred to as PN signal) in which the `` and 0'' signs are nearly random, and the generated PN signal is applied to the device under test instead of the actual digital signal. In the figure, the device under test is modulator 3.
0 and a demodulator 31, and the modulator output is applied to the demodulator input via a pseudo transmission path 32.

Although noise components are generally added to the pseudo transmission path 32, the actual transmission path can also be approximated by passing other non-linear circuit elements or circuit elements having frequency characteristics. The demodulator input is demodulated into a PN signal and appears at the output of the demodulator 31, which is applied to the comparator 41.

However, this signal not only contains bit loss, but also
Compared to the output of the generator 20, it is delayed in phase.
Therefore, the output of the PN generator 20 is given an appropriate delay by the delay adjustment circuit 40, and is applied as an error-free reference signal to the comparator 41 in the same phase as the demodulator output.
A code-by-symbol comparison is performed. This comparator 41
If there is a difference between the two inputs, set it to “1”; otherwise, set it to “0”.
” is output.

Therefore, by observing the presence or absence of "1" in the comparator output, it is possible to know the frequency of errors in the demodulator output. However, it is difficult to completely adjust the phase with the delay adjustment circuit 40 described above, and the amount of delay in the demodulator output may vary slightly due to the influence of environmental temperature and the like.

In this case, at the output of the comparator, a narrow panel row appears that corresponds to the phase shift between the two PN signal inputs and indicates a mismatch between them, making it difficult to measure the original bit error.
To solve this problem, generally the retiming circuit 42
and retiming the output of the comparator 41 at an appropriate phase using the clock output from the clock generator 10,
At the same time as removing the influence of the thin pulse train mentioned above, the counter 45
Create a waveform that is easy to measure. The frequency of the clock generated by the aforementioned clock generator 10, and therefore the code, ie the number M of bits, generated within a particular time is known. Therefore, by counting the output of the comparator 41 retimed by the counter 45 for a specific period of time, setting the number to M', and counting M'/M, the average bit error rate within the specific period of time can be determined. Usually, such a bit error rate is measured while changing the amount of added noise in the pseudo transmission path, and is often expressed as a characteristic of the amount of added noise versus the bit error rate.

Furthermore, since such a bit error rate largely depends on the performance of the demodulator, a standard one is often used as the modulator 30, and only the demodulator 31 is used as the object to be measured. .

Furthermore, there is a possibility that the pseudo transmission line 32 is an actual transmission line. Although the above-described method is effective when the bit error rate is uniform over time, it cannot evaluate the transient performance of a demodulator that handles burst-like signals, which is the object of the present invention.

That is, in order to achieve the object of the present invention, it is necessary to calculate the relative value of the burst signal as shown in FIG. A location must be defined and the bit error rate at that particular location measured. That is, it is necessary to perform M measurements at that particular position, count the number of errors M' among them, and calculate the ratio M/M. Second
The figure shows a block diagram of a conventional bit error rate measuring device for measuring transient characteristics of burst-like signals.

In this block diagram, the modulator 30, demodulator 31, and pseudo transmission line 32, which are the devices under test in FIG. 6, are collectively shown in one block as the device under test 300. A circuit for providing a burst-like signal and a circuit for measuring a bit error rate using the output from a device under test are shown in detail. clock generator 100
generates a clock signal 101 used in this measuring instrument and supplies the clock signal to each part. PN generator 20
0 is driven by clock 101 to generate a continuous PN signal 201. A gate signal generator 210 counts the clock 101 and generates a measurement burst signal at an appropriate cycle, and also generates burst start signals 211, 214 and gate signals 212, 213 for performing measurements at the same cycle.
occurs. Previous layer signal generator 22 Kawama timing signal 2
11, it generates a previous layer signal 221 as shown in 2 and 3 of FIG. , further passes through an OR gate 250 and becomes an input signal 251 to the device under test 300. On the other hand, the continuous PN signal 201 becomes an AND gate 24 burst-like signal 202 by the gate signal 213, and is added to the OR gate 2501 just after the previous layer signal 221 to become the input signal 251. The respective signal waveforms and temporal relationships in the above description are shown in FIGS. 3a to 3g.

Returning to FIG. 2, an input signal 251 is applied to the device under test 30.

The device to be measured is generally a PSK modulator/demodulator, but the blocks shown in the figure include a folding loop for measurement, a noise generator for simulating a propagation path, and the like. Further, depending on the case, it may be considered that the propagation path itself is included. The received and demodulated signal becomes an output signal 301 and returns to the error rate measuring device again. On the other hand, input signal 25
1 is given the same delay from the delay adjustment circuit 40 to the device under test 300' and becomes the reference signal 401. If the block illustrated as the device under test includes a propagation path whose delay time changes over time, a separate synchronization control device is required to always synchronize the delay amount of the reference signal with the output signal 301. However, since it is not directly related to the present invention, it will be omitted. These two signals 301 and 401 are connected to a comparator 4 configured by an exclusive OR circuit, for example.
10, and if there is a mismatch, a bit error signal 41 is generated.
yields 1. This signal is generally NRZ (NORETU
This is the RNTO (RO) signal. The bit error signal 411 is synchronized with respect to the clock 101 by a retiming circuit 420, and is further synchronized with the RZ signal so that it can be counted by a counter 450.
(RETURNTO RO) signal 421.

The gate signal generator 430 generates the burst start signal 21
4 as a reference, from which a gate signal 431 having a width equal to the clock cycle is generated at an arbitrary relative time position using the cycle of the clock signal 101 as a unit. The respective signal waveforms and temporal relationships in the above explanation are shown in Fig. 3 h to i.
Shown below.

Returning to FIG. 2, the bit error signal 421 is the gate signal 43
Only when the value matches 1, it is added to the counter 450 and counted.

Since the repetition period of the burst generated by the gate signal generator 210 and the width of the gate signal 431 are known, the number of repetitions of the burst-like signal in a certain period of time is M,
Let the count value of the counter 4501 be M', and M'/M
By determining , the bit error rate at the position of the gate signal 431 can be obtained.

By sequentially moving the gate signal 431 with respect to the reference timing signal 214 and repeating measurements, a bit error rate curve as shown in FIG. 1B can be obtained. One of the drawbacks of such a measurement method is that, as mentioned above, the measurement takes a lot of time.

Since bit errors usually occur randomly, that is, stochastically, the number of samples must be increased to accurately determine the bit error rate. That is, in any case, the measurement should be performed over a period such that the number of error bits M' is at least 10 bits or more. For example, if the burst repetition period is 5 msec, it takes about 10 minutes to measure that the bit error rate at a certain point is 10-4 (1 bit x 10 x 8 hsec = 50 sand =
8.3 minutes), and measuring over several tens of bits as shown in Figure 1B would take several hours or more even if the middle part was omitted, so it is not an effective method. Although it is a quality evaluation method, it is subject to significant restrictions in terms of use. The present invention has been made in order to solve the above-mentioned drawbacks of the conventional technology, and an object of the present invention is to obtain a characteristic curve as shown in FIG. 1B in the time required for one measurement. Novel bit error rate measuring instrument,
In other words, by simultaneously observing the transient response characteristics of the bit error rate of the device under test when receiving a burst signal as a function of the relative time position from the start point (or reference point) of the received burst, the measurement requirements can be determined. The object of the present invention is to provide a new bit error rate measuring device that can significantly shorten the time.

Another object of the present invention is to not only facilitate the measurement of line quality, but also to significantly shorten the adjustment time by using it for receiver adjustment, and to significantly improve maintenance at the site of use and inspection efficiency at the manufacturing factory. The object of the present invention is to provide a new bit error rate measuring device that can measure the bit error rate. In order to achieve the above object, the present invention measures the transient response characteristics regarding the bit error rate when a device under test receives a burst signal. When measuring the change in the bit error rate in the demodulated output of the device under test as a function of the temporal position expressed from a point in units of clock periods, the burst-like signal is supplied to the device under test M times, and each time the burst-like signal is A counter that counts the number of clocks is started from the starting point of the signal or a reference point that replaces the starting point, and each time a bit error is detected, the contents of the counter corresponding to the bit error are sequentially stored in a storage circuit as one data. After the supply of the burst-like signal ends, the number of times the same data, that is, the same counter contents, is stored in the memory circuit is determined M'(M'≧
0) for each counter content, and calculates the bit error rate at the temporal position indicated by the counter content based on the value of M'/M.

That is, one feature of the present invention is to record each detected bit error as a relative time position from the point at which the burst-like signal, eg, the burst start signal 214, occurs.

Another feature of the invention is to re-examine or edit the collection of records to determine the bit error rate at the required time position.

Hereinafter, preferred embodiments of the present invention will be specifically explained with reference to the drawings.

FIG. 4 shows an embodiment of a bit error rate measuring device according to the present invention.

In the present invention, the part that supplies a burst signal with a PN signal as data to the device under test and the part that detects bit errors in the demodulated output of the device under test are basically the same as those described in FIG. It is similar to a measuring instrument. Therefore, FIG. 4 shows the gate signal generator 210, comparator 410, retiming circuit 420, gate signal generator 430, AND
Only the parts corresponding to the gate 440 and the counter 450 are shown, and the latter three parts in particular are shown in a detailed logic diagram because they are the parts showing the features of the present invention. Although the diagram looks rather complicated, the distinctive circuit is that the clock signal 10 is used to indicate the relative time position within the burst signal
An n-stage binary counter 640 that counts 1; a memory 680 that records the contents of the n-stage binary counter 640 when a bit error is detected; A time position setting switch 700 for examining only data corresponding to a specific relative time position and a counter 730 for counting the number of times that data has been recorded.
It is.

The circuit of the present invention generally has three modes of operation: preparation mode, recording mode, and counting mode, which are operated manually or automatically through mode control circuit 500.

The preparation mode is a mode for clearing the contents of the memory 680,
The recording mode is a mode in which the contents of the n-stage binary counter 640 are written to the memory 680 at the time when a bit error is detected, and the counting mode is a mode in which the contents of the memory 680 that match the time position setting switch 700 are counted by the counter 73. mode.

In this way, the memory 68 is the center of operation in each operation mode.
0 is n bits x m words (n, m, 1 are positive integers, m =
Random access memory (hereinafter referred to as ``m'') with a capacity of 21)
RAM) and generally n=4, 8, 12, 16...
...1≧10 is possible. When the control signal 541 is applied to the W terminal, the n×m RAM ship 0 converts n pieces of parallel data 641 applied to the DIN terminal to the output of the address counter 660 applied to the ADD terminal, and one piece of parallel data 661. Write to the address indicated by W
When the terminal control signal 541 is not present, the contents specified by the address information 661 added to the ADD state are outputted to the DO terminal as n parallel outputs 681.

In the figure, a gate signal generator 210, a comparator 410,
The operations of the retiming circuit 420 and various signals related thereto are the same as in the conventional example shown in FIGS. 2 and 3 described above.

That is, the clock signal 101 is generated by a clock generator 100 (not shown) and is continuously supplied. Gate signal generator 210 is driven by this clock signal and periodically generates burst start signal 214. A comparator 410 detects bit errors in the demodulated output of the device under test and outputs a bit error signal 42 via a retiming circuit 420, regardless of the operating mode of the circuit of the invention.
Generates 1. Here, other main circuits shown in FIG. 4 will be explained.

The M counting circuit 5201 is reset while the control signal 501 of the mode control circuit 500 is "0", becomes active when it becomes "1", counts the burst start signal 214, and counts the M selected by the M selection switch 510. It stops after counting the value of . During this time, the gate signal 521 is set to "OM", and A
Opening ND gate 530 provides M burst start signals 531 to gate signal generator 60 . The value of M corresponds to the number of bursts to be measured, n×mRA
It is necessary to select it appropriately depending on the number of m in M680 or the expected bit error rate, but in general, 1pi, 1pi, 1bi, 1
It is desirable to choose a value such that the bit error rate is directly read later. Gate signal generator 60 river burst
A trigger signal 601 corresponding to the start signal 531 is generated and passed through an OR gate 650 to an n-stage binary counter 640.
In addition to supplying the single reset signal 651, the clock 101
is used to generate a gate signal 602 corresponding to the measurement target section to open and close AND gates 610 and 62o.

The AND gate 610 passes the clock 101 only through the measurement target section and drives the n-stage binary counter 640 as the clock signal 611.

Therefore, the contents of the n-stage binary counter 640 correspond to the relative time position within the burst signal from the starting point of the measurement target section. On the other hand, the retimed bit error signal 421 is allowed to pass through the AND gate 6201 only in the measurement target section, and passes through the OR gate 630 to signal 6.
31, and drives the address counter 660 as a clock signal.

That is, the address counter 660 receives the bit error signal 631.
will be counted. The bit error signal 631 that has passed through the OR gate 630 further passes through a delay circuit 670 and becomes the signal 6.
71, passes through AND gate 5 40 and n×mRAM
This becomes the write control signal 541 for 680. The amount of delay of the delay circuit 670 is appropriately determined depending on the delay between the clock input of the address counter 660 and the content output 661. Note that the AND gate 540 receives the control signal 503
This is prohibited during the counting mode. The address counter 660 is a one-stage binary counter, and the set signal 504 is output from the mode control circuit 500 at the beginning of each mode.
is reset to “0...0” by the signal 631.
Driven by

The counter contents are n×mRA as parallel output 661.
In addition to being added to the ADD terminal of M680, it is also added to decoder 690 as 662. If address counter 66
When 0 overflows, the decoder 690 detects it and sends the decoded output 691 back to the mode control circuit 50. In the preparation mode and counting mode, the decode output 691 indicates the completion of one operation, but in the recording mode, the position width of the M selection switch 510 or the gate signal 602 of the gate signal generator 600 is set incorrectly or This indicates the deterioration of the characteristics of the device under test, and serves as an alarm signal requesting resetting. Coincidence detection circuit 7101 is a circuit used in the counting mode, and is generally composed of n exclusive OR circuits and one AND circuit, and the contents of two sets of n parallel inputs 681 and 701 are completely When it matches, a match output 711 is generated.

In the counting mode, AND gate 550 is opened as described below, and bit error signal 421 is replaced by clock signal 10.
1 is used as signal 631 to drive the address counter. The signal 671 also becomes the clock signal 101 delayed by the delay circuit 670. The pulse width of the coincidence output 711 is determined by the clock 63 that drives the address counter 600.
Since it is an NRZ signal with a width equal to the period of 1, that is, the period of the delayed clock signal 671, the AND
Punching by signal 671 at gate 720, RZ
It is counted by a counter 730 as a signal 721. Next, the functions of each part in each operation mode will be described.

First, in the preparation mode, a reset signal 504 is generated between the mode control circuit 50 and the n-stage binary output counter 640.
, resets address counter 660 (and also counter 730) to its initial state.

Next, control signals 502 and 503 are set to "1", and AND gates 540 and 550 are opened. As a result, clock 101 passes through AND gate 550 and OR gate 30 and drives address counter 660, while writing the contents of n-stage binary counter 640 into n×m RAM 680. At this time, the n-stage binary counter 640 has been reset, and its contents 641
is "0...0", so when the clock 631 is applied until the address counter 660 overflows, the contents of the n×m RAM 680 will be cleared. When the mode control circuit 500 learns from the output 691 of the decoder 690 that clearing has been completed, it moves to the next recording mode.

In the recording mode, the mode control circuit 500 outputs the reset signal 504 again, and then sets the control signal 501 to "1".
502 is set to "0" and 503 is set to "1", and the position information in the burst signal in which the bit error occurs is determined by nx using the method described above.
Record in mRAM680.

This mode stops after observing M bursts. Completion of recording mode is completed by M counting circuit 52 light emitting diode (LED)
However, if the several modes described below are to be fully automated, it is necessary to send a completion signal back to the mode control circuit 500'. Counting mode - First, the Terama position setting switch 700 is set to a desired value, and then the mode control circuit 500 enters the counting mode.

In this case, first the reset signal 504 is generated, then the control signal 502 becomes "1", 501 and 503 become "0",
The contents of the n×m RAM 68 are output in accordance with the instructions from the address counter 660 while in the read mode, and the match detection output 711 is counted by the counter. The count value M′
Then, the bit error rate becomes M'/M. Since the one-time counting mode is stopped by the generation of decode output 691,
Set the next value on the time position setting switch 70 and repeat the above process.

The time required for the recording mode in the measurement of the present invention is the same as the time required for measuring a bit error at one position in the conventional measurement method.

The counting mode takes a negligible amount of time if done manually, so if you want to measure bit errors at P points and create a graph like the one in Figure 1B, the time required should be 1/P. become. The above explanation is for the case where everything is done manually, but the time position setting switch 700 is pressed once for each measurement mode.
It is also possible to write a graph like the one shown in Figure 1B on an , or by using a special clock only in counting mode, the output of the DA converter is used as the XY display of the afterimage cathode ray tube, and the first
It is also possible to look directly at the curve in Figure B.

Furthermore, if the data speed, that is, the frequency of the clock 101 is sufficiently low (for example, 6 cycles bps), most of the circuit shown in FIG. 4 can be replaced by a microcomputer with sufficient memory capacity.

FIG. 5 shows an embodiment using a microcomputer as another embodiment of the present invention.

The microcomputer stores the necessary programs.
CPU section (central processing unit) 800 including OM (read only memory) and RAM (random access memory) 82
The contents 641 of the n-stage binary counter 640 are loaded into the input register 81 by the bit error signal 621.
On the other hand, the bit error signal 621 causes an interrupt to the CPU section 800, excites the internal program, and inputs the input register 800.
10 is recorded in an appropriate address of the RAM 820 (the input register 81 can be omitted if there is sufficient timing). Since the burst start signal 214 is also added to the CPU section 800' as another interrupt signal, the function of the M counting circuit 620 in FIG.
0 River can be made to do this. The CPU unit 800 performs all the processing for each mode described above in response to instructions from an external mode control signal 801 (which can be considered as sense input).
In the counting mode, the counting results can be output to the output register 83. The output register 830 is not limited to n bits; for example, it is also possible to output the counting result and the corresponding time position information in parallel, and the use of the output can be considered in the same way as in the case of FIG.
In the above figures 4 and 5, the data rate or clock 101 is n×mRAM680 or CPU section 8.
00 was assumed to operate at high speeds, but in the case of high speeds of several 1 ps or more, a buffer was placed once to convert the speed, and a low-speed signal with the same burst repetition period but a longer burst length was assumed. It is necessary to use a process to convert it into

However, since the primary purpose of the present invention is to shorten the measurement time, it exhibits greater effects when the data rate or the frequency of the clock 101 is low. As detailed above, in the conventional method, bit errors were measured at a specific position of a received burst and the same process was repeated sequentially at other positions, whereas in the present invention, the entire received burst to be measured is measured at the same time. The present invention aims to shorten the time required for measurement by observing burst signals, and the present invention can be used to significantly shorten the time required for inspection, adjustment, and maintenance of equipment that handles burst-like signals, or On the contrary, an effective test,
It provides a means of adjustment and on-site maintenance, which has an extremely large effect.

Although the present invention has been described above with respect to its preferred embodiments,
These are merely illustrative, and it goes without saying that the present invention is not limited to the embodiments described here.

[Brief explanation of drawings]

FIG. 1A shows the burst signal waveform targeted by the present invention, and B
2 is a diagram showing the temporal change in bit errors during reception and demodulation of the burst signal of A, FIG. 2 is a block diagram of a related bit error rate measuring device, and FIG. FIG. 4 is a block diagram showing one embodiment of the present invention, FIG. 5 is a block diagram showing another embodiment of the present invention, and FIG. 6 is an explanatory diagram of the principle of bit error measurement. There are 100...clock generators, 200...
PN signal generator, 210, 430, 600...
Gate signal generator, 220... Previous signal generator, 300... Device under test, 400... Delay adjustment circuit, 410... Comparator, 420... Retiming Circuit, 450, 730...Counter, 500...Mode control circuit, 510...M selection switch, 5
20...M counting circuit, 640...n-stage binary counter, 660...address counter, 67
0...Delay circuit, 68 0...nxmRA
M, 6 9 0...Decoder, 7.00...Time position setting switch, 710...Coincidence detection circuit, 800...CPU section, 810...Input Register, 820...RAM, 830...Output register. Figure 6

Claims (1)

[Claims] 1. A bit error method in which the bit error rate for a burst-like digital signal is measured as a function of the relative time position defined in terms of the period of the clock signal from the start point of the burst-like signal or a reference point having a predetermined relationship with the start point. In a rate measuring instrument, means for repeatedly supplying a burst signal containing a known code sequence to a device under test, and comparing the content of the demodulated output of the device under test with the content of the supplied burst signal. means for detecting bit errors;
a first counting means for counting the clock signal period from a starting point of the burst signal or a reference point having a predetermined relationship with the starting point for each of M times (M≧1) repetitions of the burst signal; and storage means for sequentially recording the contents of the first counting means at the time when a bit error is detected as data, and furthermore, the number of times specific data has been recorded in the storage means after the recording is completed. M'(
M′≧0), and M′/
A bit error rate measuring device characterized in that M is a bit error rate at a relative time position corresponding to the specific data.