JPS6322480B2 - - Google Patents
Info
- Publication number
- JPS6322480B2 JPS6322480B2 JP56062151A JP6215181A JPS6322480B2 JP S6322480 B2 JPS6322480 B2 JP S6322480B2 JP 56062151 A JP56062151 A JP 56062151A JP 6215181 A JP6215181 A JP 6215181A JP S6322480 B2 JPS6322480 B2 JP S6322480B2
- Authority
- JP
- Japan
- Prior art keywords
- back panel
- printed board
- printed
- shelf
- tested
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Testing Electric Properties And Detecting Electric Faults (AREA)
- Mounting Of Printed Circuit Boards And The Like (AREA)
Description
【発明の詳細な説明】
本発明はシエルフに実装されたプリント板を該
シエルフに実装された状態で動作させてテストす
る方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for testing a printed board mounted on a shelf by operating it while mounted on the shelf.
第1図はシエルフに実装された状態のプリント
板を示す断面図であり、1はプリント板、2はバ
ツクパネル、3はシエルフ(シエルフのガイドレ
ール)、4はバツクパネルに植設された端子ピン
であり、バツクパネル2の両面にスルーホールの
中を貫通しているもの、11はプリント板のコネ
クタであり、上記ピン4を雄コンタクトとしてそ
れと嵌合する雌コンタクトを含んで成るものであ
る。 Figure 1 is a sectional view showing the printed board mounted on the shelf, where 1 is the printed board, 2 is the back panel, 3 is the shelf (shelf's guide rail), and 4 is the terminal pin implanted in the back panel. 11 is a printed board connector which includes a female contact which is fitted with the pin 4 as a male contact.
このような電子装置を動作させて各プリント板
1上の任意の点をプロービングし、電圧値や波形
を観測するとき、従来は第2図のようにしてい
た。即ち被テストプリント板1の代りにいわゆる
エクステンシヨンカード5をバツクパネル2に接
続し、その先のコネクタ52に対して被テストプ
リント板1を接続することにより、被テストプリ
ント板をシエルフ外部に引出した状態で装置全体
を動作させ、被テストプリント板のテストを行な
う。しかしこのような従来方法では、エクステン
シヨンカード5におけるコネクタ51と52との
間の配線長lによりデイレイを生じ、今日のよう
に高速動作する装置においては充分なテストがで
きないという問題を生じていた。 Conventionally, when such an electronic device is operated to probe any point on each printed board 1 and observe the voltage value and waveform, the procedure is as shown in FIG. That is, by connecting a so-called extension card 5 to the back panel 2 instead of the printed board 1 to be tested, and connecting the printed board 1 to the connector 52 at the end thereof, the printed board to be tested was pulled out to the outside of the shelf. The entire device is operated in this state, and the printed circuit board to be tested is tested. However, in this conventional method, a delay occurs due to the wiring length l between the connectors 51 and 52 in the extension card 5, and a problem arises in that sufficient testing cannot be performed in today's high-speed operating devices. .
そこで本発明では、一般にバツクパネル2に植
設されている端子ピン4が略表裏対称に形成され
ている(裏面側のピンはデイスクリート配線をラ
ツピングするために利用されているが、バツクパ
ネル自体の多層化がすすむにつれて、デイスクリ
ート配線の量は非常に少なくなつてきている)こ
とに注目し、バツクパネルの背面に被テストプリ
ント板を実装することを提案するものである。 Therefore, in the present invention, the terminal pins 4 that are generally installed in the back panel 2 are formed approximately symmetrically on the front and back (the pins on the back side are used for wrapping discrete wiring, but the This paper focuses on the fact that the amount of discrete wiring is becoming extremely small as the technology advances, and proposes to mount the printed circuit board under test on the back of the back panel.
但し、一般にコネクタ11は複数列のコンタク
トを有しており、単にバツクパネルの背面に挿入
したとするとコンタクト列が左右逆になつてしま
う。よつて、第3図aに示す如くアダプタコネク
タ6を介して接続することが必要である。このア
ダプタ6は第3図bに示す如く、バツクパネル側
の雌コンタクト61と被テストプリント板側の雄
コンタクト62とが左右逆になるように内部で配
線されている。 However, the connector 11 generally has multiple rows of contacts, and if it were simply inserted into the back of the back panel, the rows of contacts would be reversed left and right. Therefore, it is necessary to connect via the adapter connector 6 as shown in FIG. 3a. As shown in FIG. 3b, this adapter 6 is internally wired so that the female contacts 61 on the back panel side and the male contacts 62 on the printed board to be tested are left and right reversed.
尚上記の例ではバツクパネル2に植設されてい
る端子は表裏貫通したピン状の端子を仮定したが
これ以外の端子でもよいことはいうまでもない。 In the above example, it is assumed that the terminals implanted in the back panel 2 are pin-shaped terminals penetrating the front and back sides, but it goes without saying that other terminals may be used.
以上の如く本発明によればほとんど配線長を付
加することなく所望の被テストプリント板をシエ
ルフ外へ引き出して実装試験が可能であり、高速
な装置でも充分なテストが行なえる。 As described above, according to the present invention, it is possible to carry out a mounting test by pulling out a desired printed board to be tested outside the shelf without adding much wiring length, and sufficient testing can be performed even with a high-speed device.
第1図は一般的シエルフの断面図、第2図は従
来のエクステンシヨンカードを用いたテスト方法
を示す断面図、第3図aは本発明の一実施例テス
ト方法を示す断面図、第3図bはアダプタの断面
図である。
図中1はプリント板、2はバツクパネル、6が
アダプタである。
FIG. 1 is a sectional view of a general shelf; FIG. 2 is a sectional view showing a conventional test method using an extension card; FIG. Figure b is a sectional view of the adapter. In the figure, 1 is a printed board, 2 is a back panel, and 6 is an adapter.
Claims (1)
の片面に複数のプリント板が実装されてなる電子
装置におけるプリント板の試験方法において、 試験時には、被試験対象のプリント板をバツク
パネルの背面に端子配列を入れ換えたアダプタコ
ネクタを介して接続することにより試験を行なう
ことを特徴とするプリント板の試験方法。[Scope of Claims] 1. In a method for testing a printed board in an electronic device in which a plurality of printed boards are mounted on one side of a back panel in which terminals are arranged substantially symmetrically, the printed board to be tested is mounted on one side of the back panel. A printed circuit board testing method characterized by conducting a test by connecting to the back side of the board via an adapter connector with interchanged terminal arrangement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6215181A JPS57177600A (en) | 1981-04-24 | 1981-04-24 | Printed board testing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6215181A JPS57177600A (en) | 1981-04-24 | 1981-04-24 | Printed board testing system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57177600A JPS57177600A (en) | 1982-11-01 |
| JPS6322480B2 true JPS6322480B2 (en) | 1988-05-12 |
Family
ID=13191812
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6215181A Granted JPS57177600A (en) | 1981-04-24 | 1981-04-24 | Printed board testing system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57177600A (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5145468Y2 (en) * | 1971-11-30 | 1976-11-04 | ||
| JPS50129967A (en) * | 1974-03-30 | 1975-10-14 | ||
| JPS55141989U (en) * | 1979-03-30 | 1980-10-11 |
-
1981
- 1981-04-24 JP JP6215181A patent/JPS57177600A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57177600A (en) | 1982-11-01 |
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