JPS6322650B2 - - Google Patents

Description

Detailed Description of the Invention The present invention detects the reception interference level from the reception level terminal in order to achieve the best diversity reception, and selects an antenna with less interference such as multipath, or an antenna with less interference and a high reception level. This invention relates to a diversity receiving device suitable for use in a vehicle, configured to select the following.

Embodiments of the diversity receiving device of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 and 2 are antennas for diversity reception, and 3 is the antenna 1 and 2.
a selector switch section consisting of a semiconductor switch or the like to switch the signal to the receiver 23 and guide the signal to the receiver 23;
12 is a control terminal for switching, 4
is a tuner circuit of the receiver 23, 5 is an intermediate frequency amplification circuit, 6 is an FM detection circuit, 7 is an impulse noise control circuit for removing noise generated in an automobile ignition system, 8 is a stereo demodulation circuit, 9
1 is a power amplification circuit, and 10 is a speaker. Reference numeral 11 designates a reception level detection terminal for extracting an output corresponding to the reception level from the intermediate frequency amplification circuit 5, and reference numeral 12 designates a switching control terminal for the antenna switching switch section 3. 13 is a separation circuit connected to the terminal 11 and for separating the reception level component from the signal of the reception level detection terminal 11 and the interference component included in the signal; 14 is connected to the separation circuit 13 and detects the level of the interference component. interference level detection circuit for
16 is a drive circuit that receives information from the first comparison circuit 15 and the second comparison circuit 21 and drives the changeover switch unit 3; It is connected to the interference level detection circuit 14, and detects the reception interference level in the state before switching when antenna 1 or antenna 2 is switched via the first comparison circuit 15 and drive circuit 16 based on the disturbance level 14. 18 is a second sample switch for detecting the reception interference level immediately after switching, and 19 is the antenna reception obtained by the first sample switch 17 before switching. The first step is to store (memorize) the disturbance level.
A sample and hold circuit 20 is a second sample and hold circuit for storing the reception interference level of the antenna immediately after switching obtained by the second sample switch 18, and 21 is a second sample and hold circuit for storing the reception interference level of the antenna immediately after switching the antenna. 1 sample hold circuit 1
9 and the level of the second sample and hold circuit 20 that stores the reception interference level immediately after antenna switching. As a result, a pulse is generated and applied to the drive circuit 16 only when the level of the first sample and hold circuit 19 is lower than the level of the second sample and hold circuit 20 . Reference numeral 22 denotes a clock generation circuit for synchronizing the timing of the circuits of the above-mentioned parts to operate normally.

The signal waveform diagram of this clock generating circuit operates according to the timing shown in FIG. That is, the clock generation circuit is interlocked by the pulse h generated by the first comparison circuit 15, and a reset pulse b is given to the interference level detection circuit 14, and the first comparison is made with the pulse a which turns off the sample switch in order to store the interference level before switching the antenna. The circuit runs for a certain period of time (approximately 5 to 20 m
sec) Give a pulse i that does not activate.

Also, after switching the antenna, the signal is transmitted to the receiver 23,
After switching the antenna, a reset pulse d is sent to the second sample and hold circuit 20, taking into account the time (approximately 5 to 40 μsec) for the pulse to reach the interference level detection circuit 14 via the reception level detection terminal 11, level, and interference level separation circuit 13. A pulse c is applied to the second sample switch 18 in order to store the disturbance level. Then, in order to store the interference level until the next antenna switching operation starts with the operation of the second comparison circuit 21 (until the first comparison circuit 15 operates), the first sample and hold circuit 19 is cleared with a reset pulse e, A pulse a that turns on the first sample switch 7 is generated. 24 is a diversity control unit using an interference level detection method, and 25 is a level detection output terminal for outputting the received level from the level/interference level separation circuit 13.

Next, the operation of the diversity receiver configured as described above will be explained using the signal waveform diagrams of FIGS. 1, 2, and 3. Note that the signals a to i and a to d in Fig. 1 correspond to a to i and 3 in Fig. 2.
This corresponds to waveforms A to D in the figure.

Now, assuming that the switch section 3 is connected to the antenna 1 and reception is being performed by the antenna 1, the output of the antenna is transmitted through the tuner circuit 4, the intermediate frequency amplification circuit 5, the FM detection circuit 6, and the impulse The sound is output from a speaker 10 through a noise limiting circuit 7, a stereo demodulation circuit 8, and a power amplification circuit 9.

On the other hand, a reception interference level and a signal corresponding to the reception level are output to the terminal 11. Further, the clock generating circuit 22 is on standby in the first state with the signal waveform shown in FIG. In this state, the signal waveform of the reception level detection terminal 11 is as shown in FIG. 3A, and the reception level and reception interference level coexist. Only the interference level contained therein is extracted via the level/interference level separation circuit 13. This signal waveform is as shown in FIG. 3(b). This signal (b) is input to the disturbance level detection circuit 14, and the positive polarity peak and negative polarity peak are held (signal waveform in Fig. 3 (c)), and the positive polarity peak hold level and the negative polarity peak hold level are is subtracted to obtain the maximum peak hold level of the interfering signal level [signal waveform in Figure 3 D].

This level 2 is input to the first comparison circuit 15 in order to compare it with the reference voltage Es. First comparison circuit 15
Then, the first comparison circuit 15
The output is given to the drive circuit 16 and the clock generation circuit 22. As a result, the drive circuit 16 operates to apply a control signal to the control terminal 12 of the changeover switch section 3, and the changeover switch section 3 operates to switch the antenna 1 to the antenna 2. At the same time, the first sample switch 17 is turned off, and the interference level of the antenna 1 before switching is stored in the first sample and hold circuit.

Also, the receiver 23 starts operating with the antenna 2. (Second state in Fig. 2) At this time, the reception level of the antenna 2 is naturally also displayed on the reception level detection terminal 11.
Reception interference levels begin to appear.

However, there is a time delay of 5 .mu.sec to 20 .mu.sec before switching to the antenna 2 and the reception level and interference level of the antenna 2 appear on the reception level detection terminal 11. In order to match this time delay, the first
After receiving the signal of comparison time 15, antenna 2 after switching
In order to store the interference level in the second sample and hold circuit 20, the reset pulse with the waveform shown in FIG.
Add to. On the other hand, when switching from antenna 1 to antenna 2, the clock generation circuit 22
The signal is added to the first comparison circuit 15 for 5 to 20 msec.
The first comparator circuit 15 is made not to operate. At this point (third state in FIG. 2), the second comparison circuit 21 operates, and the antenna 1 before switching the antenna
and the interference level of antenna 2 after switching.
Then, the output is given to the clock generation circuit 22 and the drive circuit 16. The clock generation circuit 22 is the first
In order to store the interference level of the next antenna in the sample and hold circuit 19, the reset pulse shown in FIG. [Third state a in FIG. 2].

Further, when the level of the first sample and hold circuit 19 and the level of the second sample and hold circuit 20 are compared and the latter level is large, that is, the interference of the antenna 2 after switching is large, the second comparison circuit 21
gives a pulse to the drive circuit 16, and the drive circuit 16 and changeover switch section 3 operate so as to immediately return the antenna 1 to its original state [waveform f in FIG. 2]. Furthermore, if the level of the antenna 2 that was switched in the above case, that is, the second sample and hold circuit 20, is low, no pulse is applied from the second comparison circuit 21 to the drive circuit 16, and the antenna 2 remains as it is.
The process waits in the first state in FIG. 2 until the next first comparison circuit 15 operates. Then, antenna selection is performed in the same manner as described above.

In other words, this device uses the first comparison circuit to temporarily switch the antenna when the interference level of the antenna currently receiving becomes high, and if the interference level of the antenna before switching is low, it immediately switches back to the original antenna. If the interference level of the antenna that is returned or temporarily switched is low, the configuration is such that reception continues as is. Therefore, in the explanation, antenna 1
It has been explained that the interference level of antenna 1 is stored in the first sample and hold circuit 19 with reference to If so, the first sample and hold circuit 19 stores the interference level of the antenna 2. That is, the first sample-and-hold circuit 19 temporarily stores the interference level before switching the antenna by the first comparison circuit 15, and the second sample-and-hold circuit 20
temporarily stores the disturbance level after switching.

In addition, in this device, the changeover switch section 3 allows
Switching noise is generated due to antenna switching, but this is synchronized with the clock generation circuit 22, and the clock generation circuit 22 sends a noise limiting signal to the impulse noise limiting circuit 7 of the receiver 23.
In addition, noise is forcibly reduced. Further, instead of sharing the impulse noise limiting circuit, a signal complementing circuit may be separately provided between the FM detection circuit 6 and the power amplifying circuit 9 to reduce noise. Also, level detection output terminal 25
This method can be used separately from the diversity method using interference level switching to perform reception level switching diversity. According to this, it is effective to use a diversity reception method that operates by switching the interference level in a strong electric field and switches the reception level in a weak electric field. Furthermore, by using the signal from the reception level terminal 25 and interlocking it with the reference voltage Es of the first comparator circuit 15, it is possible to operate more stably from a strong electric field to a weak electric field.

FIG. 4 shows a specific embodiment of the main part of the present invention. This is the part of the control section 24 shown by the dotted line in FIG. 1, and the capacitor _C1 in the figure corresponds to the level/interference level separation circuit 13 in FIG. The operational amplifier circuits A ₁ , A ₂ , A ₃ , diodes D ₁ , D ₂ and analog switch R ₁ correspond to the disturbance level detection circuit 14 in FIG. The arithmetic amplifier circuit A ₄ , analog switch S ₇ , inverter 26, and NAND gate 27 correspond to the first comparison circuit in FIG.
NAND gate 28 and JK flip-flop 29 correspond to drive circuit 16 in FIG. The analog switch _S3 corresponds to the first sample switch 17 in FIG. Analog switch _S4 corresponds to second sample switch 18 in FIG. The operational amplifier circuit A ₅ , the diode D ₃ and the transistor R ₂ correspond to the first sample and hold circuit 19 in FIG. The operational amplification circuit A ₆ , the diode D ₄ and the transistor R ₃ correspond to the second sample and hold circuit 20 in FIG. Analog switch _S5 , _S6 ,
Arithmetic amplifier circuit A ₇ , inverter 31, and
The NAND gate 30 is the second comparator circuit 21 in FIG.
corresponds to

Clock generation circuit 22 corresponds to clock generation circuit 22 in FIG. Although the clock generation circuit is not particularly shown, it may have any configuration as long as the timing relationship shown in FIG. 2 is maintained.

A concrete sequence of the impulse noise limiting circuit 7 in FIG. 1 is shown in FIG. This is configured so that a control signal is applied from the clock pulse generation circuit 22 to the 11th pin of the IC 501 to forcibly reduce antenna switching noise.

As is clear from the above description, the present invention performs diversity reception by detecting the interference level included in the reception level from the reception level detection terminal with one receiver, and selects the antenna with the lowest interference level. It is something that is received. This makes it possible to realize a diversity receiving device that is economically advantageous and particularly effective against skip noise and multipath in in-vehicle FM radio receivers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of essential parts of an embodiment of the present invention.
Figure 2 a, b, c, d, e, f, g, h, and i are timing diagrams of the signal waveforms of each part in Figure 1, and Figure 3 A, B, C, and D are timing diagrams of each part in Figure 1. A signal waveform diagram, FIG. 4 is a specific circuit configuration diagram of a main part of an embodiment of the present invention, and FIG. 5 is a configuration diagram of an antenna switching noise reduction circuit that can be used in the present invention. 1, 2... Antenna for diversity reception,
3...Selector switch section, 11...Reception level detection terminal, 13...Level/interference level separation circuit,
14... Disturbance level detection circuit, 15... First comparison circuit, 16... Drive circuit, 17... First sample switch, 18... Second sample switch, 19
...First sample and hold circuit, 20...Second sample and hold circuit, 21...Second comparison circuit, 2
2...Clock generation circuit, 24...Control unit, 25
...Level detection output terminal.

Claims (1)

[Claims] 1. A plurality of antennas for diversity reception;
A changeover switch that selects one of these antennas; a receiver to which the antenna output is applied from the changeover switch; The diversity reception control section includes a diversity reception control section that controls a changeover switch section, and the diversity reception control section includes a drive circuit that drives the changeover switch section, and a disturbance level detection circuit that detects a disturbance level from the reception level detection terminal. and,
a first comparison circuit that compares the output of the interference level detection circuit with a reference voltage and supplies the output to the drive circuit; and a first comparison circuit that samples and holds outputs from the interference level detection circuit before antenna switching and after antenna switching. and a second sample and hold circuit, a sample switch that inputs either the output before antenna switching or the output after antenna switching from the reception interference level detection circuit, and the outputs of the first and second sample and hold circuits are compared. a second comparison circuit which supplies the output to the drive circuit; a clock pulse, a reset pulse, and a sample which operate the first and second sample switches, the first and second sample and hold circuits, and the drive circuit; 1. A diversity receiver comprising a pulse generating circuit for generating control pulses for a switch, and configured to automatically switch to an antenna with a lower interference level. 2. In the statement of claim 1, the disturbance level detection circuit includes a positive peak hold circuit that holds peaks at the positive and negative polarities of the disturbance level, a peak hold circuit that holds peaks at the negative polarity, and a peak hold circuit that holds the peaks at the negative polarity of the disturbance level. It is characterized by comprising a first reset circuit for resetting the hold, and including a disturbance level detection circuit comprising a subtraction circuit for obtaining the difference between the voltage of the positive peak hold circuit and the voltage of the negative peak hold circuit. diversity receiving device. 3. The diversity receiving device according to claim 1, wherein the reception interference level detection terminal of the receiver is also used as a reception level terminal. 4 In the description of claim 1, the first
The sample and hold circuit and the second sample and hold circuit determine the antenna switching determined by the first comparison circuit, and the second comparison circuit calculates the interference levels before and after switching from the outputs of the first and second sample and hold, respectively. A diversity receiving device characterized by a structure in which the antenna is determined, and if the interference level before switching is low, the antenna is immediately switched back. 5. In claim 1, the control unit is configured to apply a control signal to an impulse noise control circuit in the receiver or a demodulated signal complement circuit provided in the receiver to reduce switching noise when switching the antenna. Diversity receiver.