JPS632369B2 - - Google Patents
Info
- Publication number
- JPS632369B2 JPS632369B2 JP56072524A JP7252481A JPS632369B2 JP S632369 B2 JPS632369 B2 JP S632369B2 JP 56072524 A JP56072524 A JP 56072524A JP 7252481 A JP7252481 A JP 7252481A JP S632369 B2 JPS632369 B2 JP S632369B2
- Authority
- JP
- Japan
- Prior art keywords
- parallel
- bit
- circuit
- serial
- serial conversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Time-Division Multiplex Systems (AREA)
Description
【発明の詳細な説明】
本発明はデイジタル伝送、デイジタル信号処理
等に用いられる、ビツト多重された並列信号を分
離し、各並列信号を並直列変換して複数本の直列
出力信号を得る並直列変換分離回路に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention is a parallel to serial system used in digital transmission, digital signal processing, etc., which separates bit-multiplexed parallel signals and converts each parallel signal into parallel to serial to obtain a plurality of serial output signals. This invention relates to a conversion separation circuit.
従来ｌビツト並列ｍ多重された並列入力信号を
分離して並直列変換し、複数本の直列出力信号を
得る場合には、第１図に示すように各並列入力を
分離回路６１，６２，６３……，６ｌで分離し、
その出力をｌビツトの並直列変換回路７１，７
２，７３，……，７ｍで直列信号に変換する構成
が用いられる。 In order to obtain a plurality of serial output signals by separating parallel input signals that have conventionally been multiplexed in parallel with m bits and converting them from parallel to serial, each parallel input is separated by separation circuits 61, 62, 63 as shown in FIG. ..., separated by 6l,
The output is converted into l-bit parallel/serial converter circuits 71 and 7.
A configuration is used in which the signal is converted into a serial signal at 2, 73, . . . , 7 m.
しかし、この構成では入力信号の並列展開度
（並列展開されているビツト数）に等しい数（ｌ）
の分離回路と、入力信号の多重化回線数（多重化
されている回線数）に等しい数（ｍ）の並直列変
換回路が必要になるため、入力信号の並列展開
度、多重化回線数が増えると回路規模が増大する
という欠点があつた。 However, in this configuration, the number (l) is equal to the degree of parallel expansion (the number of bits expanded in parallel) of the input signal.
Separation circuit of The drawback is that increasing the number of circuits increases the circuit scale.
本発明の目的は、多重化レベルでの小規模並直
列変換の組合せにより、多重処理効果を挙げ、回
路規模の削減を計る並直列変換分離回路を提供す
ることにある。 An object of the present invention is to provide a parallel-to-serial conversion separation circuit that achieves a multiprocessing effect and reduces the circuit scale by combining small-scale parallel-to-serial conversion at a multiplexing level.
本発明の並直列変換分離回路は、ｌビツト並列
展開ｍ多重（ｌはm2の倍数、ｍは正の整数）さ
れた並列入力信号をｍ本毎に１ビツトずつ位相の
ずれた信号に変換する一時記憶装置と、前記一時
記憶装置出力をｍ本ずつ並直列変換する並直列変
換回路と、前記並直列変換回路出力から分離出力
を得る分離回路と、前記分離回路出力の位相合わ
せを行う遅延回路とを有することを特徴とする。 The parallel-to-serial conversion/separation circuit of the present invention converts parallel input signals that have been subjected to l-bit parallel expansion and m multiplexing (l is a multiple of m2 , m is a positive integer) into signals with a phase shift of 1 bit for every m signals. a parallel-to-serial conversion circuit for parallel-to-serial conversion of m temporary storage device outputs, a separation circuit for obtaining separated outputs from the outputs of the parallel-to-serial conversion circuit, and a delay for adjusting the phase of the outputs of the separation circuit. It is characterized by having a circuit.
次に本発明の実施例につき図面を参照して説明
する。第２図は本発明の実施例のブロツク図を示
している。まずｌ本のｌビツト並列ｍ多重（ｍ本
の直列信号がｌビツトに並列展開されビツト多重
されたもの）の入力はｌ／ｍ個ある（ｍ×ｍ）ビ
ツトの一時記憶装置３(1)，３(2)，３(3)，…，３
（ｍ），３（ｍ＋１），３（ｍ＋２），３（ｍ＋３），
…，３（ｌ／ｍ）に書込まれる。次に一時記憶装
置３(1)〜３（ｍ），３（ｍ＋１）〜３（2m），…，
３（ｌ／ｍ−ｍ＋１）〜３（ｌ／ｍ）のｍ個ずつ
のブロツクから１ビツトずつ位相がずれた状態で
ｍビツト並列に読出される。そして、この一時記
憶装置出力にｍビツトの並直列変換を並直列変換
回路２１，２２，２３，…，２ｍによつて施すこ
とにより、ｍビツトずつ多重化された出力がｍ本
得られる。更にｍ個の分離回路１１，１２，１
３，…，１ｍにより、位相がずれた形でｍ本の分
離された直列出力が得られる。そして最後にそれ
ぞれ（ｍ−１）ｍ，（ｍ−２）ｍ，（ｍ−３）ｍビ
ツトの遅延回路４１，４２，４３，…で位相を合
わせることにより、ｌビツトの並直列変換を受け
るとともに分離された直列出力５１，５２，５
３，…，５ｍがｍ本が得られる。ただし、この構
成はｌがm2の倍数である時に限り有効である。 Next, embodiments of the present invention will be described with reference to the drawings. FIG. 2 shows a block diagram of an embodiment of the invention. First, there are l/m (m x m) bit temporary storage devices 3 (1) that input l bit parallel m-multiplexed (m serial signals expanded in parallel to l bits and bit multiplexed). ,3(2),3(3),…,3
(m), 3(m+1), 3(m+2), 3(m+3),
..., 3 (l/m). Next, temporary storage devices 3(1) to 3(m), 3(m+1) to 3(2m),...
m bits are read out in parallel from each m block of 3(l/m-m+1) to 3(l/m) with the phase shifted by 1 bit. Then, by performing m-bit parallel-to-serial conversion on this temporary storage device output by parallel-to-serial conversion circuits 21, 22, 23, . Furthermore, m separation circuits 11, 12, 1
3, . . . , 1 m provides m separated series outputs with a phase shift. Finally, the phases are matched by (m-1)m, (m-2)m, (m-3)m-bit delay circuits 41, 42, 43, etc., respectively, to undergo l-bit parallel-to-serial conversion. Serial outputs 51, 52, 5 separated with
m pieces of 3,...,5m are obtained. However, this configuration is valid only when l is a multiple of m 2 .
具体例としてｌが27ビツトでｍが３多重の場合
について説明する。第３図はそれを実現するブロ
ツク図で、第４図はそのタイムチヤートである。
並列多重入力が並直列変換され分離された時に得
られるべきデータを〜〓〓、(1)〜(27)、〔１〕〜
〔27〕で表わす。まず、それぞれ（３×３）ビツ
トの一時記憶装置３(1)〜３(9)では第４図に示す多
重化された入力を書込み、データ〜、〜
、〜、……、〓〓〜〓〓のそれぞれ３ビツトを
１ビツトずつ位相をずらした状態（データ〜
はデータ〜より１ビツト遅れ、データ〜
はデータ〜より１ビツト遅れというように）
で読み出す。データ(1)〜(27)、〔１〕〜〔27〕に
ついても同様の動作を行う。そして３ビツトの並
直列変換回路２１〜２３の入力には一時記憶装置
３(1)〜３(9)の出力が３本ずつワイアードオアされ
た形で入り、それが並直列変換され、第４図に示
すように３ビツトずつ多重化された形で出力され
る。次に分離回路１１〜１３を通ることにより直
列データ〜〓〓、(1)〜(27)、〔１〕〜〔27〕に分
離される。そして最後に直列データ〜〓〓は６ビ
ツト遅延回路４１を、直列データ(1)〜(27)は３ビ
ツト遅延回路４２を通すことにより、位相がそろ
つた形で直列データ〜〓〓、(1)〜(27)、〔１〕〜
〔27〕を出力として取り出すことができる。 As a specific example, a case where l is 27 bits and m is 3 multiplexed will be explained. Figure 3 is a block diagram for realizing this, and Figure 4 is a time chart.
The data that should be obtained when parallel multiple inputs are parallel-serial converted and separated is ~〓〓, (1) ~ (27), [1] ~
It is expressed as [27]. First, in the temporary storage devices 3(1) to 3(9) each having (3×3) bits, the multiplexed input shown in FIG. 4 is written, and the data ~, ~
, ~, ..., 〓〓~〓〓 are shifted in phase by 1 bit (data ~
is 1 bit behind data~, data~
is one bit behind the data, etc.)
Read it with . Similar operations are performed for data (1) to (27) and [1] to [27]. Then, the outputs of the temporary storage devices 3(1) to 3(9) are input to the inputs of the 3-bit parallel-to-serial conversion circuits 21 to 23 in wired-OR form, and are parallel-serial converted to the fourth output. As shown in the figure, the data is output in a multiplexed form of 3 bits each. Next, by passing through separation circuits 11 to 13, the data is separated into serial data ~〓〓, (1) to (27), [1] to [27]. Finally, the serial data ~〓〓 is passed through a 6-bit delay circuit 41, and the serial data (1) to (27) are passed through a 3-bit delay circuit 42, so that the serial data ~〓〓, (1 )～(27), [1]～
[27] can be extracted as output.
以上述べたように本発明はｌビツト並列ｍ多重
入力を分離して並直列変換するに当つて、従来の
回路構成では分離回路ｌ個とｌビツト並直列変換
回路ｍ個を必要とする所を、ｌがm2の倍数の時
には（ｍ×ｍ）ビツト一時記憶装置ｌ／ｍ個とｍ
ビツト並直列変換回路ｍ個と分離回路ｍ個と遅延
回路（ｍ−１）個を組合せることにより実現で
き、入力信号の並列展開度、多重化回線数が大き
くなると大幅に回路規模を削減できるという効果
を有する。 As described above, the present invention eliminates the need for l separation circuits and m l-bit parallel-to-serial conversion circuits in the conventional circuit configuration when separating and parallel-to-serial conversion of l-bit parallel m multiple inputs. , when l is a multiple of m2 , there are (m×m) bit temporary storage units l/m and m
This can be realized by combining m bit parallel-to-serial conversion circuits, m separation circuits, and (m-1) delay circuits, and the circuit size can be significantly reduced as the degree of parallelization of input signals and the number of multiplexed lines increase. It has this effect.
第１図は従来のｌビツト並列ｍ多重入力を分離
して並直列変換する並直列変換分離回路のブロツ
ク図、第２図はｌビツト並列ｍ多重入力を分離し
て並直列変換する本発明の並直列変換分離回路の
実施例を示すブロツク図、第３図は27ビツト並列
３多重入力を分離して並直列変換する本発明の並
直列変換分離回路の実施例を示すブロツク図、第
４図は第３図の回路における信号の流れを示すタ
イミング図である。
１１，１２，１３，…１ｍ……分離回路、２
１，２２，２３，…２ｍ……並直列変換回路、３
(1)〜３（ｌ／ｍ）……一時記憶装置、４１〜４３
……遅延回路、５１〜５ｍ……直列出力。
Fig. 1 is a block diagram of a conventional parallel/serial conversion/separation circuit that separates l-bit parallel m multiple inputs and converts them into parallel/serial. FIG. 3 is a block diagram showing an embodiment of a parallel-to-serial conversion separation circuit. FIG. 4 is a timing diagram showing the flow of signals in the circuit of FIG. 3. FIG. 11, 12, 13,...1m... Separation circuit, 2
1, 22, 23,...2m...Parallel-serial conversion circuit, 3
(1)~3 (l/m)...Temporary storage device, 41~43
...Delay circuit, 51~5m...Series output.
Claims (1)
ｍは正の整数）された並列入力信号をｍ本毎に１
ビツトずつ位相のずれた信号に変換する一時記憶
装置と、前記一時記憶装置出力をｍ本ずつ並直列
変換する並直列変換回路と、前記並直列変換回路
出力から分離出力を得る分離回路と、前記分離回
路出力の位相合わせを行う遅延回路とを有するこ
とを特徴とする並直列変換分離回路。1 l-bit parallel expansion m multiplex (is a multiple of m 2 ,
m is a positive integer) for every m parallel input signals.
a temporary storage device that converts each bit into a phase-shifted signal; a parallel-serial conversion circuit that parallel-serializes the output of the temporary storage device m bits at a time; a separation circuit that obtains separated outputs from the output of the parallel-serial conversion circuit; 1. A parallel-to-serial conversion separation circuit, comprising: a delay circuit that adjusts the phase of separation circuit outputs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7252481A JPS57186830A (en) | 1981-05-14 | 1981-05-14 | Parallel-series converting and separating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7252481A JPS57186830A (en) | 1981-05-14 | 1981-05-14 | Parallel-series converting and separating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57186830A JPS57186830A (en) | 1982-11-17 |
| JPS632369B2 true JPS632369B2 (en) | 1988-01-19 |
Family
ID=13491800
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7252481A Granted JPS57186830A (en) | 1981-05-14 | 1981-05-14 | Parallel-series converting and separating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57186830A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61256828A (en) * | 1985-01-17 | 1986-11-14 | Oki Electric Ind Co Ltd | Serial parallel conversion circuit |
| JPS61164341A (en) * | 1985-01-17 | 1986-07-25 | Oki Electric Ind Co Ltd | Serial-parallel and parallel-serial converting system |
| JPS62128215A (en) * | 1985-11-29 | 1987-06-10 | Hitachi Ltd | Series-parallel and parallel-serial conversion circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49123540A (en) * | 1973-03-30 | 1974-11-26 |
-
1981
- 1981-05-14 JP JP7252481A patent/JPS57186830A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57186830A (en) | 1982-11-17 |
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