JPS6318908B2 - - Google Patents
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- Publication number
- JPS6318908B2 JPS6318908B2 JP7321881A JP7321881A JPS6318908B2 JP S6318908 B2 JPS6318908 B2 JP S6318908B2 JP 7321881 A JP7321881 A JP 7321881A JP 7321881 A JP7321881 A JP 7321881A JP S6318908 B2 JPS6318908 B2 JP S6318908B2
- Authority
- JP
- Japan
- Prior art keywords
- serial
- temporary storage
- storage device
- data
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/04—Distributors combined with modulators or demodulators
- H04J3/047—Distributors with transistors or integrated circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
Description
本発明はデイジタル伝送、デイジタル信号処理
等で用いられる、複数本の直列入力信号を並列展
開し、各並列展開出力をビツト多重する直並列変
換多重化回路に関するものである。
従来、複数本の直列入力信号を並列展開して多
重化する場合には、第１図に示すように直並列変
換回路１１〜１ｍで各直列信号１〜ｍを並列展開
してそれぞれの並列展開出力を多重化回路２１〜
２ｌで多重化する構成が用いられるのが普通であ
る。
しかし、この構成では多重化する直列入力数に
等しい数（ｍ）の直並列変換回路と、並列展開度
（並列展開されるビツト数）に等しい数(l)の多重
化回路が必要になるため、並列展開度が増え、多
重化する回線数が増えると回路規模が増大すると
いう欠点があつた。
本発明の目的は多重化レベルでの小規模直並列
変換の組合せにより、多重処理効果を挙げ回路規
模の削減を計る直並列変換多重化回路を提供する
ことにある。
本発明の直並列変換多重化回路は、ｍ本（ｍは
２以上の整数）の直列入力信号の位相をｍビツト
ずつずらすｍ−１個以上の遅延回路と、この遅延
回路により位相をずらされた直列入力信号を循環
的にｍビツトずつ直列に多重化するｍ個の多重化
回路と、前記多重化回路の各出力にｍビツトの直
並列変換を施すｍ個の直並列変換回路と、前記直
並列変換回路出力を入力し、すべての前記直列入
力信号のｌビツト分（ｌはm2の倍数）が入力され
るまでｍ個のアドレスのそれぞれに区分して前記
直列入力信号のそれぞれを記憶し、ｌビツト分ず
つ前記直列入力信号のそれぞれを並列に読み出す
ようにした複数の一時記憶装置とを有することを
特徴とする。
次に本発明の実施例につき図面を参照して説明
する。第２図は本発明の一般的な回路構成のブロ
ツク図を示している。まずｍ本（ｍは任意の正整
数）の直列入力１〜ｍは遅延回路３２〜３ｍによ
りｍビツトずつ位相がずれた状態になり、ｍ個の
多重化回路４１〜４ｍによりｍビツトずつ多重化
された出力ｍ本になる。次にｍ個のｍビツト直並
列変換回路５１〜５ｍにより、多重化されたｍビ
ツトが並列に展開され、ｌ／ｍ個ある（ｍ×ｍ）
ビツトの一時記憶装置６，１〜６，ｍ，６（ｍ＋
１）〜６（ｌ／ｍ）に書込まれる。そして最後に
ｌビツトの並列展開データが全て一時記憶装置に
蓄えられた時点で順次読出すことにより、多重化
されたｌビツト並列展開出力が得られる。ただ
し、この構成はｌがm2の倍数である時に限り有効
である。
具体例としてｌが27でｍが３の場合について説
明する。第３図はそれを実現するブロツク図で第
４図はそのタイムチヤートである。直列入力１〜
３の並列展開されるべきデータを〜〓〓，(1)〜(2
７），〔１〕〜〔27〕で表わす。多重化回路４２，
４３の入力では直列入力２，３はそれぞれ３ビツ
ト、６ビツトの遅延を受けており、多重化回路４
１〜４３の入力は３ビツトずつ位相がずれた形に
なつている。そして多重化回路４１〜４３の出力
では第４図に示すように直列入力１〜３が３ビツ
トずつ多重化された形になる。さらに３ビツトの
直並列変換回路５１〜５３により１ビツトずつ多
重化された信号として取り出すことができ、それ
が（３×３）ビツトの一時記憶装置６(1)〜６(9)に
書込まれる。一時記憶装置６(1)〜６(9)への書込み
は、一時記憶装置６(1)へはデータ〜，(1)〜
(3)，〔１〕〜〔３〕を、一時記憶装置６(2)へはデ
ータ〜，(4)〜(6)，〔４〕〜〔６〕をというよ
うに順次書込まれ、一時記憶装置６(9)へはデータ
〓〓〜〓〓，(25)〜(27)，〔25〕〜〔27〕が書込まれ
る。最後に読出しは一時記憶装置６(1)〜６(9)へデ
ータ〜〓〓が書込まれた時点でデータ〜〓〓を並
列出力として読出し、データ〜〓〓，〔１〕〜
〔27〕についても順次同じ動作を繰返す。第４図
で矢印５はすべて書き込み位置を示し、矢印６は
すべて読出し位置を示す。
一時記憶装置６(1)(4)(7)の書き込み動作を説明す
ると、１番目の書き込みパルスで一時記憶装置６
(1)のアドレス０にデータを書き込む。２番
目の書き込みパルスで一時記憶装置６(1)のアドレ
ス１にデータ(1)(2)(3)を書き込む。３番目の書き込
みパルスで一時記憶装置６(1)のアドレス２にデー
タ〔１〕〔２〕〔３〕を書き込む。４番目の書き込
みパルスで一時記憶装置６(4)のアドレス０にデー
タを書き込む。５番目の書き込みパルスで
一時記憶装置６(4)のアドレス１にデータ(10)(11)(12)
を
書き込む。６番目の書き込みパルスで一時記憶装
置６(4)のアドレス２にデータ〔10〕〔11〕〔12〕を
書き込む。７番目の書き込みパルスで一時記憶装
置６(7)のアドレス０にデータを書き込む。
８番目の書き込みパルスで一時記憶装置６(7)のア
ドレス１にデータ(19)(20)(21)を書き込む。９番目
の書き込みパルスで一時記憶装置６(7)のアドレス
２にデータ〔19〕〔20〕〔21〕を書き込む。
一時記憶装置６(2)(5)(8)の書き込み動作を説明す
ると、１番目の書き込みパルスで一時記憶装置６
(2)のアドレス０にデータを書き込む。２番
目の書き込みパルスで一時記憶装置６(2)のアドレ
ス１にデータ(4)(5)(6)を書き込む。３番目の書き込
みパルスで一時記憶装置６(2)のアドレス２にデー
タ〔４〕〔５〕〔６〕を書き込む。４番目の書き込
みパルスで一時記憶装置６(5)のアドレス０にデー
タを書き込む。５番目の書き込みパルスで
一時記憶装置６(5)のアドレス１にデータ(13)(14)(15)
を
書き込む。６番目の書き込みパルスで一時記憶装
置６(5)のアドレス２にデータ〔１−４−３〕〔14〕
〔15〕を書き込む。７番目の書き込みパルスで一
時記憶装置６(8)のアドレス０にデータ〓〓を書
き込む。８番目の書き込みパルスで一時記憶装置
６(8)のアドレス１にデータ〓〓を書き込む。９
番目の書き込みパルスで一時記憶装置６(8)のアド
レス２にデータ〔22〕〔23〕〔24〕を書き込む。
一時記憶装置６(3)(6)(9)の書き込み動作を説明す
ると、１番目の書き込みパルスで一時記憶装置６
(3)のアドレス０にデータを書き込む。２番
目の書き込みパルスで一時記憶装置６(3)のアドレ
ス１にデータ(7)(8)(9)を書き込む。３番目の書き込
みパルスで一時記憶装置６(3)のアドレス２にデー
タ〔７〕〔８〕
The present invention relates to a serial-to-parallel conversion multiplexing circuit used in digital transmission, digital signal processing, etc., which expands a plurality of serial input signals in parallel and multiplexes each parallel expanded output into bits. Conventionally, when multiplexing multiple serial input signals by expanding them in parallel, each serial signal 1 to m is expanded in parallel by serial-parallel conversion circuits 11 to 1m as shown in FIG. Output multiplexing circuit 21~
A 2l multiplexing configuration is normally used. However, this configuration requires a number (m) of serial-to-parallel conversion circuits equal to the number of serial inputs to be multiplexed, and a number (l) of multiplexing circuits equal to the degree of parallel expansion (number of bits expanded in parallel). However, as the degree of parallelization increases and the number of multiplexed lines increases, the circuit size increases. An object of the present invention is to provide a serial-to-parallel conversion multiplexing circuit that achieves a multiprocessing effect and reduces the circuit scale by combining small-scale serial-to-parallel conversion at the multiplexing level. The serial-to-parallel conversion multiplexing circuit of the present invention includes m-1 or more delay circuits that shift the phase of m (m is an integer of 2 or more) serial input signals by m bits, and a phase shift circuit of the present invention. m multiplexing circuits for cyclically serially multiplexing serial input signals of m bits each; m serial-parallel conversion circuits for performing m-bit serial-parallel conversion on each output of the multiplexing circuit; Input the output of the serial/parallel conversion circuit, and store each of the serial input signals by dividing them into m addresses until l bits (l is a multiple of m2 ) of all the serial input signals are input. and a plurality of temporary storage devices configured to read each of the serial input signals in parallel in units of l bits. Next, embodiments of the present invention will be described with reference to the drawings. FIG. 2 shows a block diagram of the general circuit configuration of the present invention. First, m serial inputs 1 to m (m is any positive integer) are shifted in phase by m bits by delay circuits 32 to 3m, and are multiplexed by m bits by m multiplexing circuits 41 to 4m. The resulting output will be m. Next, the multiplexed m bits are expanded in parallel by m pieces of m bit serial/parallel conversion circuits 51 to 5m, and there are l/m pieces (m×m).
Bit temporary storage device 6, 1 to 6, m, 6 (m+
1) to 6 (l/m). Finally, when all the 1-bit parallel expansion data is stored in the temporary storage device, the multiplexed 1-bit parallel expansion output is obtained by sequentially reading out the data. However, this configuration is valid only when l is a multiple of m 2 . As a specific example, a case where l is 27 and m is 3 will be explained. Figure 3 is a block diagram to realize this, and Figure 4 is a time chart. Series input 1~
3 data to be expanded in parallel ~〓〓, (1) ~ (2
7), expressed as [1] to [27]. multiplexing circuit 42,
43, serial inputs 2 and 3 are delayed by 3 bits and 6 bits, respectively, and multiplexer circuit 4
The inputs 1 to 43 are shifted in phase by 3 bits. As shown in FIG. 4, the outputs of the multiplexing circuits 41-43 are in the form of multiplexed serial inputs 1-3 of 3 bits each. Furthermore, it can be extracted as a multiplexed signal bit by bit by the 3-bit serial/parallel converter circuits 51 to 53, and then written to the (3×3) bit temporary storage devices 6(1) to 6(9). It can be done. Writing to temporary storage devices 6(1) to 6(9) is as follows: data to temporary storage device 6(1), (1) to
(3), [1] to [3] are sequentially written to the temporary storage device 6 (2) as data ~, (4) to (6), [4] to [6], and temporarily Data 〓〓~〓〓, (25)~(27), [25]~[27] are written into the storage device 6(9). Finally, when the data~〓〓 is written to the temporary storage devices 6(1) to 6(9), the data~〓〓 is read out as parallel output, and the data~〓〓, [1]~
Repeat the same operation for [27] in sequence. In FIG. 4, all arrows 5 indicate write positions, and all arrows 6 indicate read positions. To explain the write operation of the temporary storage device 6(1)(4)(7), the first write pulse causes the temporary storage device 6 to write.
Write data to address 0 in (1). The second write pulse writes data (1), (2), and (3) to address 1 of the temporary storage device 6(1). Data [1][2][3] are written to address 2 of temporary storage device 6(1) with the third write pulse. The fourth write pulse writes data to address 0 of the temporary storage device 6(4). At the fifth write pulse, data (10)(11)(12) is written to address 1 of temporary storage device 6(4).
Write. Data [10], [11], and [12] are written to address 2 of temporary storage device 6(4) with the sixth write pulse. Data is written to address 0 of the temporary storage device 6(7) with the seventh write pulse.
Data (19), (20), and (21) are written to address 1 of the temporary storage device 6 (7) with the 8th write pulse. Data [19], [20], and [21] are written to address 2 of temporary storage device 6(7) with the ninth write pulse. To explain the write operation of the temporary storage device 6(2)(5)(8), the first write pulse causes the temporary storage device 6 to write.
Write data to address 0 in (2). The second write pulse writes data (4), (5), and (6) to address 1 of the temporary storage device 6(2). With the third write pulse, data [4], [5], and [6] are written to address 2 of the temporary storage device 6(2). Data is written to address 0 of the temporary storage device 6(5) with the fourth write pulse. At the fifth write pulse, data (13)(14)(15) is written to address 1 of temporary storage device 6(5).
Write. At the 6th write pulse, data [1-4-3] [14] is written to address 2 of temporary storage device 6(5).
Write [15]. The seventh write pulse writes data 〓〓 to address 0 of the temporary storage device 6(8). Data 〓〓 is written to address 1 of the temporary storage device 6(8) with the 8th write pulse. 9
Data [22], [23], and [24] are written to address 2 of the temporary storage device 6(8) with the th write pulse. To explain the write operation of the temporary storage device 6(3)(6)(9), the first write pulse causes the temporary storage device 6 to write.
Write data to address 0 in (3). With the second write pulse, data (7), (8), and (9) are written to address 1 of the temporary storage device 6 (3). At the third write pulse, data [7] [8] is written to address 2 of temporary storage device 6(3).
〔９〕を書き込む。４番目の書き込
みパルスで一時記憶装置６(6)のアドレス０にデー
タを書き込む。５番目の書き込みパルスで
一時記憶装置６(6)のアドレス１にデータ(16)(17)(18)
を
書き込む。６番目の書き込みパルスで一時記憶装
置６(6)のアドレス２にデータ〔16〕〔17〕〔18〕を
書き込む。７番目の書き込みパルスで一時記憶装
置６(9)のアドレス０にデータ〓〓〓〓〓〓を書き込む
。
８番目の書き込みパルスで一時記憶装置６(9)のア
ドレス１にデータ(25)(26)(27)を書き込む。９番目
の書き込みパルスで一時記憶装置６(9)のアドレス
２にデータ〔25〕〔26〕〔27〕を書き込む。
このようにして書き込んだ時点では、一時記憶
装置６(1)乃至６(9)の記憶内容は、第５図に示すよ
うになるから、つぎに、１番目の読み出しパルス
でアドレス０を読み出すと、データ乃至〓〓が並
列に読み出される。２番目の読み出しパルスでア
ドレス１を読み出すと、データ(1)乃至(27)が並列
に読み出される。３番目の読み出しパルスでアド
レス２を読み出すと、データ〔１〕乃至〔27〕が
並列に読み出される。これにより直列入力１〜３
の27ビツト並列展開された出力が多重化された形
で取り出せる。
以上述べた様に本発明はｌビツトの直並列変換
とｍ多重のビツト多重を行うに当つて、従来の回
路構成ではｌビツト直並列変換回路ｍ個と多重化
回路ｌ個を必要とする所を、ｌがm2の倍数の時に
は遅延回路（ｍ−１）個（ｍ個でも実施できる）
と多重化回路ｍ個とｍビツト直並列変換回路ｍ個
と（ｍ×ｍ）ビツト一時記憶装置ｌ／ｍ個を組合せ
ることにより実現でき、多重化する回線数、並列
展開度が大きくなると大幅に回路規模を削減でき
るという効果を有する。Write [9]. Data is written to address 0 of the temporary storage device 6(6) with the fourth write pulse. At the fifth write pulse, data (16)(17)(18) is written to address 1 of temporary storage device 6(6).
Write. Data [16], [17], and [18] are written to address 2 of temporary storage device 6(6) with the sixth write pulse. With the seventh write pulse, data 〓〓〓〓〓〓 is written to address 0 of the temporary storage device 6(9).
Data (25), (26), and (27) are written to address 1 of temporary storage device 6 (9) with the 8th write pulse. Data [25], [26], and [27] are written to address 2 of the temporary storage device 6(9) with the ninth write pulse. At the time of writing in this way, the memory contents of the temporary storage devices 6(1) to 6(9) are as shown in FIG. 5, so when address 0 is read with the first read pulse, , data to 〓〓 are read out in parallel. When address 1 is read with the second read pulse, data (1) to (27) are read in parallel. When address 2 is read with the third read pulse, data [1] to [27] are read in parallel. This allows series inputs 1 to 3
The 27-bit parallel expanded output can be extracted in multiplexed form. As described above, the present invention can perform l-bit serial-to-parallel conversion and m-bit multiplexing, whereas the conventional circuit configuration requires m l-bit serial-to-parallel conversion circuits and l multiplexing circuits. , when l is a multiple of m 2 , delay circuits (m-1) (can be implemented with m)
This can be realized by combining m multiplexing circuits, m m-bit serial/parallel converter circuits, and l/m (m×m) bit temporary storage devices, and the number of multiplexed lines and the degree of parallelization increase significantly. This has the effect of reducing the circuit scale.
第１図は従来のｌビツト並列展開とｎ多重を行
う直並列変換多重化回路のブロツク図、第２図は
本発明のｌビツト並列展開とｎ多重を行う直並列
変換多重化回路の実施例のブロツク図、第３図は
27ビツト並列展開と３多重を行う直並列変換多重
化回路の実施例のブロツク図、第４図は第３図の
回路における信号の流れを示すタイムチヤート、
第５図は第３図中の一時記憶装置の記憶内容の説
明図である。
５１〜５ｍ……直並列変換回路、４１〜４ｍ…
…多重化回路、３２〜３ｍ……遅延回路、６(1)〜
６（ｌ／ｍ）……一時記憶装置、５……一時記憶
装置への書き込み位置、６……一時記憶装置から
の読出し位置。
Figure 1 is a block diagram of a conventional serial-to-parallel conversion multiplexing circuit that performs l-bit parallel expansion and n-multiplexing, and Figure 2 is an embodiment of the serial-parallel conversion multiplexing circuit that performs l-bit parallel expansion and n-multiplexing according to the present invention. The block diagram, Figure 3 is
A block diagram of an embodiment of a serial-to-parallel conversion multiplexing circuit that performs 27-bit parallel expansion and 3-multiplexing. Figure 4 is a time chart showing the signal flow in the circuit of Figure 3.
FIG. 5 is an explanatory diagram of the storage contents of the temporary storage device in FIG. 3. 51~5m...Serial parallel conversion circuit, 41~4m...
...Multiplex circuit, 32~3m...Delay circuit, 6(1)~
6 (l/m)...Temporary storage device, 5...Position for writing to the temporary storage device, 6...Position for reading from the temporary storage device.
Claims (1)
位相をｍビツトずつずらすｍ−１個以上の遅延回
路と、この遅延回路により位相をずらされた直列
入力信号を循環的にｍビツトずつ直列に多重化す
るｍ個の多重化回路と、前記多重化回路の各出力
にｍビツトの直並列変換を施すｍ個の直並列変換
回路と、前記直並列変換回路出力を入力し、すべ
ての前記直列入力信号のｌビツト分（ｌはm2の倍
数）が入力されるまでｍ個のアドレスのそれぞれ
に区分して前記直列入力信号のそれぞれを記憶
し、ｌビツト分ずつ前記直列入力信号のそれぞれ
を並列に読み出すようにした複数の一時記憶装置
とを有することを特徴とする直並列変換多重化回
路。1 m-1 or more delay circuits that shift the phase of m (m is an integer of 2 or more) serial input signals by m bits, and cyclically shift the serial input signal whose phase has been shifted by the delay circuits by m bits. m multiplexing circuits that serially multiplex each output, m serial-to-parallel converting circuits that perform m-bit serial-to-parallel conversion on each output of the multiplexing circuit, and the outputs of the serial-to-parallel converting circuits. Each of the serial input signals is divided into m addresses and stored until l bits (l is a multiple of m 2 ) of the serial input signal are input, and the serial input signal is stored in units of l bits. 1. A serial-to-parallel conversion multiplexing circuit comprising: a plurality of temporary storage devices configured to read out each of the above in parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7321881A JPS57188153A (en) | 1981-05-15 | 1981-05-15 | Serial parallel conversion multiplex circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7321881A JPS57188153A (en) | 1981-05-15 | 1981-05-15 | Serial parallel conversion multiplex circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57188153A JPS57188153A (en) | 1982-11-19 |
| JPS6318908B2 true JPS6318908B2 (en) | 1988-04-20 |
Family
ID=13511796
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7321881A Granted JPS57188153A (en) | 1981-05-15 | 1981-05-15 | Serial parallel conversion multiplex circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57188153A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61256828A (en) * | 1985-01-17 | 1986-11-14 | Oki Electric Ind Co Ltd | Serial parallel conversion circuit |
| JPS61164341A (en) * | 1985-01-17 | 1986-07-25 | Oki Electric Ind Co Ltd | Serial-parallel and parallel-serial converting system |
| JPS62128215A (en) * | 1985-11-29 | 1987-06-10 | Hitachi Ltd | Series-parallel and parallel-serial conversion circuit |
| JP3099955B2 (en) * | 1989-10-13 | 2000-10-16 | 株式会社東芝 | Multiplexer |
| JPH04100429A (en) * | 1990-08-20 | 1992-04-02 | Toshiba Corp | Time division multiplexer |
-
1981
- 1981-05-15 JP JP7321881A patent/JPS57188153A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57188153A (en) | 1982-11-19 |
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