JPS632519B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention stores video signals for one horizontal scanning period, uses the next horizontal scanning period to appropriately divide the entire stored content or the horizontal scanning period, and stores the stored content in the same manner. This invention relates to a television receiver that sequentially outputs the divided storage contents in accordance with the divided horizontal scanning periods.

This method uses a flat screen display tube, liquid crystal, or EL that sequentially scans one horizontal scanning line in the vertical direction.
It is most suitable for television receivers that use flat display elements such as panels, LED panels, and plasma panels.

Conventionally, cathode ray tubes have been mainly used as display elements for displaying color television images, but conventional cathode ray tubes have a very long depth compared to the screen size, making it difficult to create thin television receivers. It was impossible. In addition, EL display elements, plasma display devices, liquid crystal display elements, etc. have recently been developed as flat display elements.
All of them are insufficient in terms of performance such as brightness, contrast, and color reproducibility of color display, and have not been put into practical use.

Therefore, the aim was to achieve a device that could display color television images on a flat display device using electron beams, and the screen was divided vertically into multiple sections. Each section generates an electron beam, deflects each electron beam in the vertical direction to display multiple lines, and further divides it into multiple sections horizontally to display R, G, B, etc. phosphors are made to emit light in sequence, and the amount of electron beam irradiation to the R, G, B, etc. phosphors is controlled by a color video signal, and the television image as a whole is displayed. Something to display was devised.

First, a basic configuration example of the image display element used here will be explained with reference to FIG.

This display element is arranged in order from the back to the front.
Back electrode 1, line cathode 2 as an electron beam source, vertical focusing electrodes 3, 3', vertical deflection electrode 4, electron beam flow control electrode 5, horizontal focusing electrode 6, horizontal deflection electrode 7, electron beam accelerating electrode 8 and screen. Board 9
These are housed in the evacuated interior of a flat glass bulb (not shown). Line cathode 2 as electron beam source
is stretched in the horizontal direction so as to generate an electron beam distributed linearly in the horizontal direction, and a plurality of such linear cathodes 2 are arranged vertically at appropriate intervals (here, 2 A to 2 D). (Only books shown) provided. In this embodiment, it is assumed that 15 pieces are provided. Let's say 2i~2yo. These wire cathodes 2 are constructed by applying an oxide cathode material to the surface of a tungsten wire having a diameter of 10 to 20 μΦ, for example. Then, as will be described later, the electron beams are controlled to be emitted sequentially from the upper line cathode 2a for a fixed period of time. The back electrode 1 creates a potential gradient with a vertical focusing electrode 3, which will be described later, and prevents the generation of electron beams from other line cathodes 2 other than the line cathode 2 which is controlled to emit electron beams for a certain period of time. It has the function of suppressing the electron beam and pushing the generated electron beam forward only. The back electrode 1 may be formed by a coating of a conductive material applied to the inner surface of the rear wall of the glass bulb. Further, instead of the back electrode 1 and the linear cathode 2, a planar electron beam emitting cathode may be used.

The vertical focusing electrode 3 is a conductive plate 11 having a horizontally long slit 10 facing each of the line cathodes 2I to 2Y, and extracts the electron beam emitted from the line cathode 2 through the slit 10, and focus in a direction. The slit 10 may be provided with crosspieces at appropriate intervals in the middle, or may be substantially formed as a slit by an example of a large number of through holes arranged side by side at small intervals (almost touching each other) in the horizontal direction. may have been done. The vertical focusing electrode 3' is also similar.

A plurality of vertical deflection electrodes 4 are arranged horizontally in the middle of each of the slits 10, and are each composed of conductors 13 and 13' provided on the upper and lower surfaces of an insulating substrate 12. has been done. And the opposing conductors 13, 13'
A vertical deflection voltage is applied between them to deflect the electron beam in the vertical direction. In this configuration example, the pair of conductors 13, 23' deflects the electron beam from one line cathode 2 to positions corresponding to 16 lines in the vertical direction. And, by 16 vertical deflection electrodes 4, 15
Fifteen conductor pairs corresponding to each of the book line cathodes 2 are constructed, and the electron beam is ultimately deflected to draw 240 horizontal lines on the screen 9.

Next, the control electrodes 5 are composed of conductive plates 15 each having a vertically long slit 14, and a plurality of control electrodes 15 are arranged in parallel in the horizontal direction at predetermined intervals. In this configuration example, 320 control electrode conductive plates 15a to 15n are provided (only 10 are shown in the figure). Each of the control electrodes 5 separates and extracts the electron beam into one picture element in the horizontal direction, and controls the amount of electron beam passing therethrough in accordance with a video signal for displaying each picture element. Therefore, if 320 control electrodes 5 are provided, 320 picture elements can be displayed per horizontal line. Also,
In order to display images in color, each picture element must be R.
Display is performed using phosphors of three colors, G and B, and R, G, and B video signals are sequentially applied to each control electrode 5. In addition, 320 sets of video signals for one line are simultaneously applied to the 320 control electrodes 5.
Video for each line is displayed at once.

The horizontal focusing electrode 6 is composed of a conductive plate 17 having a plurality of vertically long slits 16 (320 slits 16) opposite to the slits 14 of the control electrode 5. Each beam is focused horizontally into a narrow electron beam.

The horizontal deflection electrode 7 is composed of a plurality of conductive plates 18 arranged vertically in the middle of each of the slits 16, and a horizontal deflection voltage is applied between each conductive plate 18 for each picture element. The electron beams are respectively deflected in the horizontal direction, and the R, G, and B phosphors are sequentially irradiated on the screen 9 to cause them to emit light. In this embodiment, the deflection range is the width of one picture element for each electron beam.

The accelerating electrode 8 is composed of a plurality of conductive plates 19 provided horizontally at the same position as the vertical deflection electrode 4, and accelerates the electron beam so that it collides with the screen 9 with sufficient energy.

The screen 9 is constructed by coating the back surface of a glass plate 21 with a phosphor 20 that emits light when irradiated with an electron beam, and adding a metal back layer (not shown). The phosphor 20 is arranged for each slit 14 of the control electrode 5, that is, for each horizontally divided electron beam.
There are pairs of phosphors in each of the three colors R, G, and B, and they are applied in stripes in the vertical direction. In FIG. 1, the broken lines drawn on the screen 9 indicate divisions in the vertical direction that are displayed corresponding to each of the plurality of line cathodes 2, and the two-dot chain lines correspond to each of the plurality of control electrodes 5. Indicates the horizontal division displayed. As shown in the enlarged view in Fig. 2, one section partitioned by these two has R, G, and B phosphors 20 for one pixel in the horizontal direction, and 16 lines in the vertical direction. It has a width of
For example, the size of one section is 1 in the horizontal direction.
mm, and the vertical direction is 16 mm.

Note that in FIG. 1, the length in the horizontal direction is greatly enlarged relative to the length in the vertical direction for clarity.

Further, in this embodiment, only one pair of R, G, and B phosphors 20 for one picture element is provided for one control electrode 5, that is, one electron beam, but two
Of course, two or more pairs for more than two picture elements may be provided, and in that case, R, G, and B video signals for two or more picture elements are sequentially applied to the control electrode 5.
Horizontal deflection is performed in synchronization with this.

Next, the basic configuration of a drive circuit for displaying television images on this display element will be explained with reference to FIG. First, a driving portion for irradiating the screen 9 with an electron beam to cause the phosphor to emit light and generate a raster will be described.

The power supply circuit 22 is a circuit for applying a predetermined bias voltage (operating voltage) to each electrode of the display element,
-V ₁ to the back electrode 1, and -V 1 to the vertical focusing electrodes 3 and 3'.
DC voltages of V ₃ , V ₃ ', V ₆ to the horizontal focusing electrode 6, V ₈ to the accelerating electrode 8, and V ₉ to the screen 9 are applied.

Next, a composite video signal of a television signal is applied to the input terminal 23, and a synchronization separation circuit 24 separates and extracts a vertical synchronization signal V and a horizontal synchronization signal H. The vertical drive pulse generation circuit 25 is composed of a counter that is reset by a vertical retrace pulse and counts horizontal pulses, and the vertical retrace pulse generation circuit 25 is configured with a counter that is reset by a vertical retrace pulse and counts horizontal pulses, and the vertical retrace pulse generation circuit 25 is configured to operate during an effective vertical scanning period (here, 240H) excluding the vertical retrace period of the vertical period. 15 drive pulses each having a length of 16H are generated sequentially during each period of 16H. These drive pulses I, B...Y are applied to the line cathode drive circuit 26, where they are inverted so that they are at a low potential only during each pulse period and approximately
The line cathode drive pulses made at a high potential of 20 volts are converted into line cathode drive pulses 2', 2', 2', 2', 2', 2', 2', 2', 2', 2', 2', 2', 2', 2', 2', 2', 2', 2', 2', 2', 2', 2', 2', 2', 3', 4', 4', 4', 4', 4', 4', 4', 4', 4', 4', 4', 4', and 4'.
...Added to 2yo. A current is passed through each of the line cathodes 2a and 2yo during the high potential of the driving pulse width A' to y', and they are heated so that they can emit electrons even during the low potential period of the driving pulses I' to y'. State is preserved. As a result, electrons are emitted from the 15 line cathodes 2i to 2yo only during the 16H period in which low-potential drive pulses I' to Y' are applied to each of them. During the period when a high potential is applied, the potential at the line cathode 2 is lower than the potential at the position of the line cathode 2 determined by the bias voltage applied to the back electrode 1 and the vertical focusing electrode 3. Since the applied high potential becomes positive, no electrons are emitted from the line cathodes 2I to 2Y. Thus, in the line cathode 2, electrons are sequentially emitted from the upper line cathode 2a toward the lower line cathode 2y every 16H period during the effective vertical scanning period. The emitted electrons are transferred to the back electrode 1
The electron beam is pushed forward by the electron beam, passes through the opposing slit 10 of the vertical focusing electrode 3, and is focused in the vertical direction to form a flat electron beam.

Next, the vertical deflection drive circuit 27 is composed of a counter that is reset by each of the vertical drive pulses y to y and counts the horizontal synchronizing signal, and a conversion circuit that converts the count output from D/A. , generates a pair of vertical deflection signals v and v' that change in 16 steps by 1H during the 16H period of each vertical drive pulse. The vertical deflection signals v and v′ both have a center voltage of V ₄ , and v increases sequentially,
v′ is configured to change in opposite directions so as to decrease sequentially. The vertical deflection signals v and v' are applied to the electrodes 13 and 13' of the vertical deflection electrode 4, respectively, and as a result, the electron beams generated from the respective line cathodes 2a to 2y are vertically divided into 16 steps. As mentioned above, on the screen 9, one electron beam is deflected so that a raster of 16 lines is drawn one line at a time from the top.

As a result of the above, electron beams are emitted for a period of 16 hours from the top of the 15 line cathodes 2A to 2Y, and each electron beam is sequentially emitted for one line from the top to the bottom within the 15 sections in the vertical direction. By being deflected, the electron beam is vertically deflected one line at a time on the screen 9 from the first line at the top end to the 240th line at the bottom end, thereby drawing a raster of 240 lines in total.

The electron beam thus vertically deflected is horizontally deflected by 320 degrees by the control electrode 5 and the horizontal focusing electrode 6.
It is divided into sections and taken out. Figure 1 shows one of these categories. The amount of electron beam passing through each section is controlled by a control electrode 5, and horizontally focused by a horizontal focusing electrode 6 into a single narrow electron beam, which is then controlled by horizontal deflection means described below. The R, G, and B phosphors 2 on the screen 9 are deflected horizontally in three stages.
0 sequentially.

That is, the horizontal drive pulse generation circuit 28 is composed of three monostable multivibrators connected in cascade, etc., and is triggered by a horizontal period signal to generate three horizontal drives with equal pulse widths within one horizontal period. Generate pulses r, g, b. Here, as an example, each pulse width is approximately 17 μsec.
3 during the effective horizontal scanning period of 50μsec.
Three pulse widths r, g, and b are generated. These horizontal drive pulses r, g, and b are applied to the horizontal deflection drive circuit 29. The horizontal deflection drive circuit 29 generates a pair of horizontal deflection signals h and h' that change in three stages by being switched by the horizontal drive pulses r, g, and b. horizontal deflection signal h,
Both h' have a center voltage of V ₇ , and change in opposite directions such that h increases sequentially and h' decreases sequentially. These horizontal deflection signals h, h' are applied to electrodes 18 and 18' of the horizontal deflection electrode 7, respectively. As a result, each horizontally segmented electron beam is transmitted to the screen 9 during each horizontal period.
It is horizontally deflected so that the G and B phosphors are sequentially irradiated for 17 μsec each. However, in the display element of FIG. 1, one conductor 18 is used in the horizontal deflection electrode 7.
Or, since 18' is used to deflect two adjacent sections of electron beams and is designed to produce a deflection effect on the adjacent electron beams in mutually opposite directions, 320 sections of electron beams can be obtained. If the odd-numbered sections are deflected in the order of R→G→B, the corner-numbered sections are deflected in the reverse order of B→G→R, and so on. deflected in the direction

Thus, in each line raster, the electron beam is divided into R, G,
Each phosphor 20 of B is sequentially irradiated.

Therefore, a color television image can be displayed on the screen 9 by modulating the electron beam with R, G, and B video signals for each horizontal section of each line.

Next, the modulation control portion of the electron beam will be explained.

First, the composite video signal applied to the television signal input terminal 23 is applied to the color demodulation circuit 30,
Here, the color difference signals of R-Y and B-Y are demodulated,
The G-Y color difference signals are matrix-synthesized, and further, they are combined with the luminance signal Y to generate R, G,
B primary color signals (hereinafter referred to as R, G, and B video signals) are output. These R, G, and B video signals are processed by 320 sample and hold circuit sets 31a to 3.
Added to 1n. Each sample hold circuit group 3
1a to 31n each have three sample and hold circuits for R, G, and B. The sample and hold outputs of these sample and hold circuit sets 31a to 31n are held by memory sets 32a to 32n, respectively.
32n.

On the other hand, the sampling reference clock oscillator 33
is composed of a PLL (phase locked loop) circuit, etc., and generates a reference clock of about 6.4 MHz in this embodiment. The reference clock is controlled to always have a constant phase with respect to the horizontal synchronizing signal H. This reference clock is applied to the sampling pulse generation circuit 34, where it is delayed by one lock period by the shift register register, etc., for an effective horizontal scanning period (approximately 50 μsec) of the horizontal period (63.5 μsec). 320 sampling pulses a to n are sequentially generated, and then one transfer pulse is generated. These sampling pulses a to n correspond to each picture element when one line of the video to be displayed is divided into 320 picture elements in the horizontal direction, and their positions are always constant with respect to the horizontal synchronizing signal H. controlled by.

These 320 sampling pulses a to n correspond to the above 320 sample and hold circuit sets 31.
a to 31n, thereby providing one line to each sample and hold circuit set 31a to 31n.
When divided into 320 picture elements, the R, G, and B video signals of each picture element are individually sampled and held. The sampled and held 320 sets of R, G, and B video signals are stored in 320 sets of memories 32a to 32a after completion of sample and hold for one line.
32n all at once by a transfer pulse t,
Here, it is held for the next one horizontal scanning period.

One line of R, G, and B video signals held in the memories 32a to 32n are applied to 320 switching circuits 35a to 35n, respectively. The switching circuits 35a to 35n each have R, G,
B individual input terminals and a common output terminal that sequentially switches and outputs them, and the output of each switching circuit 35a to 35n is sent to the control electrode 5 of the display element as a control signal for modulating the electron beam.
are individually applied to each of the 320 conductive plates 15a to 15n. Each switching circuit 35a to 35
n are simultaneously switched and controlled by a switching pulse applied from a switching pulse generating circuit 36. The switching pulse generation circuit 36 receives the pulse r.
The effective horizontal scanning period of each horizontal period is approximately 50 μsec, and the switching circuits 35a to 35n are switched for approximately 17 μsec each by dividing the effective horizontal scanning period of approximately 50 μsec into three.
The R, G, and B video signals are time-divisionally output alternately and sequentially, and switching signals r, g, and b are generated to be supplied to the control electrodes 15a to 15n. However, among the switching circuits 35a to 35n, the switching circuits 35a, 35c, etc. of the odd number are changed from R to G.
→B, and the even-numbered switching circuits 35b, 35d...35n are switched in the order of B→G→
The switching is made in the order of R.

What should be noted here is that the switching circuit 3
The switching of the supply of R, G, and B video signals in 5a to 35n and the horizontal deflection of the horizontal deflection of the electron beam irradiation to the R, G, and B phosphors by the horizontal deflection drive circuit 29 are performed both in timing and order. This means that they are synchronously controlled so that they match perfectly. As a result, when the electron beam is irradiating the R phosphor, the irradiation amount of the electron beam is controlled by the R video signal, and G and B are similarly controlled, so that the R and G of each picture element are controlled in the same manner. , B phosphors are controlled by the R, G, and B video signals of the picture elements, and each picture element is displayed by emitting light in accordance with the input video signal. Such control is performed simultaneously on 320 pixels for one line to display one line of video, and then sequentially performed for 240 minutes from the upper line to display one video on screen 9. That will happen.

The above operations are repeated for each field of the input television signal, and as a result,
The screen 9 is similar to a normal television receiver.
The television footage of the video is shown above.

As described above, television images are displayed on this display device.

Note that the terms "horizontal direction" and "vertical direction" in the above explanation refer to the horizontal direction, which is the direction in which line units are displayed when an image is projected, and the vertical direction, which is the direction in which the lines are stacked. It is used in this sense, and is not directly related to the vertical and horizontal directions on the actual screen.

However, in the example device explained above,
The following inconveniences occurred. The first is variation in output level due to variation in capacitance of a capacitor used as an analog memory of a sample-and-hold circuit. The second is the stability of the sampling clock. Unless stability is increased with a PLL circuit, etc., the cause of clock instability will manifest itself in the expansion and contraction of the image in the horizontal direction. but
A PLL circuit configuration requires a reference oscillator such as a highly stable crystal oscillator, resulting in an extremely expensive configuration.

Therefore, it is an object of the present invention to provide a device free from such inconveniences, using a digital memory as a storage device for one horizontal period without causing variations, and furthermore, even if there is some level variation in the output, the display elements can be A pulse width modulation method is used in which brightness can be controlled at time intervals using only on and off states, providing extremely good uniformity. Furthermore, A/D for digitalization
Both the converter clock and the clock used for pulse width modulation use the color subcarrier ( _sc = 3.58MHz).
By using this, an extremely inexpensive and high-performance receiver can be realized without using a new expensive reference oscillator.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure and operation of an embodiment of the present invention will be explained below with reference to the drawings showing one embodiment of the present invention. In this receiver, the third
The horizontal deflection, vertical deflection, and line cathode drive are essentially the same as those shown in the figure, but the signal modulation control portion is completely different. A block diagram of this modulation control section is shown in FIG.

The composite video signal is input from the input terminal 50, and the demodulated R, G, and B primary color signals are output from the output lines 53R, 53.
A/D converters 54R and 53B respectively.
It is input to 54G and 54B. These A/D converters 54R, 54G, and 54B may be general-purpose ones,
Use 6 to 8 bits.

Its operating clock voltage-controlled oscillation (VCO)
56 via line 55. The frequency of this operating clock is set to n times the frequency _s of the color subcarrier supplied via the line 57 (n is a natural number), and the output of the frequency divider 58 which divides the operating clock by 1/n and the color subcarrier The phase detector 59 compares the two signals and provides a control output to the VCO 56. Therefore, this PLL circuit does not require a new reference frequency oscillator. For example, if n = 2 here, n _sc = 7.15909MHz and 1
The number of possible data samples for valid video information during the horizontal scanning period is approximately 360.

The digital three primary color signals output from the A/D converters 54R, 54G, 54B are input in parallel to memories 60a, 60b, . . . 60n for each of R, G, and B. The memories 60a-60n consist of simple data latch circuits whose latch pulses are supplied by shift register 62 via lines 61a-61n. As mentioned above, if n=2, this shift register 62 is a 320-stage parallel output shift register, and its clock is supplied with _nsc clocks from the VCO 56. The start pulse 63 is a pulse with a width of 1 clock of _NSC , and the horizontal synchronization signal output from the synchronization separation circuit 52 to the line 64 is differentiated by the differentiation circuit 65, and the start time of the effective video information is determined by the D flip-flop 63. The logical AND output 66 of a signal suitably delayed up to 100 MHz and the clock of _NSC is used. In this case, there is generally no need for a particularly large delay, and as shown in Figure 4, D
One stage of flip-flop 63 is sufficient.

The output of the differentiating circuit 65 is stored in the memory 60a...60n.
The data contents of 320 sets of memories 67a...67n
It is also used as a pulse for transmission to That is, the contents of the memories 60a-60n are transferred to the memories 60a-67n all at once during the horizontal retrace period.

Next, the three primary color digital signals of R, G, and B in the memories 67a to 67n are switched by a switching pulse applied via a line 69. This switching pulse 69 is generated by an output pulse from a circuit similar to the switching pulse generating circuit 36 in FIG. 3 (described later).

The switched and selected digital three primary color signals are supplied to 320 sets of pulse width modulation (PWM) circuits 70a, 70b...70n. this
It is supplied from the VCO 73 via the clock line 72 of the PWM circuits 70a to 70n. This is VCO7
3, the output is divided by the frequency divider 74 to 1/m (m
is a natural number) and input it to the phase detection circuit 75, and by using the color subcarrier _sc as a reference signal, a PLL circuit configuration is created, and extremely stable n _sc
I'm making a clock. This PWM clock m _sc is the aforementioned A/D conversion clock (n _sc ).
Of course, if you set the same frequency as the
The PLL circuit section can be omitted. Also, if m=1
A PWM clock can be used simply by appropriately converting the impedance of _SC .

In addition, in Fig. 4, the primary color output of the color demodulation circuit 51 is A/D converted by A/D converters 54R, 54G, and 54B, but the composite video signal is A/D converted as it is using a clock, and then Exactly the same effect can be obtained even with a configuration in which digital demodulation is performed. In this case, the clock of the digital demodulator may already be set to n' times _sc for the color subcarrier, but this only affects changing the division ratio of the frequency divider due to the PLL circuit configuration. However, essentially nothing has changed.

Since the outputs of the PWM circuits 70a-70n are generally at logic level, the control electrodes 15a-15
The signals are amplified by pulse amplifiers 76a to 76n to match the saturation level and cutoff level of n and are output to output terminals 77a to 77n, and these output signals are applied to control electrodes 15a to 15n of the display elements.

Next, the specific circuit configuration and timing will be explained in the fifth to
It is shown in Figure 9. Here, explanation will be given assuming that the A/D converter has 6 bits. First, FIG. 5 shows the memory 60, memory 67, and switching circuit 68.
Memories 60 and 67, which are circuit examples, are both constructed using data latch circuits for each bit, and an example of each is shown in FIG. Here, the input state to the data input terminal D is transmitted to the output terminal Q only when the gate terminal G becomes high level, and the input state at the negative edge of the gate terminal G is latched and stored and output to the output terminal Q. is output as

As mentioned above, the latch pulse 61 of the memory 60 is an output pulse of the shift register 62, and is sequentially applied to the memories 60a to 60n during one horizontal scanning period.
Input pulse by pulse. As a result, the A/D converted digital primary color signal is stored in the memory 60 for one horizontal scanning period. The memory 60a corresponds to the leftmost picture element on the screen;
n is the right end.

The stored contents are outputted to the data latch output terminal Q in FIG. 6, which is connected to the input terminal D of the next memory 67. The latch pulse of this memory 67 is commonly supplied to all terminals. That is,
The contents stored in the memory 60 are transferred to the memory 67 all at once by the data transfer pulse.

Although the switches 68 are shown for six bits at once in FIG. 5, they are actually connected in series to the output terminals Q of each bit of the memory 67. As this switch 68, a tristate buffer circuit can be used. The control input, switching pulse 69, is generated as shown in FIG. That is, the signal lines 78, 80,
Pulse 82 is the output of the conventional switching pulse generating circuit 36 shown in FIG. signal line 79
The pulse can be generated by a monomultivibrator or the like triggered by the positive edge of the pulse on signal line 80. As a result, the data selected by switch 68 is input as preset data to 6-bit up counter 86, which constitutes the PWM circuit, during the pulse period of signal lines 79, 81, and 83. This signal line 79,
Pulses 81 and 83 are input to the load terminal of a counter 86 via an OR gate 85.

Therefore, the counter 86 starts counting up from the negative edge of the pulse from the signal line 79. The clock is applied from the signal line 72, and in this embodiment, m=1, that is,
PLL circuits 75, 74, and 73 are unnecessary.

The gate group 87 is a reset priority R-S flip-flop for PWM output, and its set input terminal receives the carry output of the counter 86, and its reset terminal receives the pulse train from the signal line 71. The pulse train of this signal line 71 is generated by a circuit as shown in FIG. If m=1 here, then 6
Maximum pulse width of bit PWM signal is 1/3.58MHz
×64=18 μsec, and the three-phase switch outputs three times in one horizontal period, resulting in a maximum of 54 μsec.
This PWM circuit is a trailing edge fixed type PWM circuit that is reset by a reset pulse 71, and its set timing is modulated by the carry output of the counter 86.

As described above, according to the present invention, by using the color subcarrier, which is essential for television receivers, as the reference for all frequencies, the subsequent signal processing circuit can be realized extremely stably and at low cost. be.

[Brief explanation of the drawing]

FIG. 1 is an exploded perspective view showing the basic configuration of an example image display element used in a television receiver according to an embodiment of the present invention, FIG. 2 is an enlarged view of the screen, and FIG. 3 is a drive of the device. A block diagram showing the basic configuration of the circuit, FIG. 4 is an overall block diagram of a television receiver according to an embodiment of the present invention, FIG. 5 is a detailed circuit diagram of its memory section and switch section, and FIG. 6 is its detailed circuit diagram. The circuit diagram for one bit of memory, Figure 7 is its timing diagram, and Figure 8 is its timing diagram.
A circuit diagram of a PWM reset pulse generation circuit, No. 9 is a circuit diagram of the PWM circuit. 2... Line cathode as an electron beam source, 3,3'...
Vertical focusing electrode, 4... Vertical deflection electrode, 5... Electron beam flow control electrode, 6... Horizontal focusing electrode, 7... Horizontal deflection electrode, 8... Electron beam acceleration electrode, 9... Screen, 20... Fluorescent material, 23... Input Terminal, 24... Synchronization separation circuit, 25... Vertical drive pulse generation circuit, 26
...Line cathode drive circuit, 27...Vertical deflection drive circuit, 2
8... Horizontal drive pulse generation circuit, 29... Horizontal deflection drive circuit, 30... Color demodulation circuit, 31a to 31n... Sample hold circuit group, 32a to 32n... Memory group, 34... Sampling pulse generation circuit, 35a
~35n...Switching circuit, 36...Switching pulse generation circuit.

Claims (1)

[Scope of Claims] 1. A screen on a screen is vertically divided into a plurality of sections, an electron beam is generated for each vertical section, and the electron beam is sequentially deflected in the vertical direction for each of the vertical sections. A plurality of lines are displayed in each section, and phosphors of red, green, and blue colors are arranged horizontally in each horizontal section obtained by dividing the screen on the screen horizontally, and the electron beam is A display element is used which is divided into the above-mentioned horizontal sections, focused and deflected in the horizontal direction for each horizontal section, so that each horizontal section is sequentially irradiated with the phosphor of each color to emit light. In an image display device, the three primary color signals of red, green, and blue are converted into digital three primary color signals by an A/D converter driven by a first clock that is synchronized with the color subcarrier and has a frequency that is a natural number multiple of the color subcarrier. a first memory for storing the digital three primary color signals until the next horizontal retrace period; and a means for converting the digital three primary color signals to the next horizontal retrace period, the contents of which are transferred all at once during the horizontal retrace period and stored. a second memory that is driven by a second clock that is synchronized with the color subcarrier and has a frequency that is a natural number multiple of the color subcarrier; a pulse width modulation circuit that converts the output of the pulse width modulation circuit into a pulse having a pulse width that is a natural number multiple of the period of the second clock using all or a part of the immediately following horizontal scanning period; and means for displaying a color television image on the screen according to the three primary color signals by controlling the time during which the electron beam is irradiated to the phosphor of each color. receiver. 2 The screen on the screen is vertically divided into a plurality of sections, an electron beam is generated in each vertical section, and the electron beam is sequentially deflected in the vertical direction for each vertical section to form a plurality of lines in each vertical section. The screen is divided horizontally, and phosphors of red, green, and blue colors are arranged horizontally in each horizontal section, and the electron beam is divided into each horizontal section. In an image display device using a display element, which is divided into two, focused and deflected in the horizontal direction for each horizontal section, and sequentially irradiated with the phosphor of each color for each horizontal section to emit light, means for converting the composite video signal into a digital composite video signal by an A/D converter driven by a first clock synchronized with the color subcarrier and having a frequency that is a natural number multiple of the color subcarrier; and demodulating the digital composite video signal. a digital demodulating means for obtaining the digital three primary color signals; a first memory for storing the digital three primary color signals until the next horizontal scanning period; and a first memory for storing the digital three primary color signals until the next horizontal scanning period; a second memory for transferring and storing the same, and a second clock that is synchronized with the color subcarrier and has a frequency that is a natural number multiple of the color subcarrier, and is configured to transfer the stored contents of the second memory to the second memory that is used for the transfer. a pulse width modulation circuit that uses all or part of the horizontal scanning period immediately after the horizontal retrace period to convert the pulse into a pulse having a pulse width that is a natural number multiple of the period of the second clock; and means for displaying a color television image on the screen according to the three primary color signals by controlling the time for irradiating the electron beam to the phosphor of each color using the output of the width modulation circuit. A television receiver featuring: