JPS6325382B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a memory access control method.

In particular, it has a function of determining the priority of memory access requests from a plurality of subprocessor groups according to a predetermined priority order and selecting one memory access request, and performing memory access based on the selection result. The present invention relates to a memory access control method in a system control device compatible with the sub-processor group.

An example of a conventional memory access control method of this type is shown in FIG. 1, in which two system control devices 20A and 20B have first priority determination circuits (hereinafter abbreviated as first circuits) 21A and 21, respectively.
B and second priority determination circuits (hereinafter abbreviated as second circuits) 22A and 22B, each of which has four subprocessors 11A to 14A and 11B to 14.
Memory access requests 11A' to 14A' and 11B' to 14, up to a total of eight memory access requests, up to four each from two subprocessor groups 10A and 10B consisting of B.
The memory access request with the first priority is selected from B' and accesses the memory 30A or 30B.

Hereinafter, the system on the left with the reference symbol A attached will be referred to as the own system, and the system on the right with the reference symbol B will be referred to as the other system, but A and B may be interchanged.

The first circuit is the subprocessor 11A to 1 of its own system.
Memory access request 11A' to 14 from 4A
Only A' is directly input, and one of them is selected according to a predetermined priority and output to the second circuit 22A of the own system and the second circuit 22B of the other system.

The second circuit 22A has the first circuit output 21 of its own system.
A' and the first circuit 21B' of another system are input, one of them is selected according to a predetermined priority order, and if the selected one is the first circuit output 21A' of the own system. If this is the second circuit output 22
It is output as A' to the flip-flop 26A of its own system.

Flip-flop 26A outputs this second circuit output 2.
When set by 2A', it outputs a memory access request 26A' to memories 30A and 30B,
Commands, addresses, write data, etc. of the selected sub-processor are supplied to the memories 30A and 30B by a circuit not shown, and memory access is executed.

In such a conventional configuration, the memory access requests 11A' to 14A' from the subprocessor are not directly input to the first circuit 21B of the other system, but are output from the first circuit after passing the preliminary round in the first circuit 21A of the own system. It is indirectly inputted as 21A' to the second circuit 22B of another system.

The first input to the second circuit 22B of the other system
Because the circuit output 21A has a large number of interfaces, it is generally supplied via a cable or the like to the system control devices 20A and 20B, which are each housed in an independent enclosure.
T ₃ is considerably longer than the propagation time T ₁ of the first circuit output 21A' to the second circuit 22A within the own system. Therefore, the memory access request propagation time from when the subprocessor outputs a memory access request until it reaches the memory is as follows: from the subprocessor to the first circuit, from the first circuit to the second circuit of another system, and from the second circuit to the memory. The _total propagation time T ₀ , T ₃ , and T ₂ up to _T This has the disadvantage that it is longer than the access request propagation time T _A and increases the memory access time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory access control method that eliminates the above-mentioned drawbacks and speeds up memory access time.

The method of the present invention is a memory access control method for a plurality of subprocessor groups that share a main memory device, and for each subprocessor group, determines the priority of memory access requests directly input from the subprocessor group according to a predetermined priority order. a first priority determining means for selecting one memory access request based on a predetermined priority order, and selecting one memory access request by determining the priority of memory access requests directly input from other subprocessors according to a predetermined priority a third priority determining means for finally selecting one of the selection results of the first priority determining means and the second priority determining means according to a predetermined priority order; The present invention is characterized in that the memory access request is provided to all the main storage devices only when the finally selected memory access request is output from the corresponding sub-processor group.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a circuit diagram showing one embodiment of the present invention.

Sub-processor groups 10A and 10B, system control devices 20A and 20B, and memory 30
Each information processing device consisting of A and 30B can execute separate jobs with two operating systems, and can also execute one larger job with one operating system. Furthermore, a more reliable information processing system can be constructed by using one operating system as a duplex system using two information processing apparatuses. In other words, it has become possible to configure flexible information processing systems to meet the needs of recent users, who are becoming more and more oriented toward more sophisticated and diverse information processing.

As in the conventional example shown in FIG. 1, these information processing devices are operated under one operating system, and eight sub-processors 11A to 14A and 11B to 14B, which are arithmetic processors and input/output processors, are used to process multiple memories. When there is an access request, the system control devices 20A and 20B determine the priority according to a predetermined priority order, select only one memory access request, and send the request to the subprocessor that outputs the selected memory access request. Allows access to memory.

As can be seen from FIG. 3, in this embodiment, the system control device 20A has three priority determination circuits 23A.
~25A, two of the circuits 23
A and 24A each have their own subprocessor 11.
Memory access request 11A' from A~14A
14A' and other subprocessors 11B to 14
Memory access requests 11B' to 14B' from B are directly input. In other words, memory access requests from all sub-processors are directly input to the priority determination means consisting of the three priority determination circuits 23A to 25A.

Therefore, as shown in FIG. 4, the difference in propagation time between the memory access requests from the sub-processors of the own system and the sub-processors of the other system until they reach the memory becomes small, so that the memory access time can be increased.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the conventional technology, FIG. 3 is a diagram showing an embodiment of the present invention, and FIG. 2 and FIG. 4 are diagrams for explaining FIG. 1 and FIG. 3, respectively. . In the figure, 11A to 14A, 11B to 14B
...Subprocessor, 10A, 10B...Subprocessor group, 21A, 21B...First priority determination circuit (first circuit), 22A, 22B...Second priority determination circuit (second circuit), 23A, 24A, 25
A, 23B, 24B, 25B...Priority determination circuit, 20A, 20B...System control device, 26
A, 26B...Flip-flop, 30A, 30
B...Memory, 11A' to 14A', 11B' to 14
B', 26A' to 26B'...Memory access request,
21A', 21B'...1st circuit output, 22A', 2
2B′...Second circuit output, T ₀ , T ₀ ′, T ₁ , T ₂ , T ₃
...Propagation time, T _A , T _B ...Memory access request propagation time.

Claims (1)

[Scope of Claims] 1. In a memory access control method for a plurality of sub-processor groups that share a main storage device, a priority order in which the priority of memory access requests directly input from the sub-processor group is predetermined for each of the sub-processor groups. a first priority determination means that determines the priority of memory access requests directly input from other subprocessors and selects one memory access request according to a predetermined priority order; a second priority determination means for selecting an access request; and a final selection of one of the selection results of the first priority determination means and the second priority determination means according to a predetermined priority order. A third priority determination means is provided so that the memory access request is supplied to all main storage devices only when the finally selected memory access request is output from the corresponding subprocessor group. A memory access control method characterized by: