JPS6325435B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a memory module in which a plurality of two-dimensional memories are stacked to form a three-dimensional structure.

Prior Art and Problems By stacking Z pieces of two-dimensional memories in which memory cells are selected by horizontal address X and vertical address Y, a three-dimensional memory module conceptually shown in FIG. 1 is obtained. This memory module can be
It is possible to write to and read from memory cells in both directions simultaneously. For example, the depth direction address Z is a memory plane selection signal (same type as a chip select signal), and if it is always in the selected state, it will be a point (Xi, Yj) on the X and Y axes of the memory plane.
When , all memory cells connected in the Z direction are selected, that is, simultaneous selection in the Z direction is performed. Furthermore, eight memory cells in the X direction can be simultaneously selected with the same X address. The square bar 10 in the X direction in FIG.
A block of memory cells in which bits are written simultaneously is shown, and 12 represents a group of memory cells in which bits are written simultaneously in the Z direction. Reference numeral 14 indicates a group of memory cells arranged in the Y direction. Although it is possible to select them simultaneously using a similar method, if the group of memory cells 10 in the X direction is simultaneously selected, the group of memory cells in the Y direction 14 can be selected individually.
For example, if this cell group 14 consists of eight cells, eight accesses must be made. In addition,
Here, writing in any one of the X, Y, or Z directions is defined as a one-dimensional mode, writing in the XY, YZ, or ZX plane is defined as a two-dimensional mode, and writing in an XYZ three-dimensional plane is defined as a three-dimensional mode.

OBJECTS OF THE INVENTION The present invention aims to provide a memory device that can access any location in any one-dimensional, two-dimensional, or three-dimensional mode.

Structure of the Invention The present invention enables simultaneous access to multiple (N) bits in the X direction and selectable by Z address.
In a storage device including a three-dimensional memory module 20 consisting of a plurality of XY two-dimensional memories, a shift register 22 receives write data of multiple (N) bits and sequentially shifts them one bit at a time when a shift clock is applied; A first multiplexer 26 that commonly outputs multiple bit write data of the shift register to a plurality of two-dimensional memories simultaneously or sequentially, an X address counter 28, a Y address counter 30, and a control circuit 32 for these address counters. , a second multiplexer 34 that sequentially extracts the read data of the memory module 20 in two-dimensional memory units, and a third multiplexer that sequentially extracts the read data of the memory module 20 one bit at a time from each two-dimensional memory, a plurality of pieces in total. This will be described next with reference to embodiments.

Embodiment of the Invention FIG. 2 shows an embodiment of the present invention, and 20 is the memory module shown in FIG. 1, which in this example consists of eight memory planes each having 1024 memory cells in both the X and Y directions. . 22 is a shift register into which write data WD is input, 24 is a buffer, and 26 is a multiplexer. In this example, the write data WD is 8 bits, and forms a unit of simultaneous writing. When writing this in the X direction of the memory 20, the multiplexer 26 transfers the 0th to 7th bits of the write data WD to each of the eight memory planes MP0 to MP7 of the memory module 20, as shown in FIG.
Commonly output to. In other words, the multiplexer 26 functions as an expander of 8→8×8=64. 8 memory planes by Z address signal
Assuming all MPs are selected, the memory plane is written as shown in FIG. 3b. The memory plane selected by the Z address signal is
If there are only three sheets MP0 to MP2, the three sheets MP0 to MP2 are written as shown in FIG. 3b, and the remaining four sheets MP3 to MP7 are not written.
If the screen is to be displayed in three colors, R, G, and B, such a selection is made.

In addition, in Fig. 3b, it seems that the same data is written to each memory plane, but if you select the memory planes sequentially, this will not happen, and the same data will be written to the same 0, 1, 2, etc. , the first, second, . . . bits also have different contents (data). When selecting a memory plane, a Z address signal (not shown) is introduced into the memory 20. If there are 8 memory planes, the number of bits of the address signal can be 3, and this can be decoded to generate any 1 bit.
You can select one. If you select multiple planes at the same time, you will need more bits, but there are not so many combinations of memory planes to use, so it is better to select the number of bits accordingly and decide on the decoding circuit.

When writing the write data WD in the Z direction, the multiplexer 26 performs switching as shown in FIG. In other words, the 0th bit of the write data is made into 8 0's and all of these are stored in the 0th memory plane MP0.
The first bit of the write data is set to eight 1's, and all of these are sent to the first memory plane MP1, and the same process is repeated. If this is done, writing to each memory plane will be as shown in FIG. 4b, and the writing will be in the Z direction. If the simultaneous selection of 8 bits in the X direction is stopped and the bits are incremented one by one, the write data can be arranged in 8 bits in the Z direction and only 1 bit in the X direction.

28 in Figure 2 is the X address counter, 30 is the Y
Address counters 32 are control circuits for these address counters. By changing the X address in 8-bit steps, Figures 3 and 4
The writing shown in each b of the figure progresses in the X direction, and
When the address is increased by +1, it advances in the Y direction.

Next, 34, 36, and 38 are multiplexers on the reading side, MPX34 is for plane selection, MPX
36 is for bit selection, MPX38 is for 2D/
This is for three-dimensional switching. 64 bits are read out from the memory 20 at the same time, and since the data bus is 8 bits, the MPX 34 selects a plane and outputs the 64 bits in 8 batches of 8 bits each. The same applies to the MPX36, but here the bits are selected, that is, the 0th bit, 1st bit, 2nd bit, . . . of each memory plane are selected in the order of 8 bits each. In other words, MPX34 handles writing in the X direction,
MPX36 deals with Z direction writing,
These selections and changes are made by the MPX38.

When writing in the Y direction, the shift register 22 is used. To write 8-bit write data WD in the Y direction, write is performed 8 times while sequentially adding 1 to the Y address, but each time the shift register 22 shifts 1 bit, the contents of the register become as shown in Figure 5. , if the X address of this write is X0 for all 8 times, then in the Y direction 0, 1, 2,
. . . is written, and writing as shown in block 14 in FIG. 1 can be performed. If you also select the memory plane, you can write on the YZ plane at X=X0. This shift register 22 serves as a mere buffer in the above-mentioned X-direction writing, and performs the above-mentioned shift operation in which a shift clock is applied.

The work of writing in the X direction while selecting one bit at a time is to fix Y and Z and write while incrementing X. When X reaches the end, return it to the start end and increase Y.
1, and when you reach the end of the X, Y plane, return to the starting end and add +1 to Z. Then, select the addresses X, Y, and Z appropriately and set XY, YZ, ZX.
It is also possible to write on a plane or even in an XYZ three-dimensional space.

The operation of writing data in the Y direction instead of in the X direction is used to rotate characters or figures by 90 degrees. As mentioned above, the Z direction is often information about the hue and shading of an image.

Effects of the Invention As explained above, according to the present invention, it is possible to freely write data in the X, Y, and Z directions to a three-dimensional memory module simultaneously as necessary, and to write data to an image memory, etc. It is extremely effective when applied.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a memory module according to the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, FIGS. 3 and 4 are diagrams explaining the operation of the multiplexer, and FIG. 5 is a shift diagram. FIG. 3 is a diagram illustrating the operation of a register. In the drawing, MP is a two-dimensional memory, 20 is a three-dimensional memory module, WD is write data, 22 is a shift register, and 26 is a multiplexer.

Claims (1)

[Claims] 1. XY2 that allows simultaneous access to multiple (N) bits in the X direction and selectable by Z address
In a storage device including a three-dimensional memory module 20 consisting of a plurality of dimensional memories, write data of multiple (N) bits is input,
A shift register 22 that sequentially shifts the data one bit at a time when a shift clock is applied; a first multiplexer 26 that commonly outputs the multiple bit write data of the shift register to a plurality of two-dimensional memories simultaneously or sequentially; A counter 28, a Y address counter 30, a control circuit 32 for these address counters, and a second multiplexer 3 that sequentially retrieves read data from the memory module 20 in two-dimensional memory units.
4 and the read data of the memory module 20, 2 each.
A storage device comprising a three-dimensional memory module, comprising a third multiplexer 36 for sequentially extracting a plurality of bits from the dimensional memory, one bit at a time.