JPS6325716B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a bipolar transistor.

Semiconductor integrated circuits are becoming more highly integrated and faster as technology advances. Among them, a technique was developed in which the periphery of the element region was covered with a thick insulating film (oxide film) and electrode openings were provided in contact with the oxide film.
This technology has made it possible to dramatically reduce the shape and parasitic capacitance of elements. However, even with this technology, when it comes to bipolar transistors, the distance between the emitter electrode hole and the base electrode hole, which greatly affects the size of the base region, is determined by the pattern required between the electrode hole and the wiring metal. It is determined by the margin and the minimum processable size of the wiring metal.
The above-mentioned margin is necessary to always cover the entire surface of the hole with the wiring metal even if there is misalignment between the hole-opening process and the wiring process or dimensional deviations that occur during processing, and is usually about 2 μm. Furthermore, the minimum dimension that can be processed for wiring metal is approximately 4μ. Therefore, the maximum distance between the openings between the emitter electrode and the base electrode is about 8μ. In this way, in the conventional technology, the emitter electrode
The distance between the holes in the base electrode is 8μ because a margin is required between the holes and the wiring metal, even if there is a processing capability of 4μ. This is an obstacle to reducing the base area, that is, making the transistor smaller and reducing parasitic capacitance. What has been described here applies not only to bipolar transistors but also to all semiconductor devices having electrodes adjacent to each other.

An object of the present invention is to provide a method for manufacturing a high-performance bipolar transistor by reducing the interval between electrode holes on a semiconductor element to the minimum size that can be processed, thereby reducing the shape and parasitic capacitance of the semiconductor element. It's about doing. In other words, the gap between the emitter electrode and the base electrode of a bipolar transistor is reduced to the minimum size that can be processed, thereby reducing the base area and creating a small transistor suitable for high density and low parasitic capacitance suitable for high speed response. The purpose is to provide a manufacturing method.

A feature of the present invention is that a first photoresist is applied on a semiconductor substrate in which the base region is covered with a thin insulating film and the surrounding area is covered with a thick insulating film, and the portion where the base electrode is formed and the emitter are coated with the first photoresist. a step of selectively removing the first photoresist in a region where an emitter electrode is to be formed; and a step of selectively removing the thin insulating film using the remaining first photoresist as a mask to form an emitter electrode. and exposing the base electrode connection region and simultaneously removing selective surface portions of the thick insulating film by approximately the same thickness as the thin insulating film, and covering the base electrode connection region with a second photoresist. and forming an emitter region by introducing impurities into the emitter forming region in the base region by ion implantation using the first and second photoresists and the portion of the thick insulating film from which the surface has been removed as a mask. a step of, after removing the second photoresist, depositing a metal layer on the entire surface with approximately the same thickness as the thin insulating film; and removing the first photoresist and the metal layer thereon. an emitter electrode that connects to the emitter region and extends over a thick insulating film from which the surface has been removed; and an emitter electrode that connects to the base electrode connection region and extends over a thick insulating film from which the surface has been removed. A method of manufacturing a semiconductor device includes forming base electrodes for each base electrode. That is, according to the present invention, a photoresist (hereinafter abbreviated as PR) is first applied in order to provide openings for electrodes in the thin oxide film on the element formation region. Next, a pattern including electrode openings is formed on this PR, and this pattern also serves as a wiring pattern. Next, using this PR pattern as a mask, holes are formed using a method such as chemical etching. At this time, on the thick oxide film,
Area without PR pattern (i.e. wiring pattern)
Also, the thickness of the thin oxide film on the top surface of the device is scraped away, resulting in a dent.
Next, a wiring metal is deposited on this semiconductor substrate including the PR pattern, and the PR is peeled off. At the same time, the metal on the PR is also removed, leaving a wiring metal pattern with exactly the same position and shape in the opening on the element and in the recess on the thick oxide film. In other words, the electrode opening and the wiring metal are self-aligned, so no design margin is required. Therefore, the spacing between the electrodes can be reduced to the minimum size that can be processed, and the above objective can be achieved. Further, according to the present invention, even on a thick oxide film as described above, a recess is formed directly under the wiring metal, so that the unevenness between the wiring metal and the surrounding oxide film is alleviated. In particular, since the thickness of the wiring metal is selected to be approximately the same as the thickness of the oxide film on the element, the flatness of this substrate is very good, making it convenient for multilayer wiring. Moreover, the PR pattern of the present invention, that is, the first PR pattern, is also used as a mask for partitioning and forming the emitter region. In this way, in the present invention, only by forming the first PR pattern,
It becomes possible to form a flattened base and emitter electrode, form an emitter region, form an emitter contact, and form a base contact, thereby reducing the number of alignment steps and providing a highly productive method.

Next, technology related to the present invention will be explained using the drawings.

FIG. 1 shows a sectional view of the vicinity of the base region of a transistor in which the base and emitter regions are formed in a silicon substrate, after the oxidation process after emitter diffusion has been completed. 1 is the collector region, 2 is the thick oxide film around the base region, 2' is the thin oxide film on the base region,
3 indicates a base diffusion region, and 4 indicates an emitter diffusion region. Hereinafter, the same numbers represent the same parts throughout all the drawings. In the conventional technology, holes are then formed by chemical etching, etc. using the PR pattern, which includes patterns of holes for emitter electrodes and holes for base electrodes, as a mask, and after this PR pattern is peeled off, a wiring metal layer is applied. Then, a wiring pattern is formed on the metal layer using the newly formed wiring PR pattern. This state is shown in FIG. 5 is a hole for base electrode, 6
is an opening for an emitter electrode, and 7 is a wiring. As already mentioned, in this prior art, the distance between the openings 5 and 6 is equal to the design margin 1 between the openings and the wiring pattern.
01 and the minimum processing dimension 102.

According to the technology related to the present invention, after the state shown in FIG. 1, as shown in FIG. As a mask,
Open holes 5 and 6 are provided by chemical etching or the like. At this time, a portion of the thick oxide film layer 2 on which the PR is not placed (a portion where the wiring is inserted) is also etched away, and a recess 12 is formed. (In the figure, the state of the oxide film before openings is shown by dotted lines.) Next, leave this PR pattern 11 as it is,
When the wiring metal layers 13 and 13' are deposited as shown in FIG. 4, and then the PR pattern 11 is peeled off, the metal layer 13' on top of the PR is also removed at the same time, and the hole is opened as shown in FIG. 5 and 6 and the wiring metal layer 13 whose position and shape completely match with the recess 12 on the thick oxide film are left. As can be seen from the figure, the distance between the base electrode hole 5 and the emitter electrode hole 6 is 103.
Since the margin in the case of the prior art is unnecessary, it can be reduced to the minimum size that can be processed. Also, when comparing the unevenness caused by the wiring with the conventional technology shown in Figure 2,
Wiring made using this technology is, so to speak, sunk into the oxide film, resulting in extremely small irregularities. Furthermore, if the thickness of the metal layer is made equal to the thickness of the thin oxide film, it becomes almost completely smooth.

Next, an embodiment of the present invention will be described regarding a so-called washed emitter bipolar transistor (WE transistor). In this case, the emitter diffusion process comes after the opening, which makes the process a little more complicated than the above process, but the basic concept of using the PR for forming the opening as it is for wiring processing remains the same. Note that the numbers in the following figures also refer to the same ones as above. State after oxidation process after base diffusion of WE transistor (shown by dotted line in Figure 6)
Then, as shown in FIG. 6, using the first PR pattern 11 including the emitter electrode hole, the base electrode hole, and at least a part of the wiring pattern as a mask, the base electrode hole 5 is formed by chemical etching or the like. An opening 6 for the emitter electrode and a recess 12 on the thick oxide film are formed. Next, as shown in FIG. 7, a second PR pattern 14 is formed to cover the opening 5 in the portion that will become the base electrode, leaving the first PR as it is. The second PR is selected to have different chemical properties from the first PR, and to contain a solvent or etchant that can dissolve only the second PR without dissolving the first PR. For example, a negative PR may be selected as the first PR, and a positive PR may be selected as the second PR. next,
Using ion implantation, an impurity that can form an emitter is diffused through the emitter electrode opening 6,
An emitter region 4 is formed. Next, only the second PR is peeled off, and the wiring metal layers 13 and 1 are removed as shown in FIG.
3' is applied. If it is necessary to prevent a short circuit between the base and the emitter due to silicon atoms on the emitter melting into the wiring metal, an appropriate amount of polycrystalline silicon is deposited prior to depositing the metal. If you peel off the first PR in the same way as in the previous example, you will see a WE transistor with a smooth surface and its wiring system, with the base-emitter electrode opening distance reduced to the minimum size that can be processed, as shown in Figure 9. is obtained.

As described above, according to the present invention, the design margins for electrode openings and wiring patterns, which were conventionally necessary, are no longer necessary, the transistor can be made smaller, and the parasitic capacitance can also be reduced. This effect is tremendous for devices that have three or more electrode holes in one base region, such as memory cells using bipolar transistors.
The base area, which needed to be as large as 100 µm, was reduced to 20μ x 4μ using the same level of processing technology. Further, according to the present invention, surface irregularities caused by wiring layers can be made very small, and workability and reliability of multilayer wiring can be improved. As described above, according to the present invention, it is possible to provide an integrated circuit with a high degree of integration, high speed, and high reliability.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views showing a transistor according to the prior art, and FIGS. 3 to 5 are cross-sectional views illustrating a method of manufacturing a transistor related to the present invention, and FIG. This is a completed drawing. 6 to 9 are cross-sectional views illustrating an embodiment of the method for manufacturing a transistor according to the present invention, and FIG. 9 is a completed view. The numbers in the figure are common to all figures, 1...Collector region, 2...Thick oxide film around the element, 2'...Thin oxide film on the element, 3...Base diffusion region, 4...
... Emitter diffusion region, 5 ... Base electrode opening,
6... Opening for emitter electrode, 7... Wiring layer, 11
... Photo resist, 12 ... Indentation on thick oxide film, 13, 13' ... Wiring layer, 14 ... Second
Photo resists, 101 to 103...Design dimensions.

Claims (1)

[Claims] 1 A semiconductor substrate with a base region covered with a thin insulating film and a thick insulating film surrounding the base region with a first
selectively removing the first photoresist in a portion where a base electrode is formed, an emitter region and a portion where an emitter electrode is formed; and removing the remaining first photoresist. Selectively removing the thin insulating film as a mask to expose the emitter formation region and the base electrode connection region, and simultaneously removing selective surface areas of the thick insulating film by approximately the same thickness as the thin insulating film. a step of covering the base electrode connection region with a second photoresist; and a step of implanting impurities into the base by ion implantation using the first and second photoresists and the portion of the thick insulating film from which the surface has been removed as a mask. a step of introducing a metal layer into the emitter formation region in the region to form an emitter region, and a step of depositing a metal layer having a thickness approximately the same as the thin insulating film over the entire surface after removing the second photoresist. , by removing the first photoresist and the metal layer thereon, the emitter electrode and the base electrode connect to the emitter region and extend over the thick insulating film from which the surface has been removed. 1. A method of manufacturing a semiconductor device, comprising forming base electrodes connected to the regions and extending on the thick insulating film from which the surface has been removed.