JPS6326605B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a constant monitoring system for input circuits, and particularly to a constant monitoring system suitable for input circuits of digital protective relay devices that require high accuracy.

When inputting power system voltage and current to a digital protective relay device, these system primary quantities are analog quantities, so they are converted from analog to digital (hereinafter referred to as A-D conversion) and then input into the device. Data processing and calculations must be performed.
In this case, in order to convert a large amount of analog information from analog to digital with high accuracy and efficiency, it is necessary to use a large number of analog signal electronic circuits such as filters, sample holders, and analog multiplexers.

Conventionally, as a constant monitoring method for the input circuit of a digital protective relay device that requires high accuracy and high reliability, the input amount from the power system is three-phase balanced voltage and current, and the vector sum of I was monitoring the input circuit, noting that it became zero.

FIG. 1 shows an example of the configuration of a digital protective relay device that receives system primary quantities as input. In the figure, BA,
BB and BC are three-phase busbars, and LA, LB, and LC are three-phase transmission lines that are protected by the digital protective relay device. 3-phase AC voltage, current is instrument transformer PDA,
Detected by PDB, PDC, CTA, CTB, and CTC and sent to digital protective relay device SBD.
The analog voltage and current input to the SBD are level-converted and band-controlled by the input circuit IN.
The signal is then A-D converted and introduced into the logic operation unit CPU. The logic operation unit CPU processes the input digital quantities of voltage and current according to a predetermined program, and determines whether protection is necessary. When it is determined that holding operation is required, the output circuit OUT will
Give a trip command to the shield breakers CBA, CBB, and CBC.

Figure 2a shows such a digital protective relay device.
Of the SBD input circuit IN, the instrument transformer CTA,
A conventional example of an input circuit for the current detected by CTB and CTC, which also includes a constant monitoring circuit, is shown. Note that the same applies to voltage input circuits, so in the following description, a current input circuit will be shown as a representative example. In this figure, first, a circuit portion for inputting current will be explained.

The secondary side of the instrument transformer CT of each phase is configured to return from the auxiliary transformer Tr of the phase to the respective instrument transformer CT via the zero-phase auxiliary transformer Tr ₀ . Auxiliary transformers for each phase and zero phase (Tr _a , Tr _b ,
In the secondary circuit of the auxiliary transformer primary current (I _a ′, I _{b ′} , I _c ′, I ₀ ′), the secondary current ( _{I a ,} I _b , I _c , I ₀ ) and secondary voltages (V _A , V _B , V _C , V ₀ )
occurs. This secondary voltage is used as an input signal for the system primary current by filters 1A, 1B, 1C,
1D to the sample holder 2. In addition, when a line-to-line signal is required in the calculation of the digital protective relay device SBD, the auxiliary transformer Tr
The methods used include inputting the line-to-line signal through vector synthesis at the step 2, or creating it by vector addition of digital values after inputting the phase signal.
The input voltage V ₀ is derived from V _A , V _B , and _VC for monitoring the input circuit, as will be described later.

Meanwhile, within the input circuit, clock pulses are generated by a clock oscillator 5 and supplied to a counter 7 and a timing circuit 6. Sample holder 2
has four analog inputs V _A , V _B ,
V _C and V ₀ are added, and a sample command is periodically given from the counter 7 via the AND gate 8, and all analog inputs V _A ,
The instantaneous values of V _B , V _C , and V ₀ are stored. The analog multiplexer 3 is supplied with the output of the sample holder 2 and the 3-bit address information from the counter 7, and the output is applied to the A/D converter 4 together with the timing pulse of the timing circuit 6. As a result, a plurality of analog inputs are quantized and sent to the logic operation unit CPU of the digital protection relay device SBD.

Next, the monitoring circuit for the input circuit will be explained. In this example, the four outputs of the sample holder 2 are added to the adder 10 as monitored voltages for detecting input circuit abnormalities, and the vector sum 〓V〓=
V〓 _A ′+V〓 _B ′+V〓 _C ′V〓 ₀ ′ is taken and applied to analog comparators 9P and 9N. Here, the system primary quantity is in three-phase equilibrium under normal conditions, so
V〓 _A ′＋V〓 _B ′＋V〓 _C ′＝V〓 ₀ ′＝0, 〓V〓＝
It should be 0. From this, if CT, Tr, 1, 2
If an abnormality occurs in a part of the input section consisting of , and the signal of that part changes, 〓V〓≠0,
With V〓≠0, the input circuit can be constantly monitored.
In order to achieve this constant monitoring, reference power supplies 13P and 13N are provided as reference voltages, and reference voltages (-V _L ,
+V _L ) are supplied to analog comparators 9P and 9N respectively, and compared with the magnitude of the monitored voltage 〓V〓.When 〓V〓>V _L or 〓V〓<-V _L , an input circuit error is detected. To detect.

FIG. 3 shows an operating waveform diagram of the monitoring circuit. Figure a shows four input analog signals I〓a', _I〓b ', _I〓c ', _I〓0 ' on the primary side _of the auxiliary transformer Tr. When the power system is normal, the vector sum is almost equal to zero. That is, I〓 _a ′+I〓 _b ′+I〓 _c ′−I〓 ₀ ′≒0. Figure b shows a sample command for the sample boulder 2, which causes the input signals I〓 _a ′,
Signals V〓 _A ′, V〓 _B ′ corresponding to I〓 _b ′, I〓 _c ′, I〓 _{0 ′}
, V〓 _C ′,
V〓 ₀ ′ is held and the sample holder output in Figure c
V〓 _A ′, V〓 _B ′, V〓 _C ′, V〓 ₀ ′. However, for convenience of explanation, it is assumed here that there is no delay between the signal a and the signal c. Figure d shows the output 〓V〓 of the adder 10, and e shows the outputs of the comparators 9P and 9N, respectively. At time t ₀ , a circuit abnormality (for example, due to A phase abnormality,
When V _A '=0) occurs, the output of adder 10 increases and comparator 9P or 9N produces an output. Note that the outputs of the comparators 9P and 9N are stored for a certain predetermined period and continue to be output. In this diagram, adder 1
The reason why an output of 0 is always generated and is not zero is due to errors in the instrument/auxiliary transformer and input circuit elements shown in FIG.

Now, when considering errors in the input circuit, especially transformer errors, for example, it is assumed that the primary analog quantities I〓 _a ′, I〓 _b ′, and I〓 _c ′ of the auxiliary transformer Tr are three-phase balanced. When, I〓 _a ′, I〓 _b ′, I〓 _c ′ on the secondary side are as shown in Fig. 2 b
The three phases are not balanced because each phase includes errors I〓 _ae , I〓 _be , and I〓 _ce . It is well known that transformers include errors, and as shown in the transformer input/output characteristics in Figure 4, ideally the characteristics should be like the straight line with two-dot chain lines, but in reality they are for
Because Tr ₀ , _Tra , Tr _b , and Tr _c have saturated characteristics, the difference between the ideal characteristics and the saturated characteristics becomes a transformer error. Moreover, this saturation characteristic differs depending on the transformer, and even if the input is the same (I _a ′ = I _b ′ = I _c ′), the output (I _a ,
I _b , I _c ) will differ for each transformer. However, since it is a saturation characteristic, the larger the current, the larger the error tends to occur. Having such saturation characteristics is not limited to the auxiliary transformer Tr.
The same applies to the instrument transformer CT. In addition to the errors in the input circuit, there are also errors in electronic circuits such as the sample holder 2, but the overall error characteristic of the error output of the adder 10 with respect to the system primary quantity is generally determined by the transformer error characteristic and is a large input. The larger the error.

Therefore, when determining the reference voltage value V _L to be compared with the output of the adder 10, it is necessary to set the reference voltage value V _LH to be greater than the maximum predictable error V _H as shown in FIG. If this is not followed, the following problems will occur. First of all, this error (vector sum of adder output voltages) does not affect the constant monitoring circuit when the power system is normal and the system primary current is maintained within the rated value; If a large current flows as in an accident, an error will occur in the instrument transformers CTA, CTB, and CTC shown in Figure 1, and even if there is no fault in the input circuit of the processing device, the second
At the inputs of the analog converters 9P and 9N in the figure, an error of 〓V〓＞V _L or 〓V〓＜−V _L occurs due to an error in the instrument transformer, which can cause the constant monitoring circuit to operate incorrectly. There is. The output of the constant monitoring circuit is not just a display or alarm, but is sometimes used to block the output of the digital protective relay device, so in this case, a power system fault may not be eliminated due to a malfunction of the digital protective relay device. Become.

Setting the reference voltage V _L high in this way also has the problem that an abnormality occurring in the input circuit IN cannot be detected when the input is small. In other words, for example, under normal operating conditions, the input circuit
Assume that the IN a-phase is disconnected and the a-phase current drops from the rated value I _U to zero. On the other hand, the maximum current in a system fault is 20 to 30 times the rated value I _U , and during A-D conversion, for example, 30 I _U is set as a full scale digital value, so the rated current I _U is the full scale.
It is only 3.3 (%). On the other hand, when the voltage is 30 I _U , the reference voltage value V _LH , which takes into account errors in the transformer, etc., is a value of several percent (for example, 7 to 8 (%)) of the full scale. Therefore, in the rated operating state, the output 〓V〓 of the adder 10 caused by the a-phase disconnection does not exceed its reference value _VL , and therefore, the abnormality monitoring circuit cannot detect an abnormality. And it's not just that it can't be detected, but according to the processing of the digital protective relay SBD logic operation unit CPU, it's 3.3
Since a current change of (%) is sufficient to detect an accident, it means that malfunction cannot be prevented.

The present invention aims to overcome the drawbacks of the conventional method as described above, and by introducing the absolute value sum voltage of the input analog voltages as the reference voltage,
When the power system is normal, the reference voltage will be a small value depending on the size of the power flow, and when a large current is input, the reference voltage will be a large value, regardless of the size of the input voltage. , which attempts to accurately detect circuit abnormalities.

FIG. 6 shows a specific example according to the invention. The same reference numerals as in FIG. 2 indicate the same parts. The components according to the present invention that are different from those in FIG. 2 are the analog inputs I〓 _A ′, I〓 _B ′,
Circuits 11A, 11B, 11C that rectify I〓 _c ′, I〓 _{0 ′}
，
11D, its absolute value sum calculation circuit 12, coefficient circuit 1
6, a polarity converter 14 and a DC reference power source 15. The feature of the present invention is that the output of the coefficient circuit 16 is connected to analog comparators 9P and 9N.
The reference voltage was set as the reference voltage.

The operation of the constant monitoring circuit according to the present invention will be explained below. Analog input V〓 _A ′, V〓 _B ′, V〓 _C ′, V〓 ₀
' is rectified by rectifier circuits 11A, 11B, 11C, and 11D, and its output is sent to DC reference power supply 1 which sets the minimum value of detection sensitivity by absolute value sum calculation circuit 12.
5 is added to the voltage E _S of 5, and its value is proportionally reduced by the coefficient circuit 16, and the reference voltage of the analog comparators 9P and 9N is k _s {〓|V〓|} and −k _s {〓|V 〓｜｝.

On the other hand, the sampled and held analog signals are added by the adder 10, and the output thereof becomes the input signal 〓V〓 of the analog comparators 9P and 9N. When 〓V〓>0, analog comparator 9P
, and when 〓V〓<0, in the analog comparator 9N, 〓V〓−k _s {〓｜V〓
An operation of |}>0 is performed. As is already clear here, when the input is small, such as when there is a constant current, 〓V〓≒0, k _s {〓｜V〓｜}>0, and 〓V〓−k _s
Since {〓|V〓|}<0, comparator 9P,
There is no output of 9N. Each part signal in this state is the 7th
This seems to be before time t ₀ in the figure.

Next, filter 1A becomes abnormal and its output
Let us discuss the case when V〓 _A ′ becomes zero. Due to the abnormality of the filter 1A, the hold signal V〓 _A ' for the a phase of the sample holder 2 input to the adder 10 also becomes zero, and as a result, the analog comparators 9P,
The input voltage 〓V〓 of 9N is 〓V〓=V〓 _A ′+V〓 _B ′+V〓 _C ′−V〓 ₀ ′≒0
What happened is 〓V〓=V〓 _B ′＋V〓 _C ′−V〓 ₀ ′＝〓V〓 _F ≠0
It increases to a certain size.

On the other hand, analog comparators 9P, 9N
_{Another input k s} {〓 _| V〓| ₀ ′｜+
What was E _s decreases to k _s {〓|V〓|｝= |V〓 _B ′|+|V〓 _C ′|+|V〓 ₀ ′|+E _s .

Therefore, the input signal 〓V〓 of analog comparators 9P, 9N and the reference voltage _ks {〓|V〓|}, −k _s {〓|V
〓
_{The relationship between
F}
If is negative, 〓V〓 _F ＜−k _s {〓｜V〓}. That is, the outputs of the analog comparators 9P and 9N become positive, and it is possible to detect an abnormality in the circuit.

FIG. 7 shows an example of the operation of the constant monitoring circuit in the first and second states described above. In the figure,
The difference from the conventional operation example shown in FIG. 3 is that k _s {〓|V〓|} and −k _s {〓|V〓|} are used as reference voltages. In this way, if the power system is normal and there is no abnormality in the input circuit, no output will be generated.
This circuit is no different from the conventional constant monitoring circuit shown in FIG. 3 in that it outputs an output when an abnormality occurs in the input circuit when the power system is normal.

As a third condition, a case will be described in which an accident occurs in the power system and an excessive input is applied to the input circuit. In this case as well, the input voltage V〓 _A ′, V〓 _B ′,
The relationship between V〓 _C ′ and V〓 ₀ ′ should always be 〓V〓＝V〓 _A ′＋V〓 _B ′＋V〓 _C ′−V〓 ₀ ′≒0, but as mentioned earlier, for instruments Due to the error of the transformer, an error of 〓V〓=〓V〓α occurs, and the error becomes 〓V〓=〓V〓α,
V〓α, −〓V〓α are applied. This error at the time of a large current at the time of an accident is quite large, and is a much larger value than the reference voltage k _s {〓|V〓|} before the time t _F of the accident occurrence. However, the reference voltage k _s {〓｜V〓
|｝, −{〓｜V〓} also changes depending on the input voltage,
_{k s {} 〓 | V〓 |
|｝＝
−k _s {〓|V〓α|}, and is added to comparators 9P and 9N. And always −k _s {〓｜V〓α｜｝＜k _s {〓V〓α}＜k _s {〓｜V〓α
The following relationship holds, and the constant monitoring circuit does not operate in the event of an accident.

FIG. 8 shows an example of operating waveforms of the constant monitoring circuit when excessive input is applied. As shown in the figure, if a fault occurs in the power system at time t _F and the input voltage changes significantly, the adder output (error voltage) 〓V〓 also changes to 〓V〓α.
At the same time, the reference voltage k _s {〓|V〓|}, −k _s {〓|V〓
|} also changes to k _s {〓|V〓α|}, −k _s {〓|V〓α|}, so the comparators 9P and 9N do not operate.

Next, the quantitative relationship between them will be explained with reference to FIG. The figure shows the system primary current and absolute value sum calculation circuit 1.
2 shows the relationship between the output voltage k _s {〓|V〓|} of the adder 10 and the output voltage 〓V〓 of the adder 10. Ideally, the relationship between the system primary current and the output voltage 〓V〓 of the adder 10 should be equal to the horizontal axis of the diagram (always zero regardless of 〓V〓), but Due to errors in circuit elements, it is expressed as a curve 〓V〓. This error tends to increase as the analog input voltage increases, and in the conventional method, the reference voltage V _L
was set to a large constant value as shown by the two-dot chain line in the figure to prevent malfunction of the circuit when excessive input is applied. However, according to this, an abnormality in the circuit could not be discovered in a failure mode in which the output voltage value of the sample holder 2, which occurs due to a circuit failure, reaches point P in the figure.

However, if the sum of the absolute values of the input voltages is adopted as the reference voltage as proposed in the present invention, the reference voltage will have a ratio characteristic like the dashed line k _s {〓|V〓|} in the figure. can get. That is, by monitoring according to the relational expression 〓V〓−k _s {〓|V〓|}≧0, it is possible to realize good constant monitoring of the input circuit regardless of the magnitude of the input analog voltage. Note that V ₀ in the present invention is necessary to distinguish between a system fault occurring in the power system and an abnormality in the input circuit. For example, when an accident occurs in the power system, the three-phase balance of input voltages V〓 _A , V〓 _B , and V〓 _C is disrupted, and a voltage with a value of V〓 _A + V〓 _B + V〓 _C = k is generated. If this voltage is used as the constant monitoring target voltage (V), it will be indistinguishable from the voltage that occurs when the three-phase balance is disrupted due to an abnormality in the input circuit. Therefore, by including the zero-sequence voltage V〓 ₀ , which is vector-synthesized from the input voltages V〓 _A , V〓 _B , and V〓 _C , as the target voltage for constant monitoring, failures of the constant monitoring circuit in the event of a system fault can be avoided. Necessary movements can be prevented.

According to the present invention, the function of the monitoring circuit, which was dependent on the magnitude of the input analog voltage, remains unchanged, and malfunctions and malfunctions are prevented, and the operation of the digital protection relay is made fast, stable, and reliable. can be made into something. Furthermore, there is the advantage that failures in the input circuit can be detected early.

Furthermore, the effect of the zero-sequence voltage V ₀ introduced for monitoring is as follows:
As is clear from the above explanation, this is necessary to determine whether there is an abnormality in the power system or an abnormality in the input circuit. Furthermore, although the above example shows an example in which the adder input is supplied from the output side of the sample holder, it is possible to obtain the same effect by calculating the reference voltage by using the signal from the input side of the sample holder instead. It should be obvious.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a configuration example of a digital protective relay device, Figure 2 is a block diagram of a conventional constant monitoring circuit, Figure 3 is its operating waveform diagram, and Figures 4 and 5 are system diagrams. Graph for explaining the error occurrence state of the input circuit with respect to the primary current, No. 6
The figure is a block diagram of one embodiment of the present invention, Figure 7 is an operating waveform diagram of the circuit of Figure 6 when the power system is normal, and Figure 8 is the operation waveform diagram of the circuit of Figure 6 when the power system is abnormal.
FIG. 9 is a graph showing an example of a ratio characteristic curve according to the present invention. V _A ~ V _D ...Analog input, 1A to 1D...Filter, 2...Sample holder, 3...Analog multiplexer, 4...A-D converter, 9P, 9
N...Analog comparator, 10...Adder,
11A to 11D... Rectifier circuit, 12... Absolute value addition circuit.

Claims (1)

[Claims] 1 An instrument transformer that detects the current and voltage of three phases of the power system, a three-phase auxiliary transformer connected to the secondary winding of each phase of the instrument transformer, and a two-phase instrument transformer for each phase of the instrument transformer. A zero-phase auxiliary transformer commonly connected to the next winding, a filter that receives the three-phase and zero-phase auxiliary transformer outputs as input, a sample holder provided after the filter, and digitizing the sample holder output. In a constant monitoring system of an input circuit consisting of an analog-to-digital converter and supplying the output of the analog-to-digital converter to a digital protective relay device,
A first signal corresponding to the three-phase auxiliary transformer output and a second signal corresponding to the zero-phase auxiliary transformer output are extracted from between the filter and the analog-to-digital converter, and a vector sum of the first signals is obtained. a first adder that vectorially subtracts the second signal from and outputs the result;
a second adder that outputs the sum of absolute values of the first signal and the second signal; a coefficient multiplier that multiplies the output of the second adder by a predetermined value; a polarity inversion circuit that inverts the polarity of the output of the coefficient multiplier; a first comparator that applies the first adder output to its positive terminal and a coefficient unit output to its negative terminal; and a second comparator that applies the polarity inversion circuit output to its positive terminal and the first adder output to its negative terminal. configured,
A constant monitoring method for an input circuit that outputs an output when the absolute value of the first adder output is greater than the absolute value of the coefficient unit output to detect an abnormality in the input circuit.