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JPS6326636B2 - - Google Patents
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JPS6326636B2 - - Google Patents

Info

Publication number
JPS6326636B2
JPS6326636B2 JP57098969A JP9896982A JPS6326636B2 JP S6326636 B2 JPS6326636 B2 JP S6326636B2 JP 57098969 A JP57098969 A JP 57098969A JP 9896982 A JP9896982 A JP 9896982A JP S6326636 B2 JPS6326636 B2 JP S6326636B2
Authority
JP
Japan
Prior art keywords
signal
circuit
motor
controlled
edge detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57098969A
Other languages
Japanese (ja)
Other versions
JPS58215991A (en
Inventor
Ryuichiro Iwai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57098969A priority Critical patent/JPS58215991A/en
Publication of JPS58215991A publication Critical patent/JPS58215991A/en
Publication of JPS6326636B2 publication Critical patent/JPS6326636B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02PCONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P7/00Arrangements for regulating or controlling the speed or torque of electric DC motors
    • H02P7/06Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual DC dynamo-electric motor by varying field or armature current

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Control Of Direct Current Motors (AREA)

Description

【発明の詳細な説明】 本発明は周波数発電機を装着した直流モータの
可変速制御装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable speed control device for a DC motor equipped with a frequency generator.

従来、周波数発電機〔以下、FGと称す〕を使
用した可変速制御装置は第1図のように構成され
ている。1は被制御直流モータ7に装着された
FGで、波形整形回路2を介して出力波形を整形
し単安定マルチバイブレータ3と混合器4、積分
器5により周波数/電圧変換して、電力増幅器6
により電力増幅して前記被制御直流モータ7を駆
動するものである。かかる従来の構成で1:10以
上の大きな変速範囲を安定に得るには、単安定マ
ルチバイブレータ3の規定時間と積分器5の積分
時間を速度設定値に連動して動かす必要があつ
て、実際の回路構成、精度、安定性に関して問題
の多いものである。
Conventionally, a variable speed control device using a frequency generator (hereinafter referred to as FG) is configured as shown in FIG. 1 is attached to the controlled DC motor 7
In the FG, the output waveform is shaped via the waveform shaping circuit 2, frequency/voltage converted by the monostable multivibrator 3, mixer 4, and integrator 5, and then sent to the power amplifier 6.
The power is amplified to drive the controlled DC motor 7. In order to stably obtain a large speed change range of 1:10 or more with such a conventional configuration, it is necessary to move the specified time of the monostable multivibrator 3 and the integration time of the integrator 5 in conjunction with the speed setting value. There are many problems with the circuit configuration, accuracy, and stability of the device.

本発明は、回転に同期した信号を発生するFG
を装着した被制御直流モータと、前記FGの信号
を矩形波の整形する波形整形回路と、前記波形整
形回路の矩形波のエツジを検出して第1の信号を
出力するエツジ検出回路と、前記エツジ検出回路
の第1の信号を遅延させて第2の信号を出力する
遅延回路と、前記被制御直流モータの速度設定信
号を積分し、前記遅延回路の第2の信号によりリ
セツトされる積分器と、前記積分器の出力信号を
前記エツジ検出回路の第1の信号によりサンプル
ホールドするサンプルホールド回路と、前記サン
プルホールド回路の出力信号と前記速度設定信号
を加算する加算器とを設け、この加算器の出力を
前記被制御直流モータへの印加電圧信号としたこ
とを特徴とし、負荷トルクによる速度変動分と速
度設定信号で指示される無負荷回転速度とを分け
て、これを加算器で加算して印加電圧信号とする
ため、速度設定信号を変更するだけで低速から高
速に至る広範囲においても安定した可変速制御を
行うことができる効果がある。
The present invention is an FG that generates signals synchronized with rotation.
a controlled DC motor equipped with a controlled DC motor; a waveform shaping circuit that shapes the signal of the FG into a rectangular wave; an edge detection circuit that detects edges of the rectangular wave of the waveform shaping circuit and outputs a first signal; a delay circuit that delays a first signal of the edge detection circuit and outputs a second signal; and an integrator that integrates the speed setting signal of the controlled DC motor and is reset by the second signal of the delay circuit. and a sample hold circuit that samples and holds the output signal of the integrator using the first signal of the edge detection circuit, and an adder that adds the output signal of the sample hold circuit and the speed setting signal. The output of the device is used as a voltage signal applied to the controlled DC motor, and the speed fluctuation due to load torque and the no-load rotation speed specified by the speed setting signal are separated and added by an adder. Since the applied voltage signal is converted into an applied voltage signal, stable variable speed control can be performed even in a wide range from low speed to high speed simply by changing the speed setting signal.

以下本発明の一実施例を第2図と第3図に基づ
いて説明する。なお、第1図と同様のものには同
一符号を付けてその説明を省く。
An embodiment of the present invention will be described below with reference to FIGS. 2 and 3. Components similar to those in FIG. 1 are given the same reference numerals and their explanations will be omitted.

8は波形整形回路2出力信号のエツジを検出す
るエツジ検出回路、9はエツジ検出回路8出力を
遅らせる遅延回路、10は速度設定信号となる可
変直流電源、11はリセツト機能を有する積分
器、12はサンプルホールド回路、13は加算器
である。FG1の出力を波形整形回路2によつて
矩形波A〔第3図参照〕に整形し、エツジ検出回
路8によつて矩形波Aの立上がりと立下がりを検
出して信号Bを得る。次にこの信号Bを遅延回路
9で時間tだけ遅延させて信号Cを得る。積分器
11によつて速度設定信号となる可変直流電源1
0の信号Dを積分し前述の信号Cでリセツトして
積分出力信号Eを得る。信号Eを前述の信号Bに
よつてサンプルしてサンプルホールド回路12に
よつてホールドして出力信号Fを得る。加算器1
3では信号Fと信号Dとが加算されて信号Gが出
力される。被制御直流モータ7は信号Gを電力増
幅器6を介して増幅した信号Gで駆動される。
8 is an edge detection circuit that detects the edge of the output signal of the waveform shaping circuit 2, 9 is a delay circuit that delays the output of the edge detection circuit 8, 10 is a variable DC power supply that serves as a speed setting signal, 11 is an integrator with a reset function, 12 1 is a sample and hold circuit, and 13 is an adder. The output of the FG1 is shaped into a rectangular wave A (see FIG. 3) by a waveform shaping circuit 2, and a signal B is obtained by detecting the rise and fall of the rectangular wave A by an edge detection circuit 8. Next, this signal B is delayed by a time t in a delay circuit 9 to obtain a signal C. Variable DC power supply 1 which becomes a speed setting signal by an integrator 11
A signal D of 0 is integrated and reset with the signal C described above to obtain an integrated output signal E. Signal E is sampled using signal B and held by sample and hold circuit 12 to obtain output signal F. Adder 1
3, signal F and signal D are added and signal G is output. The controlled DC motor 7 is driven by a signal G obtained by amplifying the signal G via a power amplifier 6.

更に前記各部を詳細に説明すると、波形整形回
路2はコンパレータ14とダイオード15、抵抗
器16によつて、エツジ検出回路8は抵抗器17
とコンデンサ18とシユミツト回路19とEx−
OR回路20によつて、遅延回路9は抵抗器21
とコンデンサ22とシユミツト回路23によつ
て、リセツト機能を有する積分器1は抵抗器24
とコンデンサ25とアナログスイツチ26とオペ
アンプ27によつて、サンプルホールド回路12
はバツフアアンプ28とアナログスイツチ29と
コンデンサ30によつて、加算器13はオペアン
プ31と抵抗器32,33,34によつてそれぞ
れ構成されている。電力増幅器6は取扱う電力の
大きさによつてアナログ式あるいはPWMによる
デイジタル式等により構成される。
To further explain each part in detail, the waveform shaping circuit 2 includes a comparator 14, a diode 15, and a resistor 16, and the edge detection circuit 8 includes a resistor 17.
and capacitor 18 and Schmitt circuit 19 and Ex-
The delay circuit 9 is connected to the resistor 21 by the OR circuit 20.
The integrator 1 having a reset function is connected to the resistor 24 by the capacitor 22 and the Schmitt circuit 23.
The sample hold circuit 12 is configured by the capacitor 25, analog switch 26, and operational amplifier 27.
is composed of a buffer amplifier 28, an analog switch 29, and a capacitor 30, and the adder 13 is composed of an operational amplifier 31 and resistors 32, 33, and 34, respectively. The power amplifier 6 is constructed of an analog type, a digital type using PWM, etc. depending on the amount of power to be handled.

第3図に示す第2図の要部波形図は、P点から
Q点にわたつて速度設定信号である信号Dの大き
さを徐々に大きくしたもので、信号Gに相当する
信号Gが被制御直流モータ7に印加されると、回
転速度が上昇し、それにつれてFG1の整形波形
である信号Aの周波数も高くなつていることがわ
かる。また、通常、遅延回路9の遅延時間tは、
動作に支障のない範囲で出来るだけ小さく設定さ
れる。
The main part waveform diagram of FIG. 2 shown in FIG. 3 is a diagram in which the magnitude of signal D, which is the speed setting signal, is gradually increased from point P to point Q, and the signal G corresponding to signal G is It can be seen that when the voltage is applied to the control DC motor 7, the rotational speed increases, and the frequency of the signal A, which is the shaped waveform of FG1, also increases accordingly. Further, normally, the delay time t of the delay circuit 9 is:
It is set as small as possible within a range that does not hinder operation.

直流モータの無負荷回転速度が印加電圧にほぼ
比例するところから、被制御直流モータ7の速度
制御を無負荷回転速度と負荷トルクによる速度変
動分を分けて別々の信号処理を行い、最後に加算
器13により加算して被制御直流モータ7への印
加電圧を得るものであつて、具体的には無負荷時
に被制御直流モータ7の回転が信号Dで指示され
る無負荷回転速度となるよう加算器13の抵抗器
33と34の比率を設定してゲインを調節し、こ
れに速度変動分の信号Fを加算器13で加算して
被制御直流モータ7への印加電圧とするため、速
度設定信号を変更するだけで、広範囲にわたつて
しかも安定して被制御直流モータ7の回転速度を
変更できる。
Since the no-load rotational speed of the DC motor is almost proportional to the applied voltage, the speed control of the controlled DC motor 7 is performed by dividing the no-load rotational speed and the speed variation due to the load torque into separate signal processing, and then adding them together at the end. 13 to obtain the voltage applied to the controlled DC motor 7. Specifically, when there is no load, the rotation of the controlled DC motor 7 is set to the no-load rotation speed indicated by the signal D. The gain is adjusted by setting the ratio between the resistors 33 and 34 of the adder 13, and the adder 13 adds the signal F corresponding to the speed fluctuation to this to obtain the voltage applied to the controlled DC motor 7. By simply changing the setting signal, the rotational speed of the controlled DC motor 7 can be changed stably over a wide range.

以上説明のように本発明によると次のような効
果が得られる。
As explained above, according to the present invention, the following effects can be obtained.

無負荷回転速度と回転変動分を別々に分けて
制御しているため、特に回転変動分の単位回転
数あたりの信号の大きさを大きくとることがで
き、安定な動作が期待できる。
Since the no-load rotational speed and the rotational fluctuation are controlled separately, the magnitude of the signal per unit rotational speed for the rotational fluctuation can be particularly large, and stable operation can be expected.

と同じ理由で低速から高速に至る1:10以
上の広範囲な可変速制御を安定に行うことがで
きる。
For the same reason, it is possible to stably perform variable speed control over a wide range of 1:10 or more from low speed to high speed.

速度設定信号として電圧あるいは電流を直接
に扱うことができ、他の機器よりの信号により
速度設定を行う場合にインターフエースが容易
である。
Voltage or current can be directly handled as a speed setting signal, making it easy to interface when speed setting is performed using signals from other devices.

の理由により低電圧電源での回路構成が容
易でTTL回路と同じ5ボルト単一電源での動
作が可能である。
For this reason, it is easy to configure the circuit with a low voltage power supply, and it is possible to operate with a single 5 volt power supply, the same as a TTL circuit.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の可変速制御装置の構成図、第2
図は本発明による可変速制御装置の一実施例の構
成図、第3図は第2図の要部波形図である。 1……周波数発電機、2……波形整形回路、7
……被制御直流モータ、8……エツジ検出回路、
9……遅延回路、10……可変直流電源、11…
…積分器、12……サンプルホールド回路、13
……加算器、D……速度設定信号。
Figure 1 is a configuration diagram of a conventional variable speed control device;
The figure is a block diagram of one embodiment of the variable speed control device according to the present invention, and FIG. 3 is a waveform diagram of the main part of FIG. 2. 1... Frequency generator, 2... Waveform shaping circuit, 7
...Controlled DC motor, 8...Edge detection circuit,
9...Delay circuit, 10...Variable DC power supply, 11...
...Integrator, 12...Sample and hold circuit, 13
...Adder, D...Speed setting signal.

Claims (1)

【特許請求の範囲】[Claims] 1 回転に同期した信号を発生する周波数発電機
を装着した被制御直流モータと、前記周波数発電
機の信号を矩形波に整形する波形整形回路と、前
記波形整形回路の矩形波のエツジを検出して第1
の信号を出力するエツジ検出回路と、前記エツジ
検出回路の第1の信号を遅延させて第2の信号を
出力する遅延回路と、前記被制御直流モータの速
度設定信号を積分し、前記遅延回路の第2の信号
によりリセツトされる積分器と、前記積分器の出
力信号を前記エツジ検出回路の第1の信号により
サンプルホールドするサンプルホールド回路と、
前記サンプルホールド回路の出力信号と前記速度
設定信号を加算する加算器とを備え、前記加算器
の出力を前記被制御直流モータへの印加電圧信号
とした可変速制御装置。
1. A controlled DC motor equipped with a frequency generator that generates a signal synchronized with rotation, a waveform shaping circuit that shapes the signal of the frequency generator into a rectangular wave, and detecting the edges of the rectangular wave of the waveform shaping circuit. First
an edge detection circuit that outputs a signal, a delay circuit that delays a first signal of the edge detection circuit and outputs a second signal, and a delay circuit that integrates a speed setting signal of the controlled DC motor and outputs a second signal. an integrator that is reset by a second signal of the edge detection circuit; and a sample and hold circuit that samples and holds the output signal of the integrator by the first signal of the edge detection circuit.
A variable speed control device comprising: an adder that adds the output signal of the sample and hold circuit and the speed setting signal, the output of the adder being used as a voltage signal applied to the controlled DC motor.
JP57098969A 1982-06-08 1982-06-08 Variable speed controller Granted JPS58215991A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57098969A JPS58215991A (en) 1982-06-08 1982-06-08 Variable speed controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57098969A JPS58215991A (en) 1982-06-08 1982-06-08 Variable speed controller

Publications (2)

Publication Number Publication Date
JPS58215991A JPS58215991A (en) 1983-12-15
JPS6326636B2 true JPS6326636B2 (en) 1988-05-31

Family

ID=14233877

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57098969A Granted JPS58215991A (en) 1982-06-08 1982-06-08 Variable speed controller

Country Status (1)

Country Link
JP (1) JPS58215991A (en)

Also Published As

Publication number Publication date
JPS58215991A (en) 1983-12-15

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