JPS6331111B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a structure of a silicon gate MOSFET in which a gate is formed of a semiconductor of a type opposite to that of a semiconductor forming a source/drain.

An object of the present invention is to obtain a voltage difference between the threshold voltages of a pair of silicon gate MOSFETs of the same polarity with different gate work functions in accordance with a design value with high accuracy, and to maintain the voltage difference against power supply voltage fluctuations. The objective is to configure the system so that it is stable and stable.

β (β=μWCox/L, where μ, W, L,
When obtaining a pair of same-polarity MOSFETs with equal mobility, channel width, channel length, and capacitance per unit area of gate oxide film, and different threshold voltages V _T , Cox of size
There is a method of realizing a MOSFET by forming gates using polycrystalline silicon having mutually different polarities.

It is assumed that one of the above-mentioned pair of MOSFETs has a gate plate made of P-type polycrystalline silicon and the other made of N-type polycrystalline silicon, and the impurity concentrations thereof are N _A and N _D , respectively. At this time, both
The difference voltage V _D in the threshold voltage of the MOSFET is given as the work function difference between both gate plates, and is expressed by the following equation.

V _D = KT/qlogeN _A・N _D /ni ² (1) where, k is Boltzmann's constant, T is absolute temperature,
q is the unit charge, and ni is the impurity concentration of the intrinsic semiconductor. The voltage V _D obtained by equation (1) can be widely applied as a highly reliable reference voltage.

Next, using Figures 1 to 4, the above
A conventional configuration of a MOSFET pair and a configuration according to the present invention will be explained. Taking the case where the MOSFET is a P-channel transistor as an example, the meanings of each symbol in FIGS. 1 to 4 are as follows.

101,201,301,401...N-type substrate 102,202,302,402...P-type silicon layer 103,203,303,403...Gate oxide film 104,304...N-type polycrystal Silicon 204,404,105,305...P-type polycrystalline silicon 306,406...Process before source/drain formation (e.g., when forming a stopper, when forming a P well)
P-type region formed in.

Generally, when MOSFETs are manufactured using an integrated circuit (hereinafter abbreviated as IC) process, consideration must be given to mask misalignment in advance at the pattern design stage.

Keeping this in mind and considering that MOSFETs are formed in a self-aligned manner, if the source and drain are made of a P-type semiconductor and the gate is made of an N-type semiconductor, the edges on the source side and the drain side of the gate plate should be A P-type region must be provided in the form of a band at the end. Conventionally, this was done using P-type polycrystalline silicon 105
It was realized as shown in Figure 1 so that it overlapped the top of the MOSFET channel. In addition, when forming the source/drain and gate with a P-type semiconductor,
The MOSFET shown in Fig. 1 was realized as shown in Fig. 2 so that the channel length was equal to that of the MOSFET shown in Fig. 1. When a MOSFET pair is realized using this method, N
Type polycrystalline silicon 104, P type polycrystalline silicon 1
Since the work functions of both 05 and 05 are different, the
The difference in threshold value V _D between the MOSFET and the MOSFET shown in Figure 2 cannot be expressed by a simple equation like equation (1);
The reference voltage cannot be obtained as designed. The present invention
This drawback has been eliminated by the method described below.

A MOSFET according to the present invention whose source and drain are P-type semiconductors and whose gate is an N-type semiconductor is formed as shown in FIG. 3 by providing a P-type silicon layer 306 on the channel side of the source and drain. In addition, a MOSFET with a P-type semiconductor gate is paired with this.
is formed as shown in FIG. 4 so that the channel length is equal to that of the MOSFET shown in FIG. FIG. 5 is an example of a pattern diagram for designing the MOSFET shown in FIG.
3 and 504 are boundaries of P-type regions formed on the substrate in a step before forming the source/drain.

Further, 505 is a contact between the gate and the wiring. What should be noted when designing the pattern is that both ends 320 and 321 of the channel in FIG. Inside boundaries 310 and 311 (channel side)
and 320,321
The distance between them should be equal to the distance between 420 and 421 in FIG. 4 (that is, the channel lengths of the MOSFETs in FIG. 3 and MOSFETs in FIG. 4 should be equal). By doing so, β of the paired transistors can be made equal with high precision.

By the way, in the above example, the source and drain are connected to P.
Although the case where the source and drain are formed using an N-type semiconductor has been described, the same thing can be said about the case where the source and drain are formed using an N-type semiconductor. That is, even if the P-type and N-type are reversed in the above example, the invention falls under the present invention.

An example of application of the present invention is shown in FIG. 6a. (This circuit is explained in detail in Japanese Patent Laid-Open No. 53-47953.) In the same figure, 601 is a high-threshold transistor whose gate is made of N-type polycrystalline silicon.
Channel MOSFETs, 602 to 606 are normal
607 is an input terminal, 608 is an output terminal, 609 is a positive power supply, and 610 is a negative power supply. When a signal as shown in FIG. 6B611 is input to 607, the difference voltage between the threshold voltages of 601 and 602 is output during a period 608 when 611 is low. The circuit of FIG. 6 using the present invention is highly effective when applied to a reference power source of a comparator, etc.

Furthermore, the greatest effect of the present invention is that when applied to a reference voltage circuit, the voltage designed based on equation (1) can be obtained with high accuracy, and at the same time, the power supply voltage fluctuation rejection ratio is extremely high. Further, the obtained reference voltage has smaller variations in mass production than those using Zener diodes. Therefore, the present invention can be applied as a reference voltage source for various linear circuits such as A/D converters and D/A converters.

[Brief explanation of drawings]

FIGS. 1 and 2 show a pair of silicon gate MOSFETs with different threshold values according to conventional configurations. Third
The figures and FIG. 4 are according to the configuration of the present invention. A pair of silicon gate MOSFETs with different threshold values. FIG. 5 is an example of a pattern diagram of a silicon gate MOSFET of the present invention. Figures 6a and 6b show an example of application of the present invention.

Claims (1)

[Claims] 1 A substrate of a first conductivity type, a gate oxide film selectively formed on the substrate, a polycrystalline silicon of the first conductivity type formed on a central portion of the gate oxide film, and a gate oxide film formed on the gate oxide film. A gate made of polycrystalline silicon of a second conductivity type formed on an end portion, a second conductivity type silicon layer formed in the substrate on both sides of the gate, and overlapping with a part of the second conductivity type silicon layer. A source/drain region comprising a second conductivity type region formed across the substrate under the second conductivity type polycrystalline silicon and a part of the substrate under the first conductivity type polycrystalline silicon. a second transistor formed on the substrate, having the same polarity and the same channel length as the first transistor, and having a gate made of polycrystalline silicon of a second conductivity type. Device.