JPS6331805B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a disk cache control method used in an information processing system.

Conventionally, magnetic disk devices, magnetic drum devices, and the like have been widely used as external storage devices for electronic computer data, but due to their structure, it is extremely difficult to reduce the access time to less than a few milliseconds. Furthermore, storage devices faster than this are expensive and cannot be used as large-capacity storage means.
Therefore, a disk cache has been announced to compensate for these two drawbacks. This stores the recently accessed data on the magnetic disk in the disk cache, and when that data is subsequently accessed, it accesses the disk cache instead of the magnetic disk, thereby achieving average access. This is an economical way to save time. The access time is determined by whether the data the program is trying to access is in the disk cache (hit rate),
This largely depends on the nature of the program and file.

There are files on a disk that have different structures, such as sequential files and random files, and files that have different uses, such as temporary work files and permanent files. Therefore, by changing the operation of the disk cache according to the structure and use of these files, the performance of the disk cache can be improved. For example, with sequential files, there is a high probability that consecutive areas on the disk will be used sequentially, so it is recommended to increase the load unit from the disk to the disk cache (the amount of data transferred from the disk to the disk cache in the event of a mishit). Therefore, all accesses to the load unit following a miss result in hits, and the hit rate can be improved.
However, in a randomly organized file, the probability that consecutive areas will be used sequentially is low, so if the load unit is made too large, other data that is more frequently used will be evicted from the disk cache due to this load, which will reduce the number of hits. rate decreases.

In an actual system, files with various structures and uses coexist, but since conventional disk caches do not have a function to dynamically switch the operation mode, it is necessary to select a disk cache that is suitable for the individual structure and use of each file. Operation cannot be controlled.

The purpose of the present invention is to provide a high-performance disk cache control system that can dynamically adapt to file structure and usage by setting an operating mode for each storage area of a disk and switching the operating mode for each used area. be.

Next, the present invention will be explained in detail with reference to the drawings. Note that the dotted lines in the figure indicate the flow of control signals, and the solid lines indicate the flow of data.

In FIG. 1 showing a first embodiment of the present invention,
Reference numeral 1 is a channel interface circuit, reference numeral 2 is a small capacity buffer circuit, reference numeral 3 is a device interface circuit, and reference numeral 7 is a cache memory, and data is transferred between these. For example, if a read command indicates that data is on the cache memory, the data is sent from the cache memory 7 via the channel interface circuit 1; if it is not on the cache memory, the data is sent to the disk via the device interface circuit 3. A read command is issued, and the data from the disk is sent to the circuit 3.
The data enters the buffer circuit 2 via the interface circuit 1, and is transferred via the interface circuit 1. The buffer size of the buffer circuit 2 is the same size as the load unit of the cache memory, and transfer from the disk is performed until this buffer size is filled.Transfer from the buffer circuit 2 to the channel is stopped by the transfer end signal from the channel. . When the read data is stored in the cache memory, it is transferred from the buffer circuit 2 to the cache memory 7. These controls are performed by a control memory 4, a firmware read-only memory 6, and a control circuit 5. A directory table for the cache and various control tables are located on the control memory 4, and a mode table for displaying the operating mode for each area of the disk is also located on the control memory 4.

FIG. 2 shows the configuration of the mode table and its access procedure in this embodiment. In the figure, MTP is a mode table pointer located at a fixed address in the control memory 4 and pointing to the start address of the mode table. DN is the device number, SA is the sector address, and the addressing of the disk storage area is DN.
and SA. The operation mode for each area of the disk is determined by the mode table entry MTEI~
It is stored in MTEn and can be pointed to by adding the DN and the upper bits of SA, SAU, to the MTP.

One input/output operation consists of a seek command followed by a read or write command. A device number and a sector address are specified in the seek command, and by using these to read the mode table entry, the operating mode of the read or write command following the seek command is determined. The firmware of the read-only memory has a control routine corresponding to each mode, and the processing corresponding to the mode determined by the above method is realized.

Next, specific examples of operation modes and their effects will be explained.

(1) In the sequential file mode, the reading unit from the disk to the disk cache is normally one block of the cache memory, but in the sequential file mode, the reading unit is several blocks.
This improves the hit rate for files that are accessed sequentially.

(2) Temporary file mode: If a write miss occurs, normally the data is written only to the disk, but in the temporary file mode, the data is written to both the disk and the disk cache. Since there is a high probability that the data of a temporary file (work file) will be read again within a short time after being written, the hit rate can be improved by writing data to the disk cache at the same time.

(3) Bypass mode: This mode bypasses disk cache and does not use cache memory. By applying this to files that have a low probability of being read again once they have been read, it is possible to prevent useless data from displacing other frequently used data and improve the overall hit rate.

(4) High-speed write mode: This mode writes only to the disk cache, does not write to the disk unless it is ejected from the cache, and terminates the write command when the write to the cache memory is completed. This greatly reduces write time and greatly improves performance. However, in this mode, if a failure occurs in the disk cache, it may become unclear up to what point data has been written to the disk, or the data may be lost immediately. Therefore, it is applicable only to files whose data can be easily restored.

In this embodiment, the unit for setting the operation mode is each area specified by the lower bits of the sector address, and has a fixed size. In order to have a strict correspondence between files and modes, the file size must be an integral multiple of the area size. When there are many types of file sizes, it becomes difficult to make exact correspondence between modes and files, but it is safe to allocate files with the same operation mode to consecutive areas, and to avoid areas where the area boundaries and file boundaries do not match. This can be resolved by changing the mode. Note that it is possible to set the upper limit address and lower limit address or file size of each area to make the setting unit of the mode variable length, or it is also possible to set the mode for each disk device.

FIG. 3 is a block diagram showing a second embodiment of the invention. In this system, an input/output processing unit 102, which is a dedicated program-controlled processor, is used for input/output processing. All input/output commands are passed from arithmetic processing units 101 to 102, and the input/output processing unit 102 handles input/output channels. 105 via the input/output device (in this country, the disk controller 10
7 and the disk device 109) to operate them. A channel program necessary to control its operation is prepared in main memory 103. Reference numeral 104 is a disk cache memory, reference numeral 106 is an input/output channel, and reference numeral 108 is a data transfer device. In this system, the functionality for controlling the disk cache is implemented within the input/output processing unit without the need for a special disk controller to control the disk cache. When a read command from the disk is passed from the arithmetic processing unit 101 to the input/output processing unit 102, the function that controls the disk cache operates within the input/output processing unit 102, and the mode table and delay within the input/output processing unit are activated. Processing is performed using a directory table. If the data is in cache memory, the input/output processing unit 102 is connected to the input/output channel 10.
6 from the disk cache memory 104 to the main memory 103 to the data transfer device 108.
Instruct data transfer to. When the data transfer is completed, the data transfer device 108 connects the input/output channel 10
6, the completion report is sent to the input/output control device 102 from the input/output processing device 102 to the arithmetic processing device 10.
1 as the end of reading from the disk. If there is no data in the disk cache memory, the input/output processing unit 102 instructs the data transfer from the disk to the disk cache memory 104 via the channel input/output channel 105, and after that, the data transfer unit 108 instructs the data to be transferred from the disk cache memory 104 to the disk cache memory 104. Instructs the transfer of the main memory 103 from the storage memory 104. The end of this transfer marks the end of the read command. In this system, operation mode determination and processing corresponding to the operation mode are all performed by the input/output processing unit 1.
The only special hardware is a small-scale data transfer device 108 and a disk cache memory.

As described above, the present invention makes it possible to control the disk cache according to the file structure and usage by switching the operation mode of the disk cache for each area on the disk, thereby improving the performance of the disk cache. It has the effect of being able to.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the invention, FIG. 2 is a block diagram showing a partial layout and addressing of the control memory of FIG. 1, and FIG. 3 is a block diagram showing a second embodiment of the invention. FIG. 2 is a block diagram showing an example. In the figure, 1... Channel interface circuit, 2... Buffer circuit, 3... Device interface circuit, 4... Control memory, 5... Control circuit, 6...
Read-only memory, 7...cache memory, 1
0... Channel interface, 11... Device interface, 100... Disk address component, 101... Control memory out, 101... Arithmetic processing unit, 102... Input/output processing unit, 103... Main memory, 104... Cache memory, 105 ，
106...I/O channel, 107...Disk control device, 108...Data transfer device, 109...Disk device.

Claims (1)

[Claims] 1. In a disk cache having a plurality of operation modes, a magnetic disk is divided into a plurality of storage areas, and a storage means for setting and storing an operation mode corresponding to each area, and input/output commands are determined from the contents of the storage means. and means for selecting an operation mode corresponding to a specified storage area of the disk to be used based on the storage area of the disk.