JPS6331816B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for converting a logical address to a real address, and more particularly to an address conversion method for obtaining a real address by referring to an address translation buffer using some bits of a logical address.

FIG. 1 shows an example of an address conversion method in a conventional processing device, and will be described.

When a memory reference request occurs, address bus 1
2, a logical address is set in the logical address register 2. The address translation buffer 5 is referred to by a partial bit group a (address designation bit group) of this logical address, and the registered logical address data c and the registered real address data d are transferred to the registered logical address register 6 and the registered real address data 7. Each is read out.

The address comparison circuit 8 compares the registered logical address data in the register 6 with the bit group b (logical address data bit group) of the logical address in the register 2 excluding the addressing bit group a.

If a match is found, the registered real address data read into the register 7 is the desired real address, and it is set in the memory address register 9 via the address bus 12, and the main memory 11 is referenced.

If there is no match in the above comparison, the first address of the address conversion table in the main memory 11 is transferred from the first address register 1 to the address calculation circuit 3, to the real address register 4, to the registered real address register 7, and to the address bus 12. The data is transferred to the memory address register 9, and the address conversion table is referenced. The data read to the memory data register 10 by this reference is input to the address calculation circuit 3 via the data bus 13. Until the desired real address is calculated and obtained by the address calculation circuit 3, the memory address register 9 is sequentially updated with the output of the address calculation circuit 3, and the address conversion table is sequentially read. When the desired real address is obtained, it is set in register 4. The real address in register 4 is transferred to memory address register 9 via register 7 and address bus 12, and a memory reference request to main memory 11 is executed. In parallel with this, the real address found in the register 4 and the logical address data bit group b of the logical address register 2 are paired and registered in the address designation bit group a in the address translation buffer 5 (address The specified bit group a becomes registered logical address data c, and the real address becomes registered real address data d).

By the way, since the address of the address conversion buffer 5 is specified by part of the bit group a of the logical address, the following problem arises. That is, the addressing bit group a may be the same even though they are in different logical address areas (pages). Therefore, even though the desired real address is registered for an address in the address translation buffer that is referenced in the logical address translation of a certain page, when the logical address of another page that precedes it is translated, the corresponding address is It happens that the contents of the text have been rewritten. If such a case occurs frequently, the usage efficiency of the address translation buffer 5 will decrease, and the number of address translation operations and rewriting of the translation buffer 5 by referring to the address translation table will increase, resulting in an increase in overhead and a decrease in system performance. Come. Specifically, conventionally, when separating a logical address into two, an address translation buffer reference address and an address registered in the address translation buffer, the logical address bit groups were separated in a fixed manner.

For example, logical address bits defined as address translation buffer reference addresses have always been used as reference addresses. For this reason, depending on the system configuration, address translation buffer references and registrations may be concentrated in some address translation buffer columns, making it impossible to improve the efficiency of using the entire address translation buffer.

In order to solve this problem, a method has been adopted in which the address translation buffer is multifaceted, but there is a problem of an increase in the amount of hardware.

Another method is to select some address designating bits from the logical address and designate the address of the address translation buffer by the bit value determined by the exclusive OR of these bits. However, since the processing is performed using an algorithm determined by the hardware connection logic, the address translation overhead may increase depending on the structure of the program, and the overhead cannot be reduced when multiple programs are executed.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an address translation method that can reduce address translation overhead for a wide variety of programs.

However, in the address translation method according to the present invention,
In order to prevent reference registration requests from concentrating on some address translation buffer columns, some of the logical addresses used as reference addresses to address translation buffers can be arbitrarily selected according to the selection information set in the address selection register. did. Specifically, an address selection circuit that selects a logical address bit group into an addressing bit group and a logical address data bit group is provided, an address selection register is provided that provides selection information to this address selection circuit, and a program instruction or panel By setting arbitrary selection information in the address selection register through operation, address selection can be optimized so that address translation overhead is as small as possible for the program to be executed.

FIG. 2 is a block diagram showing an embodiment of the address conversion system according to the present invention, and parts equivalent to those in FIG. 1 are given the same reference numerals.

15 is an address selection circuit which, according to the selection information given from the address selection register 14, distributes the logical address bit groups in the logical address register 2 into an address designation bit group a and a logical address data bit group b. Output. An example of the format of selection information set in the address selection register 14 is shown in FIG. In this example, the selection information is data having the same number of bits as the logical address, and each bit of the address register 14 corresponds to each bit of the logical address register 2.

The address selection circuit 15 outputs the bit group in the logical address register 2 corresponding to the bit group having a bit value of "1" in the address selection register 14 as an address designation bit group a.

Further, a group of bits in the logical address register 2 corresponding to a group of bits whose bit value is "0" in the address selection register 14 is output as a logical address bit group b.

In this way, the address selection circuit 15 divides the bit groups in the logical address register 2 into an address designation bit group a and a logical address bit group b, according to the selection information set in the address selection register 14, and outputs them. do.

An example of an instruction format for setting the address selection register 14 is shown in FIG. This instruction consists of a code OP indicating that it is a register setting instruction, a code I ₂ specifying the address selection register 14, and a setting data section D ₁ . By executing this instruction in the processing device, the selection information of the data portion _D1 of the instruction is set in the address selection register 14 via the data bus 13.

The address selection register 14 may be set by the initial setting when the processing device is powered on, by using the above-mentioned command when switching programs, or by panel operation, but in any case, the address selection buffer 5 The old registration details will become invalid at that point. In this way, since the address translation buffer 5 is addressed by the address designation bit a, if the contents of the address translation register 14 are changed, it is always invalidated.

Now, returning to FIG. 2, the address translation operation will be explained.

When a memory reference request occurs, address bus 1
The logical address is transferred to the logical address register 2 via the logical address register 2. This logical address bit group is divided by the address selection circuit 15 into an address designation bit group a and a logical address data bit group b. Address conversion buffer 5 is referenced by address designation bit group a, and registered logical address data c and registered real address data d are read into registers 6 and 7, respectively. The contents of register 6 and logical address data bit group b are compared by address comparison circuit 8.

If a match is found in this comparison, it means that the target real address has been obtained in the register 7, and this real address is transferred to the memory address register 9 via the address bus 12, and then transferred to the main memory 11.
A memory reference is made to .

If a match cannot be found in the comparison, the contents of the register 7 are not the intended real address, and the real address is determined by referring to the address conversion table in the main memory 11 in the same way as described above, and the address calculation circuit 3 , registers 4 and 7, and address bus 12 to memory address register 9, and memory reference is performed. In parallel with this, the above-determined real address is paired with the logical address data bit group b output from the address selection circuit 15 and converted to the address specified by the address designation bit group a of the address conversion buffer 5. be registered.

The present invention is as described above, and selection information to be set in the address selection register can be arbitrarily set according to the structure of the program to be executed by a program command or panel operation, and multi-program execution can be performed. When switching between programs, arbitrary selection information can be set in the address selection register using a program instruction, which maximizes the efficiency of address conversion buffer usage when executing various programs or multi-programs. address translation overhead can be reduced as much as possible, and system performance can be greatly improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional address translation method, FIG. 2 is a block diagram showing an embodiment of an address translation method according to the present invention, and FIG. 3 is a block diagram showing an example of a conventional address translation method.
FIG. 4 is a diagram showing an example of selection information set in the address selection register in FIG. 2, and FIG. 4 is a diagram showing an example of a setting instruction for the address selection register in FIG. 1... Start address register, 2... Logical address register, 3... Address calculation circuit, 4... Real address register, 5... Address conversion buffer, 6... Registered logical address register, 7... Registered real address register, 8... Address comparison circuit, 9...Memory address register, 10...Memory data register, 1
1... Main memory device, 12... Address bus, 13... Data bus, 14... Address selection register, 15...
Address selection circuit, a... address designation bit group,
b...Logical address data bit group.

Claims (1)

[Scope of Claims] 1. An address conversion buffer in which logical addresses and real addresses are registered in correspondence, and a logical address register in which a logical address bit group consisting of an address designation bit group and a logical address data bit group is set. refers to the address conversion buffer using the address designation bit group, reads the registered logical address data and the registered real address data, compares the registered logical address data and the logical address data bit group, and determines whether they match. If so, the registered real address data is output as the real address data of the logical address, and if they do not match, the real address data is determined and output by referring to the address conversion table, and the obtained real address data is output as the real address data of the logical address. In an address translation method that writes to an address specified by the address designation bit group in the address translation buffer in pair with a data bit group, an address selection register in which arbitrary selection information is set, and an address selection register in which arbitrary selection information is set; An address conversion method comprising: an address selection circuit that divides a group of logical address bits set in the logical address register into a group of address designation bits and a group of logical address data bits.