JPS6331946B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly relates to a semiconductor device characterized by having three-dimensional wiring made possible by forming the main surface of a semiconductor substrate into a three-dimensional structure. .

Conventional methods for taking out the electrodes of semiconductor devices to the outside include metal wire bonding for fine and complex semiconductor devices such as integrated circuits, and pressure contact for high-power semiconductor devices such as thyristors. It was on. For semiconductor elements that have both of these characteristics, that is, semiconductor elements that are minute, complex, and designed for high power use, it is difficult to use conventional connection methods, and a new connection method is required.

Therefore, by using an anisotropic etching method in which the etching rate is extremely different depending on the direction of the crystal, a plane parallel to the main surface of the semiconductor substrate with steps can be obtained, and the main surface of the semiconductor substrate can be formed by pressure contact. If the electrodes are pulled out from the main surface using the method used in conventional integrated circuits such as metal wiring, it is possible to The two sides can be used as high power terminals. The low-power electrodes for control, amplification, etc. can be easily drawn out from the stepped portion created by etching, without being affected by the high-power electrodes drawn from the front and back surfaces of the semiconductor substrate. It can also be applied to the case where a low power electrode is newly provided in an element having a plurality of high power pressure contacts on the main surface of a semiconductor substrate.

Therefore, in the present invention, by performing anisotropic etching several times from the main surface of a semiconductor substrate, a plane parallel to the main surface with steps is provided, and electrodes are taken out from the main surface by pressure bonding. This semiconductor device is characterized in that another electrode is newly taken out from the etched portion.

Specifically, for example, regarding a V-MOSFET, as shown in FIG. 1, a V-groove 6 is formed by anisotropic etching in the center of a semiconductor substrate 1 on which PN junctions 10 and 11 are formed. Furthermore, shallow V-grooves 7 are formed in a wide area B, and these V-
A gate electrode 2 is provided in the trench via an insulating film 3 and taken out to the outside C, and electrodes 4 and 5 are provided on the front and back surfaces D.

That is, in the case of a V-MOSFET, it is necessary to increase the width of the gate portion in order to obtain a large current, and the width of the gate portion of the element must be increased linearly. Therefore, the patterns of semiconductor elements become minute and complicated, and this is where the present semiconductor device becomes necessary.

In the present invention, by using an anisotropic etching method, the etching rate of a plane parallel to the {111} plane is negligible compared to the etching rate of planes parallel to the {100} plane and the {110} plane. Since it is a V-groove, the etching on the sides of the V-groove can be ignored.
By configuring the grooves, the maximum etching depth is determined by the effective length of the portion not covered with the etching-resistant coating, and various three-dimensional structures can be obtained by changing the shape of the etching-resistant coating, etching time, etc. It happens. This makes it possible to obtain a semiconductor device having the above-mentioned three-dimensional structure, that is, a semiconductor device in which the electrode can be taken out from the etched portion even if the electrode is taken out from the main surface of the semiconductor element by pressure contact.

[Brief explanation of the drawing]

1A to 1D are cross-sectional views showing embodiments of the present invention in the order of steps. FIG. 1A shows the V-groove formed by first anisotropic etching,
Figure B is a cross-sectional view of the groove after which anisotropic etching has been performed to make it wider and shallower, Figure 1C is a cross-sectional view of the groove with electrodes provided in the groove, and Figure 1D is a cross-sectional view of the groove with electrodes provided on both sides. In the figure, 1 is a silicon substrate, 2 is a metal electrode, and 3 is a silicon substrate.
is silicon dioxide, 4 and 5 are metal electrodes, 6 and 7 are V-grooves, and 10 and 11 are PN junctions.

Claims (1)

[Claims] 1. A first groove portion provided inside the semiconductor substrate from one principal surface of a semiconductor substrate of one conductivity type and having a plane substantially parallel to the one principal surface at the bottom portion thereof, and the bottom portion of the first groove portion. a second groove provided in a part of the semiconductor substrate, and a region of another conductivity type provided in the semiconductor substrate so as to be exposed on a side surface of the second groove;
an insulating coating provided on the surfaces of the bottoms of the second groove and the first groove; and an insulating coating provided on the insulating coating and located within the second groove and on the bottom of the first groove. a first electrode; a second electrode connected to the one main surface of the semiconductor substrate and provided so as to cover the first and second grooves;
A semiconductor device comprising: a third electrode connected to another main surface opposite to the one main surface of the semiconductor substrate.