JPS6337510B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device whose purpose is to form a three-dimensional structure on the main surface of a semiconductor substrate by performing a plurality of anisotropic etching processes. This relates to a manufacturing method.

Conventionally, as shown in FIG. 1, when obtaining a plurality of ohmic contacts from the main surface of a microscopic semiconductor substrate 108, metal electrodes 104, 105, 106,
A method such as using metals 101, 102, and 103 and melting the ends 109 of the metal wires and connecting them to a semiconductor substrate has been used. Note that here 107 is a silicon dioxide film. However, as the power consumption of minute and complicated semiconductor devices progresses, conventional planar ohmic contacts cannot sufficiently reduce the operating resistance of the semiconductor devices, and there is a limit to how much power can be increased.

Vertical MOS transistor (V-MOSFET) is an element structure that uses three-dimensional ohmic contacts to lower the operating resistance of semiconductor elements and achieve high power output.
is proposed. In conventional V-MOSFETs, a simple V-groove is formed in a semiconductor substrate, and a gate electrode is formed on the surface of this V-groove with an insulating film interposed therebetween. However, since it is not possible to attach a metal wire to the inclined portion of the V-groove, the gate electrode has been led out to the surface of the semiconductor substrate and the metal wire has been attached to the surface of the semiconductor substrate. Therefore, with such a simple V-groove, the complexity of electrode arrangement on the surface of the semiconductor substrate cannot be changed, and element miniaturization cannot be achieved sufficiently.

According to the present invention, a first V-shaped groove is formed by first anisotropic etching on the main surface of a semiconductor substrate having a main surface parallel to a (100) crystal plane, and then this first groove is A method for manufacturing a semiconductor device, in which a second groove shallower than the first groove is formed by second anisotropic etching in a wider area than the surface area, thereby obtaining a two-stage V-groove having a flat part in the middle. get.

According to the present invention, there is a flat part in the middle.
A step-structured V-groove can be easily obtained by two times of anisotropic etching. Furthermore, since the V-groove with the two-stage structure has a flat part in the middle, even if a metal electrode is attached to the V-groove with the two-stage structure, a metal wire can be attached at the flat part in the middle. Therefore, both the surface and the V-groove can be effectively used, the electrodes on the semiconductor substrate can be arranged three-dimensionally, the electrodes can be brought close to each other without shorting, and the device can be miniaturized.

In addition, by using an anisotropic etching method to create a three-dimensional structure on the main surface of the semiconductor substrate,
Various methods can be used for connection to external electrodes in addition to metal wire connection. For example, the external lead can be connected to the metal electrode on the main surface by pressure welding, and at this time, the portion inside the V-groove is not affected by the pressure welding.

Next, the present invention will be explained in more detail with reference to the drawings.

In FIG. 2, a pressure contact electrode 205 is pressure-connected to the main surface of a silicon substrate 204, and is provided via silicon dioxide 203 on the surface of a two-stage V-groove formed by two times of anisotropic etching. The metal wire 201 is connected only to the metal electrode 202 by melting its end. One method of anisotropic etching is
A mixture of KOH aqueous solution and isopropyl alcohol is used. As is well known, for example, if a semiconductor substrate whose principal plane is parallel to the (100) plane is used, the etching rate for the (100) plane will be lower than the etching rate for the plane parallel to the {111} plane. Since the etching is extremely fast, the portions not covered with the etching-resistant film are etched with an inclination in the direction of the {111} plane, so that a V-shaped groove is finally formed. Then, by performing anisotropic etching over a wider area and in a shorter time on the V-shaped groove formed by the first anisotropic etching, the etching speed is faster on the surface than on the side surface of the groove, resulting in a large V-shaped groove. The mold grooves are formed halfway. As a result, ideally, a plane 302 parallel to the surface is created in the middle of the large V-shaped groove 301, as shown in FIG. 3, and one electrode can be provided there. Furthermore, the V-groove formed by the first anisotropic etching can maintain its shape until the second anisotropic etching progresses from the surface.

Anisotropic etching is also advantageous because side etching on the portion covered with the etch-resistant coating is almost negligible and the etching depth can be reliably controlled.

By providing a step on the main surface of the semiconductor substrate in this way, it is possible to increase the surface area of the semiconductor device and widen the distance between the electrodes. A flat surface can be obtained, and a plurality of electrodes of a vertical semiconductor device can be easily drawn out.

An embodiment of the present invention is an n-channel V-
Regarding MOSFETs, as shown in FIG. 4A, a semiconductor substrate, that is, a silicon substrate, has a semiconductor layer, for example, a p-layer 402, formed by a diffusion method on an n-type silicon substrate 401 whose main surface is parallel to the (100) plane. form. Next, an n-layer 403 is provided on the p-layer 402 by a diffusion method (FIG. 4B), and a first anisotropic etching is performed by covering the portions that are not to be etched with an etching-resistant film (FIG. 4C).
At this time, the measurement surface 404 of the V groove is a surface parallel to the {111} plane. Then, a second anisotropic etching is performed over a wide area for a short time, and the parallel surface 40
6 (Figure 4D). At this time, the side surface 4 of the V groove
05 is a plane parallel to the {111} plane, and the plane 406
is a plane parallel to the (100) plane. Next, a silicon dioxide film 407 is provided in the V-groove obtained by the first anisotropic etching, and aluminum, for example, is vapor-deposited as a gate electrode 408. Further, the source electrode 409 is pressed into contact (FIG. 4E).

As described above, by using the bottom surface of the semiconductor substrate as the drain electrode, a vertical n-channel VMOSFET is completed.

The advantage of the present invention is that the side etching caused by anisotropic etching is negligible compared to conventional etching methods, and once the dimensions of the portion not covered by the etching-resistant film are known, the limit of the etching depth can be easily determined. By knowing the etching rate depending on the crystal direction, the etching depth can be easily controlled. In addition, by using the anisotropic etching method multiple times, it is possible to make the electrodes on the semiconductor substrate three-dimensional, and to obtain the electrodes using pressure contact, which makes it possible to make the semiconductor substrate into a three-dimensional structure. In addition, it becomes possible to make the electrodes of the semiconductor substrate three-dimensional and to obtain the electrodes by pressure contact.

Although V-MOSFET has been mainly described here, it can be expected that there will be various application fields by forming the main surface of the semiconductor substrate into a three-dimensional structure by performing the anisotropic etching method multiple times.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the wiring of a conventional semiconductor, in the case of a V-MOSFET. FIG. 2 is a sectional view of a semiconductor device obtained according to one embodiment of the present invention, and FIG. 3 is a perspective view including a partial cross section showing the results of the anisotropic etching method of the present invention. FIGS. 4A to 4E are cross-sectional views showing the manufacturing process of a V-MOSFET, which is one embodiment of the present invention, in the order of steps. In addition, in the figure, 101, 102, 103 are metal wires,
104, 105, 106 are metal electrodes, 107 is a silicon dioxide film, 108 is a silicon substrate, 201
is a metal wire, 202 is a metal electrode, 301 is a groove, 30
2 is a plane part, 203 is a silicon dioxide film, 204
is a silicon substrate, 205 is a pressure contact electrode, 401 is n
type silicon substrate, 402 is a p-type diffusion layer, 403 is an n-type diffusion layer, 404 and 405 are planes parallel to the {111} plane, 406 is a plane parallel to the (1000) plane, 407 is a silicon dioxide film, and 408 is a metal The electrode 409 is a pressure contact electrode.

Claims (1)

[Claims] 1. The first layer from the main surface parallel to the (100) crystal plane of a semiconductor substrate of another conductivity type that has a layer of one conductivity type inside.
forming a V-groove penetrating the one conductivity type layer by anisotropic etching; etching a peripheral portion of the V-groove from the main surface to a depth shallower than the V-groove by a second anisotropic etching process; A step of forming a stepped V-groove having a flat part in the middle of the V-groove, a step of forming an insulating film on the surface of the flat part of the stepped groove and a part deeper than the flat part, and a surface of the insulating film. 1. A method of manufacturing a semiconductor device, comprising the steps of: forming a metal electrode on the flat portion; and connecting a thin metal wire to a portion of the metal electrode on the flat portion.