JPS6332310B2 - - Google Patents
Info
- Publication number
- JPS6332310B2 JPS6332310B2 JP56163794A JP16379481A JPS6332310B2 JP S6332310 B2 JPS6332310 B2 JP S6332310B2 JP 56163794 A JP56163794 A JP 56163794A JP 16379481 A JP16379481 A JP 16379481A JP S6332310 B2 JPS6332310 B2 JP S6332310B2
- Authority
- JP
- Japan
- Prior art keywords
- storage device
- audible
- control information
- signal tone
- intermittent control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q1/00—Details of selecting apparatus or arrangements
- H04Q1/18—Electrical details
- H04Q1/30—Signalling arrangements; Manipulation of signalling currents
- H04Q1/44—Signalling arrangements; Manipulation of signalling currents using alternate current
- H04Q1/444—Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies
- H04Q1/45—Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling
- H04Q1/457—Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling with conversion of multifrequency signals into digital signals
- H04Q1/4575—Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling with conversion of multifrequency signals into digital signals which are transmitted in digital form
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Devices For Supply Of Signal Current (AREA)
Description
【発明の詳細な説明】
本発明は自動交換機のデイジタル可聴音発生回
路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital audible tone generation circuit for an automatic switchboard.
従来のデイジタル可聴音発生回路では、可聴音
の断続間隔は固定されており、また断続間隔と可
聴音の組合せも各タイムスロツトに対して一意に
定まつており融通性に欠けるものであつた。 In conventional digital audible sound generation circuits, the intermittent interval of the audible sound is fixed, and the combination of the intermittent interval and the audible sound is also uniquely determined for each time slot, lacking flexibility.
本発明の目的は、上記欠点を除き、書き換え可
能な記憶装置を設けることにより、任意のタイム
スロツトにおいて任意の可聴音を任意の断続間隔
で発生することを可能とした融通性のあるデイジ
タル可聴音発生回路を提供することにある。 An object of the present invention is to eliminate the above-mentioned drawbacks and provide a flexible digital audible sound that can generate any audible sound at any time slot and at any intermittent interval by providing a rewritable storage device. The purpose of this invention is to provide a generating circuit.
本発明によるデイジタル可聴音発生回路は、可
聴信号音がデイジタル時分割多重されて通話路に
供給される自動交換機において、可聴信号音を構
成するに必要な連続信号音を少くとも１種類以上
デイジタル符号化された形で記憶している第１の
記憶装置（以下、可聴音メモリと称す）、前記可
聴音メモリから読み出される連続信号音の断続制
御情報を少くとも１種類以上記憶する第２の記憶
装置（以下、断続情報メモリと称す）、前記連続
信号音と前記断続制御情報との組合せ選択情報
を、可聴信号音を時分割多重するタイムスロツト
番号に対応する番地に記憶する第３の記憶装置
（以下、組合せ選択情報メモリと称す）を設け、
可聴信号音を時分割多重する該タイムスロツト毎
に、前記組合せ選択情報メモリにより選択される
前記可聴音メモリの連続信号音と前記断続情報メ
モリの断続制御情報とを読み出し、該２情報を組
合せることにより所要の可聴信号音を発生するよ
うにしたものである。前記第１、第２、第３の記
憶装置は、記憶する情報を任意に設定することが
可能であり、かつ、再設定が可能であるので融通
性のあるデイジタル可聴音発生回路を構成するこ
とができる。 The digital audible tone generating circuit according to the present invention is capable of converting at least one kind of continuous signal tone necessary to form an audible signal tone into a digital code in an automatic switching system in which audible signal tones are digitally time-division multiplexed and supplied to a telephone line. a first storage device (hereinafter referred to as an audible sound memory) that stores the information in an encoded format; a second storage device that stores at least one type of intermittent control information for the continuous signal sound read from the audible sound memory; a third storage device (hereinafter referred to as an intermittent information memory) that stores combination selection information of the continuous signal tone and the intermittent control information at an address corresponding to a time slot number for time-division multiplexing of the audible signal tone; (hereinafter referred to as combination selection information memory) is provided,
For each time slot in which audible signal tones are time-division multiplexed, the continuous signal tone from the audible sound memory selected by the combination selection information memory and the intermittent control information from the intermittent information memory are read out, and the two pieces of information are combined. By doing so, the required audible signal tone is generated. The first, second, and third storage devices can configure a flexible digital audible sound generation circuit because the information to be stored can be arbitrarily set and can be reset. Can be done.
次に本発明の実施例を図面を用いて説明する。 Next, embodiments of the present invention will be described using the drawings.
図面は、本発明の一実施例であり、（ｎ＋１）
種類の連続信号音と（ｍ＋１）種類の断続制御情
報を記憶し、並列８ビツトの可聴信号音を発生す
るデイジタル可聴音発生回路を示した図である。
この図において、クロツク発生回路１０よりクロ
ツクを受け、カウンタ回路２０が動作することに
より、可聴音メモリ４０より（ｎ＋１）種類の連
続信号音が読出され、クロツク発生回路１０から
のクロツクに同期してバツフアレジスタ７０〜７
ｎに一時記憶される。また断続情報メモリ５０も
カウンタ回路２０により読み出され、（ｍ＋１）
種類の断続制御情報が信号線２００〜２０ｍに出
力される。一方、組合せ選択情報メモリ６０はタ
イムスロツト番号指定回路３０の出力により読み
出され、連続音選択信号を信号線３００に、断続
制御情報選択信号を信号線４００にそれぞれ出力
する。連続音選択回路９０〜９７は信号線３００
より連続音選択信号を受けて（ｎ＋１）種類の連
続信号音のうちから１つを選択して出力し、断続
制御情報選択回路８０は、信号線４００より断続
制御情報選択信号を受け、信号線２００〜２０ｍ
より入力する断続制御情報のうちから１つを選択
して出力する。連続音断続回路１００〜１０７で
は連続音選択回路９０〜９７より入力する連続信
号音を断続制御情報選択回路８０より受けた断続
制御情報により断続して出力する。 The drawing shows one embodiment of the present invention, and (n+1)
FIG. 2 is a diagram showing a digital audible sound generation circuit that stores types of continuous signal tones and (m+1) types of intermittent control information and generates parallel 8-bit audible signal tones.
In this figure, by receiving the clock from the clock generation circuit 10 and operating the counter circuit 20, (n+1) types of continuous signal tones are read out from the audible sound memory 40, and in synchronization with the clock from the clock generation circuit 10. Buffer register 70-7
Temporarily stored in n. The intermittent information memory 50 is also read out by the counter circuit 20, and (m+1)
The types of intermittent control information are output to signal lines 200 to 20m. On the other hand, the combination selection information memory 60 is read out by the output of the time slot number designation circuit 30, and outputs a continuous tone selection signal to the signal line 300 and an intermittent control information selection signal to the signal line 400, respectively. Continuous sound selection circuits 90 to 97 are connected to signal line 300
The intermittent control information selection circuit 80 receives an intermittent control information selection signal from the signal line 400 and selects and outputs one out of (n+1) types of continuous signal tones. 200-20m
One of the input intermittent control information is selected and output. The continuous sound intermittent circuits 100 to 107 output continuous signal sounds input from the continuous sound selection circuits 90 to 97 intermittently based on the intermittent control information received from the intermittent control information selection circuit 80.
以上の動作が可聴信号音を時分割多重する各タ
イムスロツトにおいて行われる。 The above operations are performed in each time slot in which the audible signal tone is time-division multiplexed.
以上の説明により明らかなように第１、第２、
第３の記憶装置の情報を任意に設定可能とするこ
とにより、任意のタイムスロツトにおいて任意の
可聴音を任意の断続間隔で発生することができ、
融通性のあるデイジタル可聴音発生回路が得られ
る。 As is clear from the above explanation, the first, second,
By making it possible to arbitrarily set the information in the third storage device, any audible sound can be generated at any intermittent interval in any time slot,
A flexible digital audible sound generation circuit is obtained.
図面は本発明の一実施例に係るデイジタル可聴
音発生回路を示した図である。
１０……クロツク発生回路、２０……カウンタ
回路、３０……タイムスロツト番号指定回路、４
０……可聴音メモリ（第１の記憶装置）、５０…
…断続情報メモリ（第２の記憶装置）、６０……
組合せ選択情報メモリ（第３の記憶装置）、７０
〜７ｎ……バツフアレジスタ、８０……断続制御
情報選択回路、９０〜９７……連続音選択回路、
１００〜１０７……連続信号音断続回路。
The drawing is a diagram showing a digital audible sound generation circuit according to an embodiment of the present invention. 10...Clock generation circuit, 20...Counter circuit, 30...Time slot number designation circuit, 4
0... Audible sound memory (first storage device), 50...
...Intermittent information memory (second storage device), 60...
Combination selection information memory (third storage device), 70
~7n...Buffer register, 80...Intermittent control information selection circuit, 90-97...Continuous sound selection circuit,
100 to 107... Continuous signal tone intermittent circuit.
Claims (1)
話路に供給される自動交換機において、前記可聴
信号音を構成するに必要な連続信号音を少くとも
２種類以上デイジタル符号化された形で記憶して
いる第１の記憶装置と、前記第１の記憶装置から
読み出される連続信号音の断続制御情報を少くと
も２種類以上記憶する第２の記憶装置と、前記連
続信号音と前記断続制御情報の組合せ選択情報
を、前記可聴信号音を時分割多重するタイムスロ
ツト番号に対応する番地に記憶する第３の記憶装
置とを設け、前記可聴信号音を時分割多重するタ
イムスロツト毎に前記第３の記憶装置により選択
される前記第１の記憶装置の連続信号音と前記第
２の記憶装置の断続制御情報とを読み出し、該２
情報を組み合わせることにより所要の可聴信号音
を発生することを特徴とするデイジタル可聴音発
生回路。1. In an automatic switching system in which audible signal tones are digitally time-division multiplexed and supplied to a communication path, at least two types of continuous signal tones necessary to constitute the audible signal tone are stored in digitally encoded form. a first storage device that stores at least two types of intermittent control information for the continuous signal tone read from the first storage device; and a combination of the continuous signal tone and the intermittent control information. a third storage device that stores selection information at an address corresponding to a time slot number for time-division multiplexing the audible signal tone, and storing selection information for each time slot for time-division multiplexing the audible signal tone; reading the continuous signal tone of the first storage device selected by the device and the intermittent control information of the second storage device;
A digital audible sound generation circuit characterized in that it generates a required audible signal sound by combining information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16379481A JPS5864862A (en) | 1981-10-14 | 1981-10-14 | Digital audible tone generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16379481A JPS5864862A (en) | 1981-10-14 | 1981-10-14 | Digital audible tone generating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5864862A JPS5864862A (en) | 1983-04-18 |
| JPS6332310B2 true JPS6332310B2 (en) | 1988-06-29 |
Family
ID=15780822
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16379481A Granted JPS5864862A (en) | 1981-10-14 | 1981-10-14 | Digital audible tone generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5864862A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6068761A (en) * | 1983-09-26 | 1985-04-19 | Oki Electric Ind Co Ltd | Digital signal oscillator |
| JPS61107260U (en) * | 1984-12-17 | 1986-07-08 | ||
| JPS62126759A (en) * | 1985-11-27 | 1987-06-09 | Nec Corp | Digital audible sound generation circuit |
| JPS62222763A (en) * | 1986-03-20 | 1987-09-30 | Fujitsu Ltd | Tone transmission system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51111324A (en) * | 1975-03-26 | 1976-10-01 | Nec Corp | Reserved sound generating apparatus |
-
1981
- 1981-10-14 JP JP16379481A patent/JPS5864862A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5864862A (en) | 1983-04-18 |
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