JPS633400B2 - - Google Patents

Description

[Detailed description of the invention]

(1) Technical Field of the Invention The present invention relates to a programmable element, and in particular to a programmable element that does not receive a bit address signal and is equipped with at least two bit strings for test cells so that a functional test can be effectively performed before writing. The present invention relates to field programmable devices such as read-only memory (ROM), programmable read-only memory (PROM), and field programmable logic array (FPLA). (2) Background of the Invention In field programmable devices such as PROM and ROM, all memory cells are in a blank state of 1 or 0 before writing, so even if one or more of the peripheral circuits of the memory cell array is damaged, The read contents are all the same, and even if the peripheral circuit is normal, abnormal, or abnormal, it is impossible to determine which part is abnormal. Therefore, in the memory cell group, a test cell bit string and a test cell word string are provided separately from the real cells, and 1010...
By writing a predetermined test pattern such as
Abnormalities can be tested before shipping (Special application
53-145829). By the way, in a normal programmable element, a bit decoder and a multiplexer select one real cell or test cell bit string from a plurality of bit strings, and send the signal of the selected bit string to an output circuit. However, with a small-capacity programmable element, a bit decoder and multiplexer are not necessarily required, and one real cell bit string is made to correspond to one output circuit, and the bit string is read out by a chip enable signal. There is also known a type in which the signal of the selected bit string is read out to the corresponding output circuit by selecting the bit string. In this way, in a small-capacity programmable element that does not have a bit decoder or multiplexer, and therefore does not have a Y address, in order to provide a test cell bit string and make it possible to select it, it is necessary to create a test cell bit string. Alternatively, it is conceivable to provide a special terminal for selecting a real cell bit string, but adding a special terminal to the package goes against the demand for smaller capacity and is not practical. Therefore, a method is known in which a chip enable terminal, which is also present in a small-capacity programmable element, is used as a terminal for selecting a test cell bit string or a real cell bit string. However, depending on the memory configuration, a plurality of chip enable terminals may not always be provided. Even when there is only one chip enable terminal, there is a need for a programmable device that can provide a plurality of bit strings for test cells and sufficiently test peripheral circuits. (3) Prior art and problems Conventionally, a programmable device without a bit decoder or multiplexer and with only one chip enable terminal could only be provided with one bit string for a test cell, and the peripheral circuit It was not possible to conduct sufficient tests. This will be explained with reference to FIG. FIG. 1 is a circuit diagram showing part of a conventional programmable read-only memory (PROM). In the figure, the PROM includes an input voltage discrimination circuit 1, a selection circuit 2, a word decoder circuit 3, and an output circuit 4. Input voltage discrimination circuit 1
The voltage V _CE applied to the voltage input to the chip enable terminal of the TTL circuit is lower than the threshold voltage of approximately 1.5V, and V ₁ is higher than 1.5V.
Voltage lower than approximately 5.5V, which is the allowable voltage for TTL circuits
If we consider the voltage V ₂ and the voltage V ₃ higher than about 6V, which is the threshold voltage of the Zener diode 11, the NAND gate 12, the NOT gate 13,
The logic level of the outputs D ₁ , D ₂ , and D ₃ of the NOT gate 14, the selected/unselected states of the test cell bit string TB and the real cell bit string RB, and the above voltages.
The relationship with V _CE is shown in Table 1 below.

[Table] In other words, when the voltage applied to the chip enable terminal is V ₁ , the level of D ₁ is high level.
(H), and the transistors 41 to 4 in the output circuit 4
Since H level voltage is applied to the base of 4,
Since the chip is enabled and D ₂ is H, the transistor 21 in the selection circuit 2 can be turned on in response to the high level of RB, and the real cell bit string RB and the word lines WL ₁ , WL ₂ , . . . The storage information of the memory cell MC at the intersection with one word line is given to the base of the transistor 44 in the output circuit 4, and the output terminal O
H or L is obtained. Furthermore, when V _CE is V ₂ , D ₁ becomes L, transistors 43 and 44 in the output circuit 4 are both turned off, and the output terminal O
goes into a high impedance state, which is the disabled state of the chip. Furthermore, V _CE is V ₃
In this case, the chip becomes enabled again, the transistor 22 in the selection circuit 2 can be turned on in response to the high level of TB, and the test cell bit string TB is selected. In the conventional circuit shown in FIG. 1, only one test cell bit string can be included in one chip.
Even if a test pattern is written into the memory cell of the actual test cell bit string, peripheral circuits such as the word decoder circuit 3 and the output circuit 4 cannot be sufficiently tested. (4) Purpose of the Invention Therefore, the purpose of the present invention is to detect a voltage for selecting a bit string for a test cell in an input voltage discriminating circuit in at least three stages. In a small-capacity programmable element that has terminals but does not have a bit decoder circuit or multiplexer, it is possible to arrange at least two bit strings for test cells on one chip, thereby ensuring the testing of peripheral circuits of memory cells. The goal is to make it possible. (5) Structure of the invention The gist of the present invention to achieve the above object is as follows:
One chip enable terminal, multiple word strings,
At least one real cell bit string intersects with the word string, at least two test cell bit strings intersect with the word string, the signal voltage input to the chip enable terminal is in a low voltage range, a medium voltage range, and an input voltage discrimination circuit for determining which of at least three voltage ranges in the high voltage range it belongs to, and when the input voltage discrimination circuit determines that the input signal voltage belongs to the low voltage range, the bit string for the real cell is determined. is selected, and when it is determined that the input signal voltage belongs to the medium voltage range, one of the bit strings for the test cell is selected, and when it is determined that the input signal voltage belongs to the high voltage range, the bit string for the test cell is selected. a selection circuit that selects one of the other bit strings for
and an output circuit that outputs a signal of the bit string selected by the selection circuit. (6) Examples of the invention Examples of the invention will be described below. FIG. 2 is a block diagram schematically showing a PROM according to the present invention. In this figure and the following drawings, elements that are the same as those in FIG. 1 are designated by the same reference numerals, and corresponding elements are designated by the same numerals with a to d appended to them. In the present invention, the input voltage discrimination circuit 1a and the selection circuit 2a are devised so that one output circuit 4 has at least two
The test cell bit strings TB ₁ and TB ₂ can now be connected. Word decoder circuit 3 and output circuit 4
The configuration is the same as that of the conventional example shown in FIG. FIG. 3 is a circuit diagram showing a portion of a PROM according to an embodiment of the present invention. In the figure, the input voltage discrimination circuit 1b includes a Zener diode 11,
NAND gate 12, NOT gate 13 and 14
In addition to Zener diodes 15 and 16,
It further includes NOT gates 17 and 18.
The cathodes of Zener diodes 11 and 15 and the first input of NAND gate 12 are connected to the chip enable terminal, and the anode of Zener diode 11 is grounded via resistor R ₁ and NOT gates 13 and 14 are connected to the chip enable terminal. via one output D _3b of the half-circuit 1b. Zener diodes 15 and 16 are connected in series, and Zener diode 16
The anode of is grounded via a resistor R ₁ and connected via NOT gates 17 and 18 to the other output D _5b of the discrimination circuit 1b.
The output of the NOT gate 13 is also connected to yet another output D _2b of the discrimination circuit 1b,
The output of the gate 17 is connected to yet another output D _4b of the discrimination circuit 1b. NAND gate 12
The output of is another output D _1b of the discrimination circuit 1b.
It is connected to the. The selection circuit 2b includes transistors 21-23, diodes 24-31, and resistors 32-34. The outputs D _2b , D _3b , D _4b of the discrimination circuit 1b, and
_D5b is connected to the bases of diodes 24 to 28 and transistors 22, 21, 22, and 23, respectively. Output D _2b is also connected to the base of transistor 23 via diode 26 . The collectors of transistors 21 to 23 are power lines
They are commonly connected to V _CC , and their emitters are connected to the first input of the output circuit 4 . transistor 2
1 is also connected via diode 31 to the first
is connected to the test cell bit string _TB1 .
The base of the transistor 23 is connected via a diode 30 to the second test cell bit string _TB2 . The base of the transistor 21 is connected to the real cell bit string RB via a diode 31. Output D _1b of discrimination circuit 1b is output circuit 4
is connected to the second input of the. transistor 21
23 are also connected to the power supply line V _CC via resistors 34, 32, and 33, respectively. In FIG. 3, the voltage V _CE input to the chip enable terminal and the output D _1b of the discrimination circuit 1b,
The relationship between D _2b , D _3b , D _4b , D _5b and the test cell bit strings TB ₁ , TB ₂ and the real cell bit string RB is shown in Table 2 below.

[Table] In other words, the voltage at the chip enable terminal V _CE
When is V ₁ , D _1b is at H level, so the output circuit 4 is enabled, and D _2b and D _4b are at H level, so diodes 24 and 27 are cut off, and resistor 3 is connected to the base of transistor 22.
A base current is input via 2. Therefore RB
The upper memory information is transistor 22, output circuit 4
It is output to output terminal O through . On the other hand, since D _5b is L, the diode 26 is in the on state, and the second
Since the current on the test cell bit string _TB2 is not applied to the transistor 23 and flows through the diode 26, _TB2 is in a non-selected state. Similarly,
Since _D3b is at L level, the diode 25 is on, and the transistor 21 is always off because no base current is supplied, so the first test cell bit string _TB1 is also in a non-selected state. When V _CE is V ₂ , D _1b is at L level, so the first
As in the case shown, the output circuit is disabled. When V _CE is V ₃ , D _3b is at H level, so diode 25 is turned off, and the first test cell bit string TB ₁ is selected, and D _2b and D _5b are at L level, so diodes 24, 26, 28 are turned off. is turned on,
RB and TB ₂ will be deselected. When V _CE is a voltage V ₄ of 12 V or more, D _5b is at H level, so the diode 26 is turned off, the second test cell bit string TB ₂ is selected, and D _2b , D _4b
is at L level, so diodes 24, 27, 28
is turned on and TB ₁ and RB are deselected. Thus, in the first embodiment shown in FIG.
Two bit strings for test cells in one output circuit 4
TB ₁ and TB ₂ can be connected. It may be necessary to apply not only voltages V ₃ and V ₄ for selecting bit strings for test cells, but also a program control signal to the chip enable terminal. When applying a program control signal to the chip enable terminal, the output circuit must be in a high impedance state. FIG. 4 is a circuit diagram showing a part of a PROM to which a program control signal can be applied according to a second embodiment of the present invention. 4 differs from FIG. 3 in that the input voltage discrimination circuit 1c further includes Zener diodes 35, 36 and 37 and an ENOR gate 38. Zener diodes 35 to 37 are connected in series, and the anode of Zener diode 35 is the chip enable terminal.
At CE, the cathode of 37 is connected to ground through resistor R ₃ and to the first input of ENOR gate 38 . The output of ENOR gate 38 is
It is connected to the second input of NAND gate 12 and the input of NOT gate 13. The cathode of Zener diode 11 is connected to the second input of ENOR gate 38. The configuration of selection circuit 2c is substantially the same as selection circuit 2b in FIG. 3. In FIG. 4, the relationship between V _CE , the input/output level of the ENOR gate 38, the input/output level of the NAND gate 12, and the states of TB ₁ , TB ₂ , and RB is shown in Table 3 below.

[Table] As is clear from Table 3 above, V _CE is V ₂ and V ₅
At this time, the output of the NAND gate 12 is at L level, and the output circuit 4 is disabled.
RB when V _CE is V ₁ , TB ₁ when V ₃ , and
The fact that TB ₂ is selected when V ₄ is the same as in the case of the first embodiment shown in FIG. 3 is the case. In the embodiments shown in FIGS. 3 and 4, two test cell bit strings are connected to one output circuit, but since this test cell bit string is added, the selection circuit 2C in FIG. As shown in FIG. 2, a parasitic capacitance C is added to the base of the transistor, which causes a reduction in the switching speed of these transistors. FIG. 5 is a circuit diagram showing a part of a PROM according to a third embodiment of the present invention which improves this point. In the same figure, the input voltage discrimination circuit 1d is the same as the input voltage discrimination circuit _1c of FIG. 4, and the difference from _FIG .
Two output circuits 4d ₁ and 4d ₂ corresponding to these
is provided. The selection circuit _2d1 receives the outputs _D2d , _D3d , and _D5d of the discrimination circuit 1d, selects either the first real cell bit string RB1 or the first test cell bit string _TB1 , and selects the first real cell bit string RB1 or the first test cell bit string _TB1 . The information is given to the output circuit _4d1 , and the selection circuit _2d2 outputs the outputs _D2d , D3d, and _D3d of the discrimination circuit 1d.
In response to _D5d , either the second real cell bit string _RB2 or the second test cell bit string _TB2 is selected and the information is given to the output circuit _4d2 . With this circuit configuration, the base capacitance of the transistor in the selection circuit is smaller than in the case of FIGS. 3 and 4, and the switching speed is increased accordingly. Although all of the above embodiments use PROM, the present invention is not limited to this, and it goes without saying that it can be applied to any field programmable element. (7) Effects of the Invention As is clear from the above explanation, according to the present invention, the voltage applied to the chip enable terminal is
By detecting voltages in at least three stages: the real cell bit string selection voltage, the first test cell bit string selection voltage, and the second test cell bit string selection voltage, only one chip enable terminal can be used. In a small-capacity programmable element that has a memory cell and does not receive a bit address signal, it is possible to arrange at least two bit strings for test cells on one chip, and as a result, testing of peripheral circuits of memory cells is ensured. be done.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing part of a conventional PROM.
FIGS. 2 to 5 are circuit diagrams showing portions of PROMs according to first, second, third, and fourth embodiments of the present invention, respectively. 1, 1a, 1b, 1c, 1d...input voltage discrimination circuit, 2, 2a, 2b, 2c, 2d ₁ , 2d ₂ ... selection circuit, 3... word decoder circuit, 4... output circuit,... chip Enable terminal, WL ₁ ,
WL ₂ ... Word string, TB, TB ₁ , TB ₂ ... Bit string for test cells, RB... Bit string for real cells.

Claims (1)

[Claims] 1. One chip enable terminal, a plurality of word strings, at least one real cell bit string that intersects with the word string, at least two test cell bit strings that intersect with the word string, An input voltage determination circuit that determines which of at least three voltage ranges a signal voltage input to a chip enable terminal belongs to, a low voltage range, a medium voltage range, and a high voltage range; When it is determined that the voltage belongs to the low voltage range, select the bit string for the real cell, and when it is determined that the input signal voltage belongs to the medium voltage range, select one of the bit strings for the test cell, A selection circuit that selects another bit string for the test cell when it is determined that the input signal voltage belongs to a high voltage range, and an output that outputs a signal of the bit string selected by the selection circuit. A programmable element comprising a circuit.