JPS6334700B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic synchronizer that automatically issues a closing command to a circuit breaker when a generator is started and connected in parallel to a grid.

A conventional device of this type is shown in FIG. In FIG. 1, reference numeral 1 denotes an alternating current generator connected in parallel to the grid by a circuit breaker 2, and at both ends of the circuit breaker 2 there are voltage transformers 3 for transforming the sine wave voltages on the generator side and the grid side, respectively. 4 are connected to each other, and an automatic synchronizer 20 consisting of the following components is connected to the secondary sides of these transformers 3 and 4. 5 and 6 are auxiliary transformers connected to the secondary sides of the instrument transformers 3 and 4, respectively; 7 is a full-wave rectifier that rectifies the secondary side AC voltage of the auxiliary transformers 5 and 6; 8 and 1;
1 is a capacitor, 9 is a variable resistor that removes high frequency components of the output voltage of the full-wave rectifier 7 along with the capacitor 8, 10 is a resistor, and 12 is a unit that compares the output of the advance phase angle setting circuit 15 and the output of the full-wave rectifier 7. 13 is a circuit breaker closing time setting circuit that detects a progressive phase difference angle to compensate for the closing time of the circuit breaker; 14 is a constant advance phase angle detector 12 and closing time; A synchronization signal generation circuit generates a synchronization signal based on the output of the setting circuit 13, and 16 is an output contact for synchronous parallelism.

Next, the operation will be explained. In the case of a sine wave on both the grid side and the generator side, the polarity of the secondary coil of the auxiliary transformer 6 is reversed compared to that of the auxiliary transformer 5, and a sine wave with the positive and negative sides of the sine wave on the generator side reversed. It is superimposed with the sine wave on the grid side and input to the full wave rectifier 7.
In this case, if there is a frequency difference between the two sine waves, a beat voltage as shown at A in FIG. 2 is generated at the output of the full-wave rectifier 7. This capacitor 8
When high frequency components are removed using resistor 9, B in Figure 2 is obtained.
A DC pulsating voltage like . The leading phase angle setting circuit 15, which is made up of a resistor, generates a voltage as indicated by D in C in FIG. As shown in E in FIG. 2, an output that becomes "L" is output during a phase angle close to the synchronization point. That is,
By changing the resistance value of the leading phase angle setting circuit 15, the detected leading phase angle can be changed. Note that the point at which the DC pulsating voltage becomes zero is when the phases of the sine wave voltage on the grid and generator side match, that is, the synchronization point, and the point at which the DC pulsating voltage becomes maximum is the phase difference.
Indicates that it is 180°. In this way, the DC pulsating voltage shown in FIG. 2B is approximately proportional to the phase difference between the sinusoidal voltages of the generator and the grid, and a predetermined leading phase angle is detected by detecting this DC pulsating voltage.

On the other hand, the closing time setting circuit 13 that detects the gradual degree of phase difference in order to compensate for the closing time of the circuit breaker includes:
A current proportional to the DC pulsating voltage as shown in F in Figure 2.
i _a is input through the resistor 10, and the DC pulsating voltage is differentiated by the capacitor 11 to obtain the sine waveform.
Input the differential current i _d that has a cos waveform. The closing time setting circuit 13 detects and outputs that the sum i _y of these currents i _a and i _d has become less than zero ampere.
In other words, the output is output at 25Y ON of F in Figure 2. Note that this output 25Y ON is based on the function of the differential current i _d so that if the beat period is doubled, the differential current i _d is halved, and if the beat period is halved, the differential current i _d is doubled. Therefore, it has a characteristic that it is always output a certain period of time before synchronization.

The synchronization signal generation circuit 14 includes the output 25X of the constant advance phase angle detector 12 and the synchronization time setting circuit 1.
It is determined which of the outputs 25Y of 3 operates first, and only when the output 25X operates first and then the output 25Y operates, the synchronous parallel output contact 16 is closed at the same time as the output 25Y operates, and the circuit breaker 2 is closed. Parallel. In other words, if the predetermined advance phase angle 25X is set large by the advance phase angle setting circuit 15, the circuit breaker 2 can be closed even in a place where the frequency difference is large, and if 25X is set small, the circuit breaker 2 cannot be closed unless the frequency difference becomes small. It is. That is, by adjusting the constant advance phase angle setting circuit 15, the closing frequency difference can be limited, and the closing time setting circuit 13 compensates for the closing frequency difference.

Although not shown, the condition is that the voltage difference between the grid and the generator is below the specified value, and the closing command to circuit breaker 2 is made so that the voltage difference and frequency difference become small and the closing command is made from the synchronization point. Issued at a point in time minutes in advance.

Since the conventional automatic synchronizer is configured as described above, the circuit breaker closing time setting circuit 13 and constant advance phase angle setting circuit 15 are tested for each product.
Relationship between the scales of the circuit breaker closing time setting circuit 13 and the variable resistor 9, and the leading phase angle and the leading phase angle setting circuit 1
It was not possible to set this unless we had created a large amount of data that clarified the relationship between the 5 scales.

The present invention has been made in order to eliminate the drawbacks of the conventional ones as described above, and in order to shorten test time and save labor, the present invention has been made to improve the circuit breaker closing time setting circuit and constant advance phase of an automatic synchronizer. To provide an automatic synchronizer which can be digitally set and used without taking test data for input time or advance phase angle by simply confirming normal operation by digitizing an angle detection circuit. It is an object.

An embodiment of the present invention will be described below with reference to FIGS. 3 to 9. In FIG. 3, the same or corresponding parts as in FIG. 1 are designated by the same reference numerals. In FIG. The circuit 29 is an exclusive OR gate (hereinafter referred to as "Ex-
30 is a crystal oscillator (hereinafter referred to as "OSC") which is a reference clock pulse generation circuit.
31 is an advanced phase angle detection circuit for setting and detecting an advanced phase angle, the details of which are shown in FIG.
2 is a pulse width extension circuit 33 whose details are shown in FIG. 7 for enlarging the output pulse of this advanced phase angle detection circuit;
is a circuit breaker closing time setting circuit consisting of the following components, the details of which are shown in FIG. In FIG. 5, 51 and 52 each detect the rising edge of a pulse and generate an "L" pulse at the rising edge, and 53 detects the rising edge of the pulse and becomes "H" after a certain period of time to generate the pulse. Rising detection ON-DELAY circuit that goes “L” at the falling edge of 54
55 is a presettable up counter; 56 and 57 are each presettable down counters; 58, 60, and 62.
~65 and 69 are each IC NAND circuit, 59 is
IC inverter circuit, 61 is the arbitrarily set number (K
K outputs 1 pulse for every input pulse
67 and 68 are direct-coupled flip-flops each consisting of two NAND circuits of an IC, 70 is a pulse width expansion circuit, and 71 is an inverter. In FIG. 7 showing details of the advanced phase angle detection circuit 31 and the pulse width extension circuit 32, 81, 101, and 108 are IC inverters, 82 is a down counter that can be preset, 83 to 86 are pull-up resistors,
87 to 90 are preset switches, 102 is a diode, 103 is a low resistance of, for example, 1KΩ, and 10
4 is a high resistance of, for example, 100KΩ, 105 is a capacitor for creating a time delay, and 106 and 107 are each an IC Schmitt circuit.

Next, the operation of the present invention will be explained. In FIG. 3, the rectangular wave conversion circuits 27 and 28 are each
It is configured to output "L" when there is a positive input, and output "H" when there is a negative input. In this case, a sine wave voltage on the system side such as the BUS in FIG. The sine wave voltage on the generator side as shown in FIG.
When the waveform is transformed into a rectangular waveform and input to the Ex-OR gate 29, an output pulse train as shown in FIG. 4G is generated at the Ex-OR gate 29. In other words, in Figure 4
When BUS and GEN AC voltages have the same sign, Ex
-OR gate 29 outputs "L" and "H" when the signs are different. Examining the width of the "H" pulse of this Ex-OR gate 29 pulse train (Fig. 4G), it becomes clear from Fig. 4 that the phase difference between the AC voltages BUS and GEN is proportional to the pulse width. .
The output pulse train G of the Ex-OR gate 29, which is proportional to the phase difference between the alternating current voltages, is gradually input to the input time setting circuit 33 shown in detail in FIG. 5 and the advance phase angle detection circuit shown in detail in FIG. Ru. 6G and 8G are enlarged views of this input pulse train, that is, FIG. 4G.

Next, the operation of the closing time setting circuit 33 will be explained. The first rise detection circuit 51 detects the rise of the input pulse train G of the input time setting circuit 33 and outputs a waveform as shown in FIG. 6A. In this case, the detection pulse width is set as short as, for example, 1 microsecond (hereinafter abbreviated as "1 μS").
The second rise detection circuit 52 detects the rise of the output pulse of the first rise detection circuit 51. That is, the output pulse of the second rise detection circuit 52 (FIG. 6B) is an "L" pulse after the rectangular wave input to the input time setting circuit 33 is delayed by the "L" pulse time width of the first rise detection circuit 51. occurs. rising
The ON-DELAY detection circuit 53 generates an output as shown in FIG. 6C, which becomes "H" after a certain period of time after the rectangular wave input G rises, and becomes "L" when the pulse train G falls. This fixed period of time is also very short,
For example, set it to about 3μS. Fall detection circuit 5
Reference numeral 4 detects the falling edge of the rectangular wave input G, and generates an "L" pulse at the falling edge as shown in FIG. 6D. The up counter X55 converts each rectangular wave pulse width of the pulse train G into a binary digital value and detects it, and 1 μS after the rise of the rectangular wave G, it is preset to zero by the output of the second rise detection circuit 52. Rise ON with high frequency pulse of OSC30 from
The count is increased only while the output of the DELAY detection circuit (FIG. 6C) is "H".

Here, the frequency of OSC30 is 1MHz, and the sine wave voltage is
If the frequency of GEN or BUS is 50Hz, the maximum width of the square wave G is 1/(50Hz x 2) = 10 milliseconds (m
sec), and the maximum width pulse number is 1×10 ⁶ ×10×
10 ^-3 = 10 ⁴ pulses. In other words, each pulse width of 0 to 10 msec of the pulse train is determined by the up counter
5 for 0 to 10000 pulses (precisely the first 3μS
is 0 to 10000-3) because no oscillation pulse is input.
is converted to

The down counter Y56 presets the output of the up counter 55 proportional to the "H" pulse width generated immediately before the rising edge of the pulse waveform G in FIG. Count down only during the "H" pulse width shown in Figure C. FIG. 6Y shows the waveform output of the down counter Y56. In other words, the down counter Y56 divides the time corresponding to the difference between the previous pulse width and the immediately following pulse width in the pulse train G by 2.
Convert to base number and detect. Specifically, if the frequency difference ΔF between the sine wave voltage GEN and BUS on the generator side and the grid side is 0.1 Hz, and the frequency of either the sine wave voltage on the generator side or the grid side is 50 Hz,
The period of the beat voltage shown between the synchronization points in Fig. 4 is T = 1/0.1Hz = 10 seconds (sec) (1), and the difference between two adjacent pulse widths of the pulse train G is expressed in time as ΔT. =10msec/10sec×0.5×50Hz×2=10/500=20μS
(2), and expressed in terms of the number of high-frequency pulses, it is 10,000 pulses x 1/500 = 20 pulses (3). In other words, down counter Y56 has 10
A binary number corresponding to base 20 is stored in memory.

The down counter Z57 uses the output pulse of the fall detection circuit 54 shown in FIG. 6D at the moment when the pulse in FIG. Proportional up counter x5
Preset the output of 5. Down counter Y5
6 is a NAND circuit 63 when the output of the rising edge detection ON-DELAY circuit 53 (FIG. 6C) is "H".
The output of the NAND circuit 64 is “L”, and the output of the NAND circuit 64 is “H”
Therefore, regardless of the output of the K-ary counter 61,
The oscillation frequency (1MHz) of the OSC 30 itself is used to count down via the NAND circuit 62. on the other hand,
When the rectangular wave G in Fig. 6 becomes “L”, a rising edge is detected.
Since the output of the ON-DELAY circuit 53 (FIG. 6C) becomes "L", the output of the NAND circuit 62 becomes "H", and the output of the NAND circuit 63 also becomes "H".
The down counter Y56 counts down with the output pulse of the K-ary counter 61 which outputs one pulse when the K pulse is input. FIG. 6Y shows the waveform in this case. When the count value becomes zero due to this down count, the down counter Y56 outputs a borrow output (BRO), and the first flip-flop 67
is inverted, and an "L" input is applied to the NAND circuit 60, causing the down counter Z57 to stop counting down. In other words, the down counter Z57 presets the pulse width of the latest pulse in FIG. ) is stored in memory by the down counter Y56, the down count is counted down by K pulses for each pulse indicating the difference in pulse width, and the down count is stopped when the output of the down counter Y56 becomes zero.

To give a concrete example, the closing time of circuit breaker 2 is
Assuming 0.1 _seconds , the value of up counter Pulse (5). Furthermore, if the frequency difference ΔF = 0.1 Hz, the difference in the width of successive pulses (Fig. 6 G) that is the output of the down counter Y56 is 20 as shown in equation (3).
If the K-ary counter 61 is set to decimal, the down counter Z57 will be 20 pulses x 10 =
Since it becomes zero at 200 pulses, a borrow output (BRO) is output as shown in FIG. The "L" output from this inverter 71 becomes the output of the closing time setting circuit 33 which detects the pre-synchronization predetermined time.

Similarly, when the frequency difference ΔF=0.05Hz, the period of the beat voltage is T=1/0.05=20sec, and the value of up counter X55 0.1 seconds before the synchronization point is Tx=10msec×0.1sec/20sec× 0.5=0.1msec(6), and when converted to the number of pulses, it becomes 10000×0.1/10=100 pulses(7). Further, the pulse width difference output of the down counter Y56 is 10 pulses if the frequency difference ΔF = 0.05Hz, and if the K-ary counter 61 is set to decimal, the down counter Z57 is 10 pulses x 10 = 100
Since it becomes zero with a pulse, a borrow output (BRO) is output 0.1 seconds before the synchronization point, similar to when ΔF is 0.1Hz.

In this way, if the K-ary counter 61 is set to decimal, the inverter 71 will generate an "L" output signal 0.1 seconds before the synchronization point even if the frequency difference ΔF changes. If this K-ary counter 61 is set to quinary, the down counter Z57 can be output 0.05 seconds before the synchronization point, and if set to 20, the down counter Z57 can be output 0.2 seconds before the synchronization point.
By adjusting the settings of the K-ary counter 61,
Settings can be made that match the predetermined circuit breaker closing time.

Next, the operations of the advanced phase angle detection circuit 31 and the pulse width extension circuit 32 will be explained. In addition, the seventh
The advanced phase angle detection circuit 31 in the figure actually uses two or more 4-bit binary counters 82 connected in series, but here, to simplify the explanation, one 4-bit binary counter 82 is used. Consider one having a forward counter 82.

Now turn on the preset switches 87 to 89 of the down counter 82 and connect the terminals DA, DB and
While applying 0V (“L”) to DC, turn off the preset switch 90 and apply 5V (“H”) to terminal DD. When the LOAD of the down counter 82 is set to “L”, the DA set by the switches 87 to 90
DD data (binary number 1000, i.e. decimal number 8)
Preset. When the output of FIG. 8G, which is the output pulse train of the Ex-OR gate 29, is "H", the output of the inverter becomes "L", and the down counter 82 is reset as shown in FIG. 8M. Set the terminal T _u of the down counter 82 to “H” (+
5V) and give a high frequency pulse of OSC30 to TD, it will count down.

That is, as shown in FIG. 8M, the length of the "L" pulse of the pulse train G, in other words, the interval between successive "H" pulses of the pulse train G, is measured by the number of high-frequency pulses of the OSC 30. The ones preset to base 8 are down one by one.
When the output value of the down counter 82 becomes “0”
An "L" pulse is output from the BRO terminal as shown in Figure 8N. That is, when the phase difference between the sine wave voltages on the generator side and the grid side decreases, the width of the "H" pulse in Figure 8G decreases in proportion to it, and the width of the "L" pulse in Figure 8G decreases in proportion. Since the width increases inversely proportionally, in reality, when the length of the "L" pulse exceeds a predetermined value (which can be set with switches 87 to 90), the "L" pulse advances to the output of the phase angle detection circuit 31. occurs. In this way, an "L" pulse is generated at the output of the advanced phase angle detection circuit 31 (N in FIG. 8) once every cycle of the pulse train in FIG. 8G when the phase difference is below a certain value. do.

Next, the operation of the pulse width extension circuit 32 will be explained. In FIG. 7, the diode 102 conducts only when the output of the inverter 101 is "H", that is, when the output N of the advanced phase angle detection circuit 31 is "L", and makes the low resistance 103 conductive.
3 and the high resistance 104 are connected in parallel, the combined resistance becomes low and the capacitor 105 is charged quickly, and the terminal voltage of the capacitor 105 rises rapidly. On the other hand, when the output of the inverter 101 is "L", the diode 102 is non-conductive, and only the high resistance 104 is conductive, discharging the energy stored in the capacitor 105, so that the discharge time becomes longer, and as shown in FIG. The output waveform will be as follows. Schmidt trigger circuit 1
06 and 107 constitute a flip-flop circuit, and when the terminal voltage of the capacitor 105 is discharged to a certain value or more, the Schmitt trigger circuit 10
The input of 7 becomes "L".

That is, in the output pulse train of the advanced phase angle detection circuit 31 (N in FIG. 9), the number of "L" pulses is 1.
When it is a pulse, the pulse width is extended. In addition, when the above-mentioned "L" pulse number occurs multiple times at regular intervals, the pulses are converted into continuous ones and turned off after a fixed time period from the last pulse.
(Figure 9 Q).

The synchronization signal generation circuit 14 is the same as the conventional one shown in FIG. Only when the output 25Y turns ON after the output 25X turns ON, the parallel output contact 16 is closed simultaneously with the ON operation of the output 25Y, and the circuit breaker 2 is connected in parallel.

When the advanced phase angle detection circuit 31 is set to 3.6°, the output 25X of the pulse width extension circuit 32 turns ON.
When the frequency difference from the synchronization point is ΔF=1Hz, 1sec×3.6°/360°=0.01sec When ΔF=0.2Hz, 5sec×3.6°/360°=0.05sec When ΔF=0.1Hz, 10sec×3.6°/ 360° = 0.1sec ago. Therefore, the input command of the synchronization input signal generation circuit 14 is 0.1 before synchronization when the frequency difference ΔF is 0.1Hz or less.
seconds, and the input frequency difference will be 0.1Hz if the lead phase angle is set to 3.6°. Similarly, if the leading phase angle is set to 7.2°, it is possible to input the frequency difference ΔF = 0.2Hz or less, and if the leading phase angle is set to 1.8°, ΔF = 0.05
It can be input at frequencies below Hz. In this way, the advanced phase angle detection circuit 31 sets the possible input frequency difference.

Although not shown, in the present invention,
The voltage difference between the grid side and the generator side is detected by a voltage difference detection circuit, and the condition is that the voltage difference has become less than the specified value, and a turn-on command is issued when both the voltage difference and the frequency difference become small. Of course.

In the above explanation, the frequency of OSC30 is
Although we have stated that the frequency is 1MHz, it is clear that the accuracy will improve if this frequency is increased to the limit at which the counter can operate. Also, in the above explanation, up counter X55, down counter Y56, and down counter Z57 were explained as binary counters, but they are binary counters.
It is clear that a decimal counter (BCD counter) can have a similar effect.

Furthermore, although the leading phase angle detection circuit 31 of the present invention is configured to detect the leading phase angle using the down counter 82, it is of course possible to detect the leading phase angle using an up counter. Although the configuration is such that the leading phase angle is detected at intervals of the "L" state which are inversely proportional to each other, it is clear that the leading phase angle may also be detected by the pulse width of the "H" state which is proportional to the phase difference.

As described above, in the automatic synchronizer of the present invention, both the closing time setting circuit and the advance phase angle detection circuit are digitally set, so that the scale of the advance phase angle setting circuit and the test data for a certain period of time before synchronization at each frequency difference are Since it can be used without having to take the oscillator, test time can be significantly shortened, and the input command can be made more accurate due to the stability of the frequency of the crystal oscillator, regardless of errors such as capacitance changes and ripple effects. It has this effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional automatic synchronization device, FIGS. 2 A to F are operational waveform diagrams of each part of the automatic synchronization device shown in FIG. 1, and FIG. 3 shows an embodiment of the automatic synchronization device of the present invention. Block diagram, Figure 4 BUS~25Y
are the operation waveform diagrams of each part of the automatic synchronization device in Figure 3, and Figure 5.
The figure is a block diagram of the closing time setting circuit in the automatic synchronizer of the present invention, Figure 6 is a waveform diagram of each part of the closing time setting circuit of Figure 5, and Figure 7 is lead phase angle detection in the automatic synchronizer of the present invention. A circuit diagram of the circuit and the pulse width extension circuit, FIG. 8 is a time chart of the advanced phase angle detection circuit of FIG. 7, and FIG. 9 is a diagram of operation waveforms of each part of the pulse width extension circuit of FIG. 7. 1: AC generator, 2: Circuit breaker, 3, 4, 5,
6: Transformer, 7: Full wave rectifier, 12, 31: Advance phase angle detector, 13, 33: Closing time setting circuit,
14: Synchronization signal generation circuit, 15: Advance phase angle setting circuit, 20: Automatic synchronizer, 27, 28: Rectangular wave conversion circuit, 29: Exclusive OR gate, 3
0: Crystal oscillator, 32: Pulse width extension circuit, 5
1, 52: Pulse rising detection circuit, 53: Rising detection ON-DELAY circuit, 54: Pulse falling detection circuit, 55: Up counter, 56, 57, 8
2: down counter, 67, 68: flip-flop, 106, 107: Schmitt circuit,
In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] 1. A first square wave conversion circuit that converts a sine wave voltage on the grid side into a rectangular wave in an automatic synchronizer that issues a closing command to a circuit breaker when a generator is started and connected in parallel to a grid. , a second rectangular wave conversion circuit that converts the sine wave voltage on the generator side into a rectangular wave, and a phase difference between the two sine wave voltages by inputting the outputs of these first and second rectangular wave conversion circuits. an exclusive OR gate that converts the pulse train into a pulse train having a pulse width proportional to
The clock is preset during the "H" or "L" pulse generation period of the pulse train, and a predetermined advanced phase is achieved by counting down or counting up with the high frequency pulse of the reference clock pulse generation circuit during the pulse interval or pulse width period of successive pulses of the pulse train. an advanced phase angle detection circuit that detects the angle; a pulse width extension circuit that expands the output pulse width of the advanced phase angle detection circuit; and a pulse width extension circuit that increases the output pulse width of the exclusive OR gate, and counts up each pulse width of the output pulse train of the exclusive OR gate using the high frequency pulse. a first counter that detects the first counter;
a second counter that presets a count number corresponding to the pulse width immediately before the counter, and then counts down by the high-frequency pulse only during the latest pulse width to detect the difference between the pulse widths before and after the pulse train; When the second counter detects the difference, a count number corresponding to the latest pulse width of the first counter is preset, and the difference value of the second counter is counted down to zero by the output pulse of the K-ary counter. A third step that detects a certain period of time before synchronization by counting down with the high frequency pulse until
a counter, an input blocking circuit that stores when the output of the second counter becomes zero and blocks the input of the high frequency pulse to the third counter; The synchronous closing signal generation circuit includes a memory element that stores this information, and a synchronous closing signal generating circuit that generates a synchronous closing signal to the circuit breaker, and the synchronous closing signal generating circuit generates a synchronous closing signal after the output pulse of the pulse width extension circuit via the storage element. An automatic synchronization device characterized in that it is configured to issue a closing command to a circuit breaker only when an output pulse from a third counter is generated. 2. The automatic synchronization device according to claim 1, wherein the first, second and third counters are binary counters. 3 The first, second and third counters are binary coded.
The automatic synchronization device according to claim 1, characterized in that it is a decimal counter. 4. A voltage difference detection circuit is provided to detect the difference between the voltages on the grid side and the generator side, and the output of the voltage difference detection circuit and the output of the above-mentioned pulse width extension circuit are ANDed, and if the voltage difference is excessive, The automatic synchronizer according to any one of claims 1, 2, and 3, characterized in that the automatic synchronizer is configured to block a closing command to a circuit breaker.