JPS6334701B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic synchronizer that automatically issues a closing command to a circuit breaker when a generator is started and connected in parallel to a grid.

A conventional device of this type is shown in FIG. In FIG. 1, reference numeral 1 denotes an alternating current generator connected in parallel to the grid by a circuit breaker 2, and at both ends of the circuit breaker 2 there are voltage transformers 3 for transforming the sine wave voltages on the generator side and the grid side, respectively. 4 are connected to each other, and an automatic synchronizer 20 consisting of the following components is connected to the secondary sides of these transformers 3 and 4. 5 and 6 are auxiliary transformers connected to the secondary sides of the instrument transformers 3 and 4, respectively; 7 is a full-wave rectifier that rectifies the secondary side AC voltage of the auxiliary transformers 5 and 6; 8 and 1;
1 is a capacitor, 9 is a variable resistor that removes high frequency components of the output voltage of the full-wave rectifier 7 along with the capacitor 8, 10 is a resistor, and 12 is a unit that compares the output of the advance phase angle setting circuit 15 and the output of the full-wave rectifier 7. 13 is a circuit breaker closing time setting circuit that detects a gradual phase difference angle to compensate for the circuit breaker closing time; 14 is a comparator 1;
2 and a synchronization signal generation circuit 16 that generates a synchronization signal based on the output of the input time setting circuit 13;
is the synchronous parallel output contact.

Next, the operation will be explained. If both the grid side and the generator side are sine waves, the polarity of the secondary coil of the auxiliary transformer 6 is reversed compared to the auxiliary transformer 5, and the sine wave is a sine wave with the positive and negative sides of the sine wave on the generator side reversed. is superimposed on the sine wave on the grid side and input to the full-wave rectifier 7. In this case, if there is a frequency difference between the two sine waves, the output of the full-wave rectifier 7 will be A in FIG.
A beat voltage like this is generated. When high frequency components are removed from this using a capacitor 8 and a resistor 9, a DC pulsating voltage as shown in B in FIG. 2 is produced. The lead phase angle setting circuit 15, which is composed of a resistor, is shown in FIG.
By generating a voltage like D in the middle and comparing the magnitude of this voltage with the DC pulsating voltage, the constant advance phase angle detector 12 detects "L" between the phase angles near the synchronization point as shown in E of FIG. Produces an output that looks like this. That is, by changing the resistance value of the leading phase angle setting circuit 15, the leading phase angle to be detected will change. Note that the point at which the DC pulsating voltage becomes zero is when the phases of the sine wave voltage on the grid and generator side match, that is, the synchronization point, and the point at which the DC pulsating voltage becomes maximum is a phase difference of 180°. show. In this way, the DC pulsating voltage shown in FIG. 2B is approximately proportional to the phase difference between the sinusoidal voltages of the generator and the grid, and a predetermined leading phase angle is detected by detecting this DC pulsating voltage.

On the other hand, the closing time setting circuit 13 that detects the gradual degree of phase difference in order to compensate for the closing time of the circuit breaker includes:
A current proportional to the DC pulsating voltage as shown in F in Figure 2.
i _a is input through the resistor 10, and the DC pulsating voltage is differentiated by the capacitor 11 to obtain the sine waveform.
Input the differential current i _d that has a cos waveform. The closing time setting circuit 13 detects and outputs that the sum i _y of these currents i _a , i _d has become less than zero ampere.
In other words, the output is output at 25Y ON of F in Figure 2. Note that this output 25Y ON is based on the function of the differential current i _d so that if the beat period is doubled, the differential current i _d is halved, and if the beat period is halved, the differential current i _d is doubled. Therefore, it has a characteristic that it is always output a certain period of time before synchronization.

The synchronization signal generation circuit 14 includes the output 25X of the constant advance phase angle detector 12 and the synchronization time setting circuit 1.
3, which of the outputs 25Y operates first, and only when the output 25X operates first and then the output 25Y operates, the synchronous parallel input output contact 16 is closed at the same time as the output 25Y operates, and the circuit breaker 2 is closed. Parallel. In other words, if the predetermined advance phase angle 25X is set to be large by the advance phase angle setting circuit 15, the circuit breaker 2 can be closed even in a place where the frequency difference is large, and if 25X is set to be small, the circuit breaker 2 cannot be closed unless the frequency difference is small. It is. That is, by adjusting the constant advance phase angle setting circuit 15, the closing frequency difference can be limited, and the closing time setting circuit 13 compensates for the closing frequency difference.

Although not shown, the condition is that the voltage difference between the grid and the generator is below the specified value, and the closing command to circuit breaker 2 is made so that the voltage difference and frequency difference become small and the closing command is made from the synchronization point. Issued at a point in time minutes in advance.

Since the conventional automatic synchronizer is configured as described above, the circuit breaker closing time setting circuit 13 is tested for each product, and the variable resistor forming the circuit breaker closing time and advance phase angle setting circuit 15 is tested. It was necessary to create something that clarified the relationship with the value of . That is, in addition to confirming that the automatic synchronizer operates normally, it is necessary to obtain a large amount of detailed test data of the circuit breaker closing time setting circuit 13.

The present invention was made in order to eliminate the drawbacks of the conventional ones as described above, and in order to shorten test time and save manpower, the circuit breaker closing time setting circuit of an automatic synchronizer is digitalized. The purpose of this invention is to provide an automatic synchronizer that can be used by digitally setting the closing time without any test data for the closing time, just by confirming normal operation.

An embodiment of the present invention will be described below with reference to FIGS. 3 to 6. In FIG. 3, the same or corresponding parts as in FIG. 1 are designated by the same reference numerals. In FIG. 29 is an exclusive OR gate (hereinafter referred to as "Ex-OR gate") which takes the exclusive OR of the output signals of the rectangular wave conversion circuits 27 and 28. ), 30
is a circuit breaker closing time setting circuit consisting of the following components, the details of which are shown in FIG. In FIG. 5, reference numerals 51 and 52 each detect the rising edge of a pulse and generate an "L" pulse at the rising edge. 53 detects the rising edge of the pulse and becomes "H" after a certain period of time after the rising edge of the pulse. 54 is a falling detection circuit that detects the falling edge of a pulse and generates an "L" pulse at the falling edge; 55 is a presettable up counter; 56, 57; are down counters that can be preset, respectively, 58, 60, 62 to 65
and 69 are NAND circuits of the ICs, 59 are inverter circuits of the ICs, 61 is a K-ary counter that outputs one pulse in response to input of an arbitrarily set number (K) of pulses, and 6
6 is a crystal oscillator (hereinafter abbreviated as "OSC") which is a reference clock pulse generation circuit, 67 and 68 are direct-coupled flip-flops each made up of two NAND ICs, 70 is a pulse width expansion circuit, and 71 is an inverter.

Next, the operation of the present invention will be explained. In FIG. 3, the rectangular wave conversion circuits 27 and 28 are each
It is configured to output "L" when there is a positive input, and output "H" when there is a negative input. In this case, the sine wave voltage on the grid side as shown in FIG. The sine wave voltage on the generator side as shown in Fig. 4 GEN is converted into a rectangular wave conversion circuit 2 via the transformer 26.
When the signal is transformed into a rectangular wave at step 8 and inputted to the Ex-OR gate 29, an output pulse train as shown in FIG. 4G is generated at the Ex-OR gate 29. In other words, when the AC voltages of BUS and GEN in Fig. 4 have the same sign,
The Ex-OR gate 29 outputs "L" and "H" when the signs are different. Examining the width of the "H" pulse of the output pulse train of this Ex-OR gate 29 (Fig. 4G), it is found from Fig. 4 that the phase difference between the AC voltages BUS and GEN is proportional to the pulse width. do. Ex−OR proportional to the phase difference between this AC voltage
The output pulse train G of the gate 29 is gradually inputted to the input time setting circuit 30 whose details are shown in FIG. FIG. 6G is an enlarged view of this input pulse train, that is, FIG. 4G.

The operation of the closing time setting circuit 30 will be explained below. The first rise detection circuit 51 detects the rise of the input pulse train G of the input time setting circuit 30 and outputs a waveform as shown in FIG. 6A. in this case,
The detection pulse width is set as short as, for example, 1 microsecond (hereinafter abbreviated as "1 μs"). The second rise detection circuit 52 detects the rise of the output pulse of the first rise detection circuit 51. That is, the output pulse of the second rise detection circuit 52 (FIG. 6B) is either a rectangular wave input to the input time setting circuit 30 or an "L" pulse delayed by the "L" pulse time width of the first rise detection circuit 51. occurs. Rising ON−
The DELAY detection circuit 53 generates an output as shown in FIG.
becomes. This fixed time is also set to a very short time, for example, about 3 μs. The falling edge detection circuit 54 detects the falling edge of the rectangular wave input G, and generates an "L" pulse at the falling edge as shown in FIG. 6D. The up counter X55 converts each rectangular wave pulse width of the pulse train G into a binary digital value and detects it, and 1 μs after the rise of the rectangular wave G, it is preset to zero by the output of the second rise detection circuit 52. After that, the high frequency pulse of OSC68 turns on the rising edge.
The count is increased only while the output of the DELAM detection circuit (FIG. 6C) is "H".

Here, the frequency of OSC66 is 1MHz, and the sine wave voltage is
If the frequency of GEN or BUS is 50Hz, the maximum value of the square wave G is 1/(50Hz x 2) = 10 milliseconds (m
sec), and the maximum width pulse number is 1×10 ⁶ ×10
×10 ^-3 = 10 ₄ pulses. In other words, each pulse width of 0 to 10 m sec in the pulse train is determined by the up counter
3μs is 0 to 10000- because no oscillation pulse is input.
3).

The down counter Y56 presets the output of the up counter 55 proportional to the "H" pulse width generated immediately before the rise of the pulse waveform G in FIG. Count down only during the "H" pulse width shown in Figure C. FIG. 6Y shows the waveform output of the down counter Y56. That is, the down counter Y56 converts the time corresponding to the difference between the previous pulse width and the immediately following pulse width of the pulse train G into a binary number and detects the time. Specifically, if the frequency difference ΔF between the sine wave voltages GEN and BUS on the generator and grid sides is 0.1 Hz, and the frequency of either the sine wave voltages on the generator side or the grid side is 50 Hz, then 4
The period of the beat voltage shown between the synchronization points in the figure is T = 1/0.1 Hz = 10 seconds (sec) (1), and the difference between two adjacent pulse widths of pulse train G is expressed in time as ΔT = 10 m. sec/10sec×0.5×50Hz×2=10/500=20
μs(2), and expressed in terms of the number of high-frequency pulses, it is 10000 pulses x 1/500 = 20 pulses (3), that is, the down counter Y56 has 10
A binary number corresponding to base 20 is stored in memory.

The down counter Z57 uses the output pulse of the fall detection circuit 54 shown in FIG. 6D at the moment when the pulse in FIG. Proportional up counter x5
Preset the output of 5. Down counter Y5
6 is a NAND circuit 63 when the output of the rising edge detection ON-DELAY circuit 53 (FIG. 6C) is "H".
The output of the NAND circuit 64 is “L”, and the output of the NAND circuit 64 is “H”
Therefore, regardless of the output of the K-ary counter 61,
The oscillation frequency (1MHz) of the OSC 66 is counted down via the NAND circuit 62. on the other hand,
When the rectangular wave G in Fig. 6 becomes “L”, a rising edge is detected.
Since the output of the ON-DELAY circuit 53 (FIG. 6C) becomes "L", the output of the NAND circuit 62 becomes "H", and the output of the NAND circuit 63 also becomes "H".
The down counter Y56 counts down with the output pulse of the K-ary counter 61 which outputs one pulse when the K pulse is input. FIG. 6Y shows the waveform in this case. When the count value becomes zero due to this down count, the down counter Y56 outputs a borrow output (BRO), and the first flip-flop 67
is inverted, and an "L" input is applied to the NAND circuit 60, causing the down counter Z57 to stop counting down. In other words, the down counter Z57 presets the pulse width of the latest pulse in FIG. Pulse 1 indicating the difference in pulse width from the time when down counter Y56 memorizes pulse 1
The down-count is counted down by K pulses for each pulse, and the down-count is stopped when the output of the down counter Y56 becomes zero.

To give a concrete example, the closing time of circuit breaker 2 is
Assuming 0.1 seconds, the value of up counter X55 0.1 seconds before the synchronization point is _T Pulse (5). Furthermore, if the frequency difference ΔF = 0.1 Hz, the difference in the width of successive pulses (Fig. 6 G) that is the output of the down counter Y56 is 20 as shown in equation (3).
If the K-ary counter 61 is set to 10, the down counter Z57 will be 20 pulses x 10 = 200.
Since the pulse becomes zero, a borrow output (BRO) is output 0.1 seconds before the synchronization point as shown in FIG. The "L" output from this inverter 71 becomes the output of the closing time setting circuit 30 which detects the pre-synchronization predetermined time.

Similarly, when the frequency difference ΔF = 0.05Hz, the period of the beat voltage is T = 1/0.05 = 20sec, and the value of up counter _X55 0.1 seconds before the synchronization point is T ×0.5=0.1msec(6), and when converted to the number of pulses, it becomes 10000×0.1/10=100 pulses (7). Further, the pulse width difference output of the down counter Y56 is 10 pulses if the frequency difference ΔF = 0.05Hz, and if the K-ary counter 61 is set to decimal, the down counter Z57 is 10 pulses x 10 = 100
Since it becomes zero with a pulse, a boro output (BRO) is output 0.1 seconds before the synchronization point, similar to when ΔF is 0.1Hz.

In this way, if the K-ary counter 61 is set to decimal, the inverter 71 will generate an "L" output signal 0.1 seconds before the synchronization point even if the frequency difference ΔF changes. If this K-ary counter 61 is set to quinary, the down counter Z57 can be output 0.05 seconds before the synchronization point, and if set to 20, the down counter Z57 can be output 0.2 seconds before the synchronization point.
By adjusting the settings of the K-ary counter 61,
Settings can be made that match the predetermined circuit breaker closing time.

The leading phase angle setting circuit 15 and the constant leading phase angle detector 12 are conventional devices, and similarly set the leading phase angle, detect it, and output an output 25X (FIG. 2E). Further, the synchronization signal generation circuit 14 also includes:
It is the same as the conventional one shown in FIG. 1, and it is determined which of the output 25X of the constant advance phase angle detector 12 and the output 25Y of the closing time setting circuit 30 of the present invention operates first, and the output 25X is After turning on,
Only when output 25Y turns ON, output 25Y
At the same time as the ON operation, the synchronous parallel output contact 16 is closed and the circuit breakers 2 are connected in parallel.

When the setting of the leading phase angle setting circuit 15 is set to 3.6°, the output 25X of the constant leading phase angle detector 12 becomes
Turns on when the frequency difference ΔF=1Hz from the synchronization point: 1sec×3.6°/360°=0.01sec When ΔF=0.2Hz, 5sec×3.6°/360°=0.05se
c When ΔF=0.1Hz, 10sec×3.6°/360°=0.1se
c before. Therefore, the input command of the synchronization input signal generation circuit 14 is 0.1 before synchronization when the frequency difference ΔF is 0.1Hz or less.
seconds, and the input frequency difference will be 0.1Hz if the lead phase angle is set to 3.6°. Similarly, if the leading phase angle is set to 7.2°, it is possible to input the frequency difference ΔF = 0.2Hz or less, and if the leading phase angle is set to 1.8°, ΔF = 0.05
It can be input at frequencies below Hz. In this way, the advance phase angle setting circuit 15 sets the input possible frequency difference.

Although not shown, in the present invention,
The voltage difference between the grid side and the generator is detected by a voltage difference detection circuit, and the condition is that the voltage difference becomes less than a specified value, and a turn-on command is issued when both the voltage difference and the frequency difference become small. Of course.

In the above explanation, the frequency of OSC66 is
Although we have stated that the frequency is 1MHz, it is clear that the accuracy will improve if this frequency is increased to the limit at which the counter can operate. Also, in the above explanation, up counter X55, down counter Y56, and down counter Z57 were explained as binary counters, but they are binary counters.
It is clear that a decimal counter (BCD counter) can have a similar effect.

As described above, in the automatic synchronizer of the present invention, the setting of the pre-synchronization fixed time of the closing time setting circuit can be digitally set by skillfully combining three counters, and the scale of the constant advance phase angle setting circuit can be set versus each frequency. Since it can be used without taking test data for a certain period of time before synchronization at the difference, the test time can be significantly shortened, and the input command can be set at the crystal oscillator frequency regardless of errors such as capacitance changes or ripple effects. This has the effect of increasing accuracy due to its stability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional automatic synchronization device, FIGS. 2 A to F are operational waveform diagrams of each part of the automatic synchronization device shown in FIG. 1, and FIG. 3 shows an embodiment of the automatic synchronization device of the present invention. 4 is an operational waveform diagram of each part of the automatic synchronizer shown in FIG. 3, FIG. 5 is a block diagram showing the closing time setting circuit in the automatic synchronizer of the present invention, and FIG. 6 is a diagram showing the closing time of FIG. 5. FIG. 3 is a waveform diagram showing the operation of each part of the setting circuit. 1... AC generator, 2... Circuit breaker, 3, 4,
5, 6, 25, 26...Transformer, 7...Full wave rectifier, 12...Constant advance phase angle detector, 13,30
... Closing time setting circuit, 14... Synchronous closing signal generation circuit, 15... Advance phase angle setting circuit, 20...
automatic synchronizer, 27, 28... rectangular wave conversion circuit,
29...Exclusive OR gate, 51, 52...Pulse rise detection circuit, 53...Rise detection ON-
DELAY circuit, 54...Pulse falling detection circuit,
55... Up counter, 56, 57... Down counter, 66... Crystal oscillator, 67, 68...
Flip-flop. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] 1. A first square wave conversion circuit that converts a sine wave voltage on the grid side into a rectangular wave in an automatic synchronizer that issues a closing command to a circuit breaker when a generator is started and connected in parallel to a grid. , a second rectangular wave conversion circuit that converts the sine wave voltage on the generator side into a rectangular wave, and the outputs of these first and second rectangular conversion circuits are inputted to calculate the phase difference between the two sine wave voltages. an exclusive OR gate for converting into a pulse train having a proportional pulse width; a first counter for counting up and detecting each pulse width by high-frequency pulses from a reference clock pulse generation circuit only during each pulse width of the pulse train; After presetting a count number corresponding to the immediately preceding pulse width of the first counter, the high-frequency pulse of the reference clock pulse generation circuit is used to count down only during the pulse width of the latest pulse train, and the difference between the pulse widths before and after the pulse train is detected. When the second counter detects the difference between the pulse widths before and after the pulse train, the second counter presets a count proportional to the latest pulse width that is the output of the first counter, and The detected value of the pulse width difference of the second counter is counted down by the output pulse of the K-ary counter and is counted down by the high frequency pulse of the reference clock pulse generation circuit until it reaches zero, and the count number corresponding to the pulse width difference is counted down. a third counter that detects a value K times , an input blocking circuit that stores when the output of the second counter becomes zero and blocks input of high-frequency pulses to the third counter; a memory element that stores information when the output of the counter No. 3 becomes zero; an advanced phase angle setting circuit that sets a predetermined advanced phase angle before synchronization; and an advanced phase angle detector that detects an advanced phase angle corresponding to the set value. A circuit is provided to detect which of the output pulse of the leading phase angle detection circuit and the output pulse of the third counter outputted via the storage element is outputted earlier, and detecting the output of the leading phase angle detection circuit. An automatic synchronizer comprising a synchronization signal generation circuit that generates a synchronization signal to a circuit breaker only when an output pulse from a third counter is output after a pulse is output. 2. The automatic synchronization device according to claim 1, wherein the first, second and third counters are binary counters. 3 The first, second and third counters are binary coded.
The automatic synchronization device according to claim 1, characterized in that it is a decimal counter. 4. A voltage difference detection circuit is provided to detect the voltage difference between the grid side and the generator side, and the logical product of the voltage difference detection circuit and the output of the advance phase angle detection circuit is taken, and when the voltage difference is excessive, the circuit breaker is activated. The automatic synchronization device according to any one of claims 1, 2, and 3, characterized in that the automatic synchronization device is configured to prevent generation of an input command to the automatic synchronization device.