JPS6337395B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic rhythm performance device, and more particularly to an automatic rhythm performance device in which a player can set his or her own rhythm pattern.

In conventional automatic rhythm performance devices, multiple rhythm patterns (for example, waltz, tango, etc.) are stored in a read-only memory (ROM) corresponding to each rhythm sound source, and the performer can select one of these rhythm patterns. A desired rhythm pattern was obtained by selecting one using a rhythm selection switch. (For example, Tokuko Sho 51-36059
There is an invention disclosed in No. ) However, in this type of automatic rhythm performance device, the rhythm pattern is determined by the contents stored in the read-only memory, and once the rhythm pattern is determined, the performer cannot arbitrarily change or set the rhythm pattern. I can't. Therefore, the types of rhythms that can be played are limited, making it impossible for players to play as they wish.

In contrast to the above-mentioned automatic rhythm performance apparatus, an automatic rhythm performance apparatus has been proposed in which a rhythm pattern can be arbitrarily set using a mechanical switch. In this method, the rhythm selection switch is constructed from a matrix circuit into which multiple columns and multiple rows of pins can be inserted, and a rhythm pattern is set by appropriately inserting multiple pins into this matrix circuit (for example, (A device disclosed in the specification of Utility Model Publication No. 47-525.) However, such an automatic rhythm performance device using a mechanical switch has the disadvantage that the device is inevitably large due to its mechanism. Therefore, even though it is possible to arbitrarily set various rhythm patterns, it is impossible to increase the capacity of the device in order to make it more compact, which naturally limits the range of rhythm settings. .

This invention was developed in view of the above-mentioned drawbacks of the conventional automatic rhythm playing device, and allows the rhythm pattern for each rhythm sound source to be set arbitrarily according to the player's will. The purpose of the present invention is to provide a compact automatic rhythm performance device.

The automatic rhythm playing device of the present invention includes: an address generator that generates an address signal at a desired speed; a pattern forming switch section having at least as many switches as the number of rhythm sound sources; and a rhythm pattern corresponding to each rhythm sound source. a random access memory (RAM) for storing; a rhythm sound source circuit that receives rhythm pattern signals output from the random access memory corresponding to each rhythm sound source and generates rhythm sound signals corresponding to each rhythm sound source; It is composed of;

The present invention will be explained in more detail below with reference to embodiments shown in the accompanying drawings.

FIG. 1A shows a first embodiment of the invention, in which the output terminal of a clock generator 1 having a variable resistor 3 is connected to the input side of an address generator 4. In FIG. The movable contact of the start switch 2 is grounded, and the fixed contact is connected on one side to a constant voltage source +V via a resistor, and on the other hand to the reset terminal R of the clock generator 1 and the reset terminal R of the address generator 4, respectively. ing. The output side of the address generator 4 is connected on the one hand to the address input side of the random access memory 6 and on the other hand to the read address input side of the read-only memory 7. Further, the write input terminal group A1 to An of the random access memory 6 is configured so that a logic value "1" is inputted through the corresponding automatic return type switches S1 to Sn of the pattern forming switch section 5, respectively. ing. The output side of the read-only memory 7 is connected on one side to a first input terminal of an AND circuit 10, and on the other side is grounded via a resistor and a light emitting diode 9. Further, among the readout output terminal groups B1 to Bn of the random access memory 6, the first output terminal B1 is connected to the second input terminal of the OR circuit 11, and the other output terminal groups B2 to Bn are directly connected to the rhythm sound source circuit 12. is connected to the input terminal group C2 to Cn. Furthermore, the write/read command terminal W/R of the random access memory 6 is connected to the write/read designation switch 8.
A logic value "1" is input to the fixed contact W of the write/read designation switch 8, and a logic value "0" is input to the fixed contact R. Further, the movable contact of the write/read designation switch 8 is connected to the second input terminal of the AND circuit 10, and the output side of the AND circuit 10 is connected to the OR circuit 11.
is connected to the first input terminal of. The output side of this OR circuit 11 is connected to the first input terminal C1 of the rhythm sound source circuit 12.

The output side of the rhythm sound source circuit 12 is connected to a sound system 13 consisting of an amplifier, speakers, and the like.

Here, the clock generator 1 generates a clock pulse by adjusting the variable resistor 3.
It is configured so that the cycle of CP occurrence is adjusted.
Further, the address generator 4 is composed of a counting circuit consisting of, for example, a shift register or a combination of a counter and a decoder, and counts the clock pulses CP generated by the clock generator 1, and connects a corresponding output line according to the counted value. address signal
ADi (i=1, 2...m) (logical value "1") is output. The read-only memory 7 stores desired rhythm patterns in advance, and is configured to sequentially read out the stored rhythm patterns as the rhythm pattern signal rP upon receiving the read address signal ADi output from the address generator 4. ing.

The random access memory 6 enters a writable state when a logical value "1" is input to its write/read command terminal W/R, and a switch S1 is applied to each of the write input terminals A1 to An of the random access memory 6. The logical value "1" which is appropriately inputted by opening and closing of ~Sn is sequentially stored in the addresses designated by the address generator 4 as a rhythm pattern. Here, the random access memory 6 has m×n addresses as shown in FIG. 1B, and each address has coordinates (i,
j) Indicated by i=1, 2...m, j=1, 2...n. Each of these addresses is connected to the address signal ADi
(i=1, 2...m) is specified as follows.
That is, n addresses (1, 1) (1, 2)...(1, n) in the first column of the random access memory 6 are specified by the address signal AD1 (logical value "1"), and generally is the n address (i, j) in the i-th column, j = 1, 2, by the address signal ADi.
...n is specified. Therefore, each address signal ADi
A group of signals with logical value "1" that are sequentially input to the input terminal A1 of the random access memory 6 in synchronization with
m addresses (1, 1) in the first line of Figure 1B
(2, 1)...(m, 1) are stored as one rhythm pattern. Generally, each address signal
A group of signals with a logic value "1" sequentially input to the input terminal Aj in correspondence with ADi, i=1, 2...m are m addresses (i, j) of the j-th row, i=1 , 2...
m is stored as one rhythm pattern. That is, the illustrated random access memory 6 has the ability to store one rhythm pattern corresponding to each of the input terminals Ai, for a total of n types of rhythm patterns. Further, the random access memory 6 becomes readable when logic "0" is input to the write/read command terminal W/R, and the address signal ADi, i=1, 2, . . . is output from the address generator 4. According to m, n types of rhythm patterns already stored are read out from the read output terminals B1 to Bn as rhythm pattern signals RP1 to RPn, respectively. The rhythm sound source circuit 12 has a function of simultaneously outputting n types of rhythm sound signals, and each of the input terminals C1 to Cn is configured as an input terminal for rhythm pattern signals RP1 to RPn for one rhythm sound. . For example, the first input terminal C1 corresponds to a cymbal, the second input terminal C2 corresponds to a bass drum, and each of the input terminals C1 to Cn corresponds to one rhythm sound. Therefore, for example, the rhythm pattern signal RP of logical value "1" is input from the random access memory 6 to the first input terminal C1.
1 is input sequentially, the rhythm pattern signal RP
A cymbal rhythm sound signal is generated according to No. 1.

The effects of the first embodiment of the present invention having the above configuration will be described next.

When the start switch 2 is set to the "open" position, a positive voltage +V is applied to the reset terminal R of the clock generator 1 and the address generator 4, so that the clock generator 1 and the address generator 4 are connected to each other. 4 are both in the reset state. Therefore, the automatic rhythm playing device is in a stopped state.

In the following description, for convenience, a rhythm pattern writing operation for writing a rhythm pattern into the random access memory 6 and a rhythm pattern reading operation for reading it will be explained separately.

Rhythm pattern writing operation When a performer writes and sets a rhythm pattern in the random access memory 6, the player first writes and sets the rhythm pattern.
The read designation switch 8 is set to the fixed contact W side. As a result, the logical value "1" is input to the write/read command terminal W/R of the random access memory 6, so that the random access memory 6 becomes in a writable state. Next, when the start switch 2 is turned on, the reset terminals R of the clock generator 1 and the address generator 4 are grounded, so that both the clock generator 1 and the address generator 4 are released from the reset state. Therefore, the clock generator 1 starts generating clock pulses CP, and the address generator 4 sequentially counts the clock pulses CP and addresses a logical value "1" to one output line corresponding to the counted value. Signal ADi, i=1,
2... m are output sequentially. Therefore, the same address signal ADi (logical value "1") is input to the address input sides of the random access memory 6 and the read-only memory 7. The read-only memory 7 receives this address signal ADi and sequentially outputs pre-stored predetermined rhythm patterns as a rhythm pattern signal rP. The light emitting diode 9 receives this rhythm pattern signal rP and starts blinking according to the predetermined rhythm pattern. Further, this rhythm pattern signal rP is input to the first input terminal of the AND circuit 10. At this time, since the logical value "1" is input to the second input terminal of the AND circuit 10 via the write/read designation switch 8, the AND condition is established in the AND circuit 10, and the rhythm pattern signal rP is Circuit 10 and OR circuit 1
1 to the first input terminal C1 of the rhythm sound source circuit 12. Therefore, the sound source circuit (cymbal sound) corresponding to the first input terminal C1 of the rhythm sound source circuit 12 is driven in synchronization with the blinking of the light emitting diode 9, and the above-mentioned rhythm pattern signal stored in the read-only memory 7 is driven. In response to rP, the sound system 13 starts generating musical cymbal sounds.

The performer detects the address signal ADi (i=1 to m) by sensing with his eyes and ears the flashing of the light emitting diode 9 and the sound of the cymbal sound, which occur in synchronization.
can sense the tempo of occurrence. The reason for this is that, as mentioned above, the blinking period of the light emitting diode 9 and the sounding period of the cymbal sound are different from each other in the read-only memory 7.
Address signal ADi input to i=1, 2...m
This is because it is determined by the rhythm pattern signal rP read out from the read-only memory 7. Therefore, the performer detects the generated tempo of the address signal ADi by the blinking of the light emitting diode and the sound of the cymbal, and by appropriately turning on each of the switches S1 to Sn of the pattern forming switch section 5 according to the generated tempo. Therefore, n types of rhythm patterns can be stored in the random access memory 6.

On the other hand, the address signal ADi is input from the address generator 4 to the random access memory 6 every moment. Therefore, if the switch Sj in the rhythm pattern forming switch section 5 is turned on at a certain timing and the address signal ADi is input from the address generator 4 at that timing, the i-th signal in the j-th row of the random access memory 6 is Switch Sj at the th address (i, j)
A rhythm pattern corresponding to this is written.

In other words, when a performer wants to write a specific rhythm pattern at a specific timing during a performance, by turning on the switch Sj corresponding to that specific rhythm pattern and specifying a row, the address signal ADi representing that timing is written. The column is specified by , and as a result, the random access memory 6
The above specific rhythm pattern is written at address (i, j) inside.

At this time, if it is difficult to operate all the switches S1 to Sn of the pattern forming switch section 5 in one rhythm pattern writing operation, the above-described rhythm pattern writing operation may be repeated several times. However, in this case, it is necessary to take measures to prevent the rhythm patterns already written in each row of the random access memory 6 from being erased by the repeated rhythm pattern writing operations. As an example, a row of writable random access memory 6 (each switch S1 to Sn
) corresponding to the random access memory 6 can be specified from outside the random access memory 6.
All you have to do is configure. In addition, if the generation speed of the address signal ADi is fast and the tempo of rhythm pattern writing (blinking of the light emitting diode 9 and the cymbal sound generation period) is too fast for the performer, the clock generator 1 may be By adjusting the cycle of the clock pulses generated by adjusting the variable resistor 3, the address signal ADi that is sequentially output from the address generator 4 is generated slowly, and the writing tempo of the rhythm pattern is slowed down. good.

Rhythm Pattern Reading Operation When a performer reads a rhythm pattern from the random access memory 6 and performs it, first the write/read designation switch 8 is set to the fixed contact R side. As a result, the logical value "0" is input to the write/read command terminal W/R of the random access memory 6, so that the random access memory 6 becomes readable. Next, when the start switch 2 is turned on, the reset terminals R of the clock generator 1 and address generator 4 are both grounded, so that both the clock generator 1 and the address generator 4 are released from the reset state. Therefore, the clock generator 1 starts generating clock pulses CP, and the address generator 4 sequentially counts the clock pulses CP and sends a logical value "1" to the output line corresponding to the counted value as the address signal ADi. i=1, 2...m
Output as . Since the random access memory 6 is in a readable state as described above, upon receiving this address signal ADi (logical value "1"), the n types of rhythm patterns stored in the rhythm pattern writing operation are transferred to the rhythm pattern signals RP1 to RPn. They are output from the read output terminals B1 to Bn, respectively. For example, at the "specific timing" mentioned in writing, the address signal ADi is input from the address generator 4 and the column i in the random access memory 6 to be read is specified. This column i has row j, ie address (i,
j) has a ``specific rhythm pattern'' written in it, so it is read out. This “specific rhythm pattern” can be switched by the performer at that “specific timing” when writing.
This is specified by inserting Sj. The rhythm sound source circuit 12 receives the rhythm pattern signals RP1 to RPn at input terminals C1 to Cn, respectively (only the rhythm pattern signal RP1 passes through the OR circuit 11).
N types of rhythm sound signals are sequentially output according to each rhythm pattern signal RP1 to RPn. These n types of rhythm sound signals are input to the sound system 13, and as a result, they are produced according to each rhythm pattern stored in the random access memory 6.

At this time, since the address signal ADi is also input to the read-only memory 7, the read-only memory 7 outputs the rhythm pattern signal rP. However, this rhythm pattern signal rP is blocked by the AND circuit 10 and sent to the rhythm sound source circuit 12 because the logical value "0" is input to the second input terminal of the AND circuit 10 and the AND condition is not satisfied in the AND circuit 10. is not input to input terminal C1. Therefore, the rhythm sound generation by the rhythm pattern stored in the random access memory 6 is not affected in any way.

FIG. 2 shows a second embodiment of the present invention, in which an automatic rhythm playing device is provided with a synchronized start function with an electronic musical instrument. The synchronized start function is a function that automatically drives the automatic rhythm performance device at the same time as the electronic musical instrument starts playing, when the performer uses both the automatic rhythm performance device and the electronic musical instrument to perform. In rhythm performance devices that are not equipped with this synchronized start function, the timing of the key press on the electronic musical instrument and the start time of the rhythm performance device often do not match, and it is inevitable that the start of the performance will be very unnatural. . Incidentally, in FIG. 2, the same parts as in FIG. 1 are given the same reference numerals, and the explanation thereof will be omitted. Furthermore, the clock generator 1 in FIG. 1 is replaced with an oscillator 1 whose oscillation frequency can be adjusted by a variable resistor 3.
The address generator 4 in the figure is composed of a shift register 4.

In FIG. 2, the movable contact of the start switch 2 is connected to a positive voltage source +V, and its fixed contact is connected to one end of a capacitor 22. The other end of the capacitor 22 is connected to the second input terminal of the OR circuit 24 on one side and the resistor 23 on the other side.
It is grounded through. A logic value "1" is input to one end of the automatic return type stop switch 21, and the other end is connected to the first input terminal of the OR circuit 24. The output side of the OR circuit 24 is connected to a set terminal S of an RS type flip-flop 27. The pattern forming switch section 5 is a switch S.
The logic value "1" is input to one end of each switch S1 to Sn, Sn+1, and the other end is connected to the input side of the OR circuit 26, respectively. Further, the signal line 25 is led from the electronic musical instrument, and is a key-on signal generated when a certain key is pressed in the electronic musical instrument.
KON (logical value “1”) is supplied.
This signal line 25 is connected to the input side of an OR circuit 26. Further, the other ends of each of the switches S1 to Sn of the pattern forming switch section 5 are connected to each of the write input terminals A1 to An of the random access memory 6, as in the first embodiment. The output terminal Q of the flip-flop 27 is connected on one side to the oscillator 1 and the reset terminal R of the shift register 4, respectively, and on the other side to the input side of the differentiating circuit 28. In this case, the differentiating circuit 28 is configured to generate a pulse only in response to a change in the input signal from logical value "1" to "0". The output side of the differentiating circuit 28 is connected to a second input terminal of an OR circuit 30 via a delay circuit 29. Further, the output side of the oscillator 1 is connected to a first input terminal of an OR circuit 30, and the output side of the OR circuit 30 is connected to a shift input terminal S of a shift register 4. Further, each output line of the shift register 4 is connected to a random access memory 6 on the other hand as in the first embodiment.
and the read address input side of the read-only memory 7, and the other end is connected to the input terminal C of the shift register 4 via a NOR circuit 31. Hereinafter, for convenience, the rhythm pattern writing operation and the rhythm pattern reading operation will be explained separately.

Rhythm Pattern Writing Operation When a performer writes and sets a rhythm pattern, first, the write/read designation switch 8 is turned on to the fixed contact W side. As a result, the random access memory 6 becomes writable as in the first embodiment. Next, start switch 2
Input and set. As a result, the positive voltage +V is differentiated by a differentiating circuit including a capacitor 22 and a resistor 23, and one pulse is formed. This pulse is input to the set terminal S of the flip-flop 27 via the OR circuit 24. Therefore, the output terminal Q of the flip-flop 27 has a logic value of "1" (positive potential).
Output. Oscillator 1 and shift register 4 receive this logical value "1" at their reset terminals R and are reset together. In this case, the differentiating circuit 28 also receives this logic value "1", but as described above, the differentiating circuit 28 is configured to function in response to a change from the logic value "1" to the logic value "0". Therefore, the differentiating circuit 28 does not operate and does not generate pulses. Therefore, the shift register 4 maintains the reset state, and all the outputs of each stage appearing on the output side of the shift register 4 have a logical value of "0". Therefore, the logic value "1" is input to the input terminal C of the shift register 4 via the NOR circuit 31.

Next, depending on the performer, switches S1 to Sn, Sn
When at least one of the +1 switches is turned on, a logical value "1" is input to the OR circuit 26. Here, as an example, it is assumed that the switch S1 is set to be on. By turning on the switch S1, a logic value "1" is input to the reset terminal R of the flip-flop 27, whereby the flip-flop 27 is inverted and the output terminal Q outputs a logic value "0". Therefore, the logic value "0" is input to the reset terminal R of the oscillator 1 and the shift register 4, and the reset state of both is released.

At the same time, the change in the output terminal Q of the flip-flop 27 from the logical value "1" to the logical value "0" is input to the differentiating circuit 28, so that the differentiating circuit 28 generates one pulse. This pulse is transmitted to the delay circuit 2
9, the OR circuit 30
The signal is inputted to the shift input terminal S of the shift register 4 via. As mentioned above, the input terminal C of the shift register 4 receives the logic value "1" through the NOR circuit 31.
is input, so when the above pulse is input to the shift input terminal S, the logic value "1" is stored in the first stage of the shift register 4. in this case,
Since the delay time by the delay circuit 29 is set to be very short, a logic value "1" is stored in the first stage of the shift register 4 almost at the same time as the switch S1 is turned on. Therefore, shift register 4
is the first one almost at the same time as switch S1 is turned on.
Address signal AD1 (logical value “1”) is output to the output line of
Output. This address signal AD1 specifies the n addresses (1, 1), (1, 2), . . . (1, n) in the first column of the random access memory 6 and makes them writable. In this case, since the switch S1 is turned on as described above, the logical value "1" is stored at the address (1, 1).

The above explanation deals with the case where only the switch S1 is set to close, but even if multiple switches are set to close, the output from these switches to the random access memory 6 is done in exactly the same way. The logical value “1” is stored at each address (1, j) j=1, 2 . . . n in the first column of the random access memory 6. here,
For switch Sn+1, the first beat of the rhythm pattern is n.
This type of rhythm sound is used when all of the rhythm sounds are rests.

In parallel with the above operation, the reset state of the oscillator 1 is released. Therefore, the oscillator 1 starts generating clock pulses CP, and the generated clock pulses CP are sequentially input to the shift input terminal S of the shift register 4 via the OR circuit 30. The shift register 4 follows this clock pulse CP,
The logical value “1” stored in the first stage is transferred to the second stage.
Shift to the third stage one after another. As a result, the shift register 4 receives the address signal ADi,i.
=2, 3...m are output one after another. At this time, the address signal is input to the input terminal C of the shift register 4.
Since ADi, i=1, 2...m (logical value "1") is inverted by the NOR circuit 31, the logical value "0" is input. Therefore, only one initially written logic value "1" exists in the shift register 4, and as described above, this is sequentially shifted to form the address signal ADi.

The subsequent rhythm pattern writing operation is performed in exactly the same manner as in the first embodiment. That is, the performer operates the rhythm pattern forming switch 5 while sensing with his/her eyes and ears the blinking of the light emitting diode 9 and the sound generation of the silval tone, which occur in synchronization with each other, to store n different rhythm tones in the random access memory 6. Rhythm patterns can be memorized.

Rhythm Pattern Reading Operation When a performer reads a rhythm pattern from the random access memory 6 and performs it, he or she first sets the write/read designation switch 8 to the fixed contact R side. As a result, the random access memory 6 becomes readable as in the first embodiment. Next, the performer turns on the start switch 2. As a result, the oscillator 1 and shift register 4 are brought into a reset state, just as in the rhythm pattern writing operation of the second embodiment described above. At this time, all outputs of each stage of the shift register 4 have a logical value of "0".

Next, when the performer presses a key on the electronic musical instrument to start playing, a key-on signal KON (logical value "1") is output from the electronic musical instrument to the signal line 25 at this moment. Since this key-on signal KON is inputted to the reset terminal R of the flip-flop 27 via the OR circuit 26, the flip-flop 27 is inverted and its output terminal Q outputs a logic value "0". Therefore, the logic value "0" is input to the reset terminal R of the oscillator 1 and the shift register 4, and the reset state of both is released.At this time, the output terminal Q of the flip-flop 27 changes from the logic value "1" to the logic value "0". Since the change to 0'' is input to the differentiating circuit 28, the differentiating circuit 28 generates one pulse.This pulse is sent to the delay circuit 29 and the OR circuit 30, just as in the rhythm pattern writing operation described above. Since the logic value "1" is input to the input terminal C of the shift register 4 via the NOR circuit 31, the first stage of the shift register 4 The logic value "1" is stored. In this case, since the delay time of the delay circuit 29 is set to be very short as described above, the shift register 4 simultaneously stores the address signal AD1 (the logic value "1") when the key of the electronic musical instrument is pressed. 1"). This address signal AD1 causes n addresses (1, 1) in the first column of the random access memory 6 to be output.
(1, 2)..., (1, n) are specified and their contents are output as rhythm pattern signals RP1 to RPn.

In parallel with the above operation, the reset state of the oscillator 1 is released. Therefore, the shift register 4 starts generating clock pulses CP, and the generated clock pulses CP are sequentially input to the shift input terminal S of the shift register 4 via the OR circuit 30. The shift register 4 sequentially shifts the logic value "1" stored in the first stage to the second and third stages in accordance with this clock pulse CP. As a result, the address signal ADi (i=2, 3...m)
are output one after another.

Address signals ADi generated sequentially in this way
With i=2, 3...m, n types of rhythm patterns stored in each column of the random access memory 6 by a rhythm pattern writing operation are read out one after another as rhythm pattern signals RP1 to RPn.
The rhythm sound source circuit 12 is driven by the rhythm pattern signals RP1 to RPn, and various rhythm sounds are generated from the sound system 13, just as in the first embodiment.

When the performance is finished, press stop switch 2.
By pressing 1, a logic value "1" is input to the set terminal S of flip-flop 27.
Therefore, flip-flop 27 is inverted and its output terminal Q outputs a logic value "1". As a result, both the oscillator 1 and the shift register 4 are reset again.

As is clear from the above description, according to the second embodiment of the present invention, the key-on signal KON (logical value "1") is output to the signal line 25 at the same time as the key of the electronic musical instrument is pressed, and this causes the shift. Since the register 4 is configured to output the address signal AD1, the automatic rhythm playing device is driven at the same time as the key is pressed. Therefore, a synchronized start with a so-called electronic musical instrument can be performed reliably.

Incidentally, the first and second aspects of this invention described in detail above
In this embodiment, the pattern forming switch section 5 may be specially provided as a manual switch or a foot switch on the main body of the electronic musical instrument so that the player can easily operate it. Furthermore, each key of the electronic musical instrument may be appropriately associated with a cymbal sound, a bass drum sound, etc., and each key may be used as the pattern forming switch section 5 only during the rhythm pattern writing operation. Furthermore, in this invention, by increasing the storage capacity of the random access memory 6 (for example, by configuring the random access memory 6 with a plurality of memory chips), it is possible to not only store rhythm patterns for one song, but also to store rhythm patterns for one song. It is also possible to store a plurality of different rhythm patterns so that the performer can perform different songs in succession. In this case, the random access memory 6 is divided into a plurality of groups (for example, when the random access memory 6 is composed of a plurality of chips, each chip may be treated as one group), and each group is divided into two or more groups. A designation switch for designation may be provided in the random access memory 6.

As is clear from the above description, the automatic performance device according to the present invention uses a writable storage means to write and read out rhythm patterns, thereby setting and playing an arbitrary rhythm pattern according to the performer's will. making it possible to do so.
In addition, the sound generation timing (column) and sound source type (row) for specifying the storage position in the storage means is automatically advanced at a predetermined period based on the output from the clock generation means. This eliminates the need for manual input and reduces the number of controls for inputting memory locations. Furthermore, by displaying the output signal from the clock generating means or the address generating means as a rhythm tempo, the timing of sound generation can be easily sensed. Therefore, according to the apparatus of the present invention, the performer can freely and easily set or change the rhythm pattern, and furthermore, the player can easily and quickly perform the settings or changes while performing the performance. Furthermore, the device can also be made much smaller than conventional devices.

[Brief explanation of the drawing]

FIG. 1A is a block diagram showing a first embodiment of this invention, FIG. 1B is an explanatory diagram showing the contents of a random access memory, and FIG. 2 is a block diagram showing a second embodiment of this invention. be. 1...Clock generator, 2...Start switch, 4...Address generator, 5...
Pattern formation switch section, 6... Random access memory, 7... Read only memory, 8...
Write/read designation switch, 9... Light emitting diode, 10... AND circuit, 11, 24, 2
6, 30...OR circuit, 12...Rhythm sound source circuit, 13...Sound system, 21...Stop switch, 28...Differentiating circuit, 29...Delay circuit, KON...Key-on signal, ADi...Address signal, RP1~RPn...Rhythm pattern signal.

Claims (1)

[Scope of Claims] 1. A clock generating means for generating a frequency signal of a predetermined period; an address generating means for generating an address signal based on the output signal from the clock generating means; and a number of operations corresponding to at least the number of rhythm sound sources. Write and read addresses are specified by the address signal generated by the pattern input means having a child and the address signal generated by the address generation means, and a rhythm pattern corresponding to each rhythm sound source is written by opening and closing each operator of the pattern input means. Rhythm tempo display means for representing a rhythm tempo by an output signal from the clock generation means or address generation means; and outputting a plurality of rhythm sound signals in response to the plurality of rhythm pattern signals read from the storage means. An automatic rhythm performance device characterized by comprising a rhythm sound source circuit that performs a rhythm sound source circuit.