JPH0631983B2 - Automatic rhythm playing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an automatic performance device, and more specifically, a performer can set a rhythm by himself / herself while listening to a tempo sensed sound automatically generated. The present invention relates to a type of automatic rhythm playing device.

[Prior Art] Conventionally, there is an automatic rhythm playing device in which a player arbitrarily writes a rhythm in a storage device such as a RAM and can perform a rhythm performance according to the written rhythm. In such an automatic rhythm playing device, when an automatic rhythm is created, an LED or a lamp is turned on in synchronization with the beat timing for the purpose of detecting the tempo and the input timing when inputting to the performer. It is easy to operate.

[Problems to be Solved by the Invention] However, in such an automatic rhythm playing device, since tempo and timing are detected only by light display, there is a disadvantage that it is difficult to set a timing to be input. That is, humans usually take a rhythm tempo with sound, and it was very difficult to obtain accurate timing only with light.

The present invention has been made to eliminate the above-mentioned drawbacks of the conventional automatic rhythm playing device, and has a simple structure.
It is an object of the present invention to provide an automatic rhythm playing device that makes it easy to grasp the tempo and the timing to be input.

[Means and Actions for Solving the Problems] In order to achieve this object, an automatic rhythm playing device according to the present invention has a clock generating means for generating a clock signal of a predetermined cycle, a performance operation switch means, and a writing state. Write / read switch means for switching the read state; memory means for writing and reading performance data;
When the writing state is designated by the writing / reading switch means, the writing means writes the performance data in the memory means in real time based on the clock signal generated by the clock generating means in response to the operation of the performance operating switch means. Reading means for reading performance data from the memory means based on a clock signal generated by the clock generating means when a read state is designated by the write / read switch means, and performance data read by the reading means Sound source means for generating a musical tone based on the above, a tempo sensing sound generating means for generating a tempo sensing sound based on a clock signal generated by the clock generating means, and a writing state in association with the state of the writing / reading switch means. When the tempo is Together to generate a thiine, when the read state is characterized in that a control means for controlling so as not to generate tempo sensing sound to the tempo sensing sound generating means.

According to the above configuration, the tempo sensing sound is generated when writing the performance data, while the tempo sensing sound is prohibited when reading the performance data.

[Embodiment] The present invention will be described in more detail with reference to an embodiment shown in the accompanying drawings.

FIG. 1A shows a first embodiment of the present invention,
The output terminal of the clock generator 1 having the variable resistor 3 is connected to the input side of the address generator 4.
The movable contact of the start switch 2 is grounded, the fixed contact is connected to the constant voltage source + V via a resistor on one side, and is connected to the reset terminal R of the clock generator 1 and the reset terminal R of the address generator 4 on the other side. The output side of the address generator 4 is connected on one side to the address input side of the random access memory 6 and on the other side to the read address input side of the read only memory 7. Further, the write input terminal groups A1 to An of the random access memory 6 are configured so that the logical value "1" is input via the corresponding automatic restoration type switches S1 to Sn of the pattern forming switch section 5, respectively. ing. Read only memory 7
The output side of is connected to the first input terminal of the AND circuit 10 on the one hand, and is grounded via the resistor and the light emitting diode 9 on the other hand. In addition, the first output terminal B1 of the read output terminal groups B1 to Bn of the random access memory 6 is connected to the second input terminal of the OR circuit 11,
The other output terminal groups B2 to Bn are directly connected to the input terminal groups C2 to Cn of the rhythm sound source circuit 12. Further, the write / read command terminal W / R of the random access memory 6
Is connected to the movable contact of the write / read designation switch 8, and the fixed contact W of the write / read command switch 8
A logical value "1" is input to the circuit contact R and a logical value "0" is input to the circuit contact R. The movable contact of the write / read designation switch 8 is connected to the second input terminal of the AND circuit 10, and the output side of the AND circuit 10 has the OR circuit 1
1 is connected to the first input terminal. This OR circuit 1
The output side of 1 is the first input terminal C1 of the rhythm sound source circuit 12.
It is connected to the.

The output side of the rhythm sound source circuit 12 is connected to a sound system 13 including an amplifier and a speaker.

Here, the clock generator 1 is configured such that the generation cycle of the clock pulse CP generated by adjusting the variable resistor 3 is adjusted. The address generator 4 is composed of, for example, a counting circuit including a shift register or a combination of a counter and a decoder, counts the clock pulses CP generated by the clock generator 1, and addresses the corresponding output line in accordance with the counted value. The signal ADi (i = 1, 2, ... M) (logical value “1”) is output. A desired rhythm pattern is stored in advance in the read-only memory 7, and the address generator 4
The rhythm pattern stored in response to the read address signal ADi output from the rhythm pattern signal rP is sequentially read.

The random access memory 6 becomes writable when a logical value “1” is input to the write / read command terminal W / R, and switches S1 to Sn are provided to the write input terminals A1 to An of the random access memory 6, respectively.
The logical value "1", which is appropriately input by opening and closing, is sequentially stored as rhythm patterns in the addresses designated by the address generator 4. Here, the random access memory 6 has m × n addresses as shown in FIG. 1B, and each address has coordinates (i, j) i = 1,
2 ... m, j = 1, 2 ... n. Each of these addresses is designated by the address signal ADi (i = 1, 2, ... M) as follows. That is, the first of the random access memory 6 is generated by the address signal AD1 (logical value "1").
N addresses in the column (1, 1) (1, 2) ... (1,
n) is designated, and generally n addresses (i, j) in the i-th column, j = 1, 2, ...
Is specified. Therefore, the signal group of the logical value "1" sequentially input to the input terminal A1 of the random access memory 6 in synchronization with each address signal ADi is the m number of addresses (1, 1) (2, 1) ... 1 for (m, 1)
It is stored as one rhythm pattern. Generally, a signal group of logical value "1" sequentially input to the input terminal Aj corresponding to each address signal ADi, i = 1, 2, ... j), i = 1, 2 ... 1 for m
It is stored as one rhythm pattern. That is, the illustrated random access memory 6 has the ability to store one rhythm pattern corresponding to each of the input terminals Ai and a total of n types of rhythm patterns. The random access memory 6 has a write / read command terminal W.
When the logical value "0" is input to / R, the state becomes readable and the n kinds of rhythm patterns already stored according to the address signals ADi, i = 1, 2, ... From the output terminals B1 to Bn respectively.
It is configured to read as RPn. The rhythm sound source circuit 12 has a function of simultaneously outputting n types of rhythm sound signals, and each of the input terminals C1 to Cn has rhythm pattern signals RP1 to PRn for one rhythm sound.
Is configured as an input terminal of. For example, the first input terminal C1 corresponds to a cymbal, the second input terminal C2 corresponds to a bass drum, and each of the input terminals C1 to Cn corresponds to one rhythm sound. Therefore, for example, when the rhythm pattern signal RP1 having the logical value "1" is sequentially input from the random access memory 6 to the first input terminal C1, the cymbal rhythm sound signal is generated according to the rhythm pattern signal RP1.

The operation and effect of the first embodiment of the present invention having the above configuration will be described below.

When the start switch 2 is set to the "open" position, the clock generator 1 and the address generator 4
Since a positive voltage + V is applied to the reset terminal R of the clock generator 1 and the address generator 4,
Are both in reset. Therefore, the automatic rhythm playing device is in a stopped state.

In the following description, the random access memory 6 is used for convenience.
The rhythm pattern writing operation for writing the rhythm pattern and the rhythm pattern reading operation for reading the rhythm pattern will be described separately.

Rhythm Pattern Writing Operation When the performer writes and sets a rhythm pattern in the random access memory 6, first, the writing / reading designation switch 8 is set to the fixed contact W side. As a result, the logical value "1" is input to the write / read command terminal W / R of the random access memory 6, so that the random access memory 6 becomes writable. Next, when the start switch 2 is turned on, the reset terminals R of the clock generator 1 and the address generator 4 are grounded, so that both the clock generator 1 and the address generator 4 are released from the reset state.
Therefore, the clock generator 1 outputs the clock pulse CP
, The address generator 4 sequentially counts this clock pulse CP, and the count value corresponds to 1
The logical value "1" is applied to the output line of the book as the address signal ADi, i =
It is sequentially output as 1, 2, ... M. Therefore, the same address signal ADi (logical value “1”) is input to the address input sides of the random access memory 6 and the read only memory 7. The read-only memory 7 receives the address signal ADi and sequentially outputs a predetermined rhythm pattern stored in advance as a rhythm pattern signal rP.
The light emitting diode 9 receives this rhythm pattern signal rP and starts blinking in the predetermined rhythm pattern. Further, the rhythm pattern signal rP is input to the first input terminal of the AND circuit 10. At this time, since the logical value “1” is input to the second input terminal of the AND circuit 10 via the write / read designation switch 8, the AND condition is satisfied in the AND circuit 10, and the rhythm pattern signal rP is ANDed. It is input to the first input terminal C1 of the rhythm tone generator circuit 12 via the circuit 10 and the OR circuit 11. Therefore, the sound source circuit (cymbal sound) corresponding to the first input terminal C1 of the rhythm sound source circuit 12 is driven in synchronization with the blinking of the light emitting diode 9, and the rhythm pattern signal rP stored in the read-only memory 7 is driven. Corresponding to the sound system 13
Starts to produce the cymbal sound.

The performer senses the blinking of the light emitting diode 9 and the pronunciation of the cymbal sound, which occur in synchronization with each other, by the eyes and ears,
It is possible to detect the tempo at which the address signal ADi (i = 1 to m) is generated. The reason is that, as described above, the blinking period of the light emitting diode 9 and the sounding period of the cymbal sound are input to the read-only memory 7 by the address signals ADi, i =
This is because the rhythm pattern signal rP read from the read-only memory 7 by 1, 2, ... M. Therefore, the performer senses the tempo at which the address signal ADi is generated by blinking the light emitting diode and the cymbal sound, and according to the tempo at which the pattern forming switch unit 5 is formed.
By appropriately turning on each switch S1 to Sn of
The random access memory 6 can store n types of rhythm patterns.

On the other hand, from the address generator 4, the address signal ADi
Are input to the random access memory 6 every second.
Therefore, at a certain timing, the switch Sj in the rhythm pattern forming switch unit 5 is turned on, and at that timing, the address signal A from the address generator 4 is generated.
If Di is input, the rhythm pattern corresponding to the switch Sj is written at the i-th address (i, j) in the j-th row of the random access memory 6.

That is, when the player wants to write a specific rhythm pattern at a specific timing during performance, the switch Sj corresponding to the specific rhythm pattern is turned on to specify a row, and an address signal A representing that timing is represented.
The column is designated by Di, and the specific rhythm pattern is written at the address (i, j) in the random access memory 6 determined as a result.

At this time, when it is difficult to operate all the switches S1 to Sn of the pattern forming switch section 5 by one rhythm pattern writing operation, the above rhythm pattern writing operation may be repeated several times. However, in this case, it is necessary to take measures so that the rhythm pattern already written in each row of the random access memory 6 is not erased by the repeated rhythm pattern writing operation. As an example thereof, a row of the writable random access memory 6 (corresponding to each of the switches S1 to Sn) can be designated from outside the random access memory 6,
The random access memory 6 may be configured. Further, when the generation speed of the address signal ADi is high and the tempo of writing the rhythm pattern (blinking of the light emitting diode 9 and sounding cycle of the cymbal sound) is too fast for the performer, the variable resistor 3 provided in the clock generator 1 is used. It is sufficient to adjust the period of the clock pulse that is generated by adjusting, and thereby slowly generate the address signal ADi that is sequentially output from the address generator 4 to slow down the writing tempo of the rhythm pattern.

Rhythm Pattern Reading Operation When the performer reads and plays a rhythm pattern from the random access memory 6, first, the write / read designation switch 8 is set to the fixed contact R side. As a result, the logical value "0" is input to the write / read command terminal W / R of the random access memory 6, so that the random access memory 6 becomes ready for reading.
Next, when the start switch 2 is turned on, the reset terminals R of the clock generator 1 and the address generator 4 are both grounded, so that both the clock generator 1 and the address generator 4 are released from the reset state.
Therefore, the clock generator 1 outputs the clock pulse CP
Of the clock pulse CP, the address generator 4 sequentially counts the clock pulse CP and outputs a logical value "1" to the output line corresponding to the count value as the address signal ADi, i = 1, 2
Output as m. Since the random access memory 6 is in the readable state as described above, the n kinds of rhythm patterns stored in the rhythm pattern writing operation in response to the address signal ADi (logical value “1”) are stored in the rhythm pattern signals RP1 to RPn. Are output from the read output terminals B1 to Bn, respectively. For example, at the “specific timing” mentioned at the time of writing, the address signal ADi is input from the address generator 4 and the column i to be read in the random access memory 6 is designated. Since the "specific rhythm pattern" is written in the row j, that is, the address (i, j) in this column i, it is read out. This "specific rhythm pattern" is specified by the player by turning on the switch Sj at the "specific timing" at the time of writing. The rhythm sound source circuit 12 uses this rhythm pattern signal RP
1 to RPn are received at the input terminals C1 to Cn respectively (only the rhythm pattern signal RP1 is passed through the OR circuit 11).
The rhythm sound signals of various types are sequentially output. The n kinds of rhythm sound signals are input to the sound system 13 and, as a result, sounded according to each rhythm pattern stored in the random access memory 6.

At this time, the read-only memory 7 also receives the address signal A
Since Di is input, the read-only memory 7 outputs the rhythm pattern signal rP. However, this rhythm pattern signal rP is cut off by the AND circuit 10 because the logical value “0” is input to the second input terminal of the AND circuit 10 and the AND condition is not satisfied in the AND circuit 10. Is not input to the input terminal C1. Therefore, there is no influence on the rhythm sound generation by the rhythm pattern stored in the random access memory 6.

FIG. 2 shows a second embodiment of the present invention in which an automatic rhythm playing device is provided with a function for synchronizing with an electronic musical instrument. The synchro start function is a function of automatically driving the automatic rhythm playing device at the same time when the player starts playing the electronic musical instrument when the player uses both the automatic rhythm playing device and the electronic musical instrument. In a rhythm playing device that does not have this synchro start function, it is unavoidable that the key pressing of an electronic musical instrument does not coincide with the start of the rhythm playing device, which makes the playing start very unnatural. . In FIG. 2, the same parts as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. Further, the clock generator 1 in FIG. 1 is replaced with an oscillator 1 of the type whose oscillation frequency can be adjusted by a variable resistor 3, and the address generator 4 in FIG.

In FIG. 2, the movable contact of the start switch 2 is connected to the positive voltage source + V, and its fixed contact is the capacitor 2
2 is connected to one end. The other end of the capacitor 22 is connected to the second input terminal of the OR circuit 24 on the one hand and is grounded via the resistor 23 on the other hand. The logical value "1" is input to one end of the automatic reset type stop switch 21, and the other end is connected to the first input terminal of the OR circuit 24. The output side of the OR circuit 24 is connected to the set terminal S of the RS flip-flop 27. The pattern forming switch unit 5 includes switches S1 to Sn and Sn + 1.
The logical value "1" is input to one end of each of the switches S1 to Sn and Sn + 1, and the other ends thereof are connected to the input side of the OR circuit 26, respectively. Also, the signal line 2
Since 5 is led from the electronic musical instrument, a key-on signal KON generated when a certain key is pressed in the electronic musical instrument
(Logical value "1") is supplied. The signal line 25 is connected to the input side of the OR circuit 26. Also,
The other end of each of the switches S1 to Sn of the pattern forming switch unit 5 has a random access memory 6 as in the first embodiment.
Of the write input terminals A1 to An. The output terminal Q of the flip-flop 27 is connected to the oscillator 1 and the reset terminal R of the shift register 4 on the one hand, and to the input side of the differentiating circuit 28 on the other hand. In this case, the differentiating circuit 28 is configured to generate a pulse only in response to the change of the logical value "1" to "0" of the input signal. The output side of the differentiating circuit 28 is connected to the second input terminal of the OR circuit 30 via the delay circuit 29. The output side of the oscillator 1 is the first circuit of the OR circuit 30.
Of the OR circuit 30 and the output side of the OR circuit 30 is connected to the shift input terminal S of the shift register 4. Further, each output line of the shift register 4 is connected to the address input side of the random access memory 6 and the read address input side of the read only memory 7 on the one hand, and the NOR circuit 31 on the other hand as in the first embodiment. It is connected to the input terminal C of the shift register 4 via. Hereinafter, the rhythm pattern writing operation and the rhythm pattern reading operation will be separately described for convenience.

Rhythm pattern writing operation When the performer writes and sets the rhythm pattern First,
The writing / reading designation switch 8 is set on the fixed contact W side. As a result, the random access memory 6 becomes writable as in the first embodiment. Next, the start switch 2 is turned on and set. As a result, the positive voltage + V is differentiated by the differentiation circuit composed of the capacitor 22 and the resistor 23 to form one pulse. This pulse is input to the set terminal S of the flip-flop 27 via the OR circuit 24. Therefore, the output terminal Q of the flip-flop 27 outputs the theoretical value "1" (positive potential). The oscillator 1 and the shift register 4 receive the theoretical value "1" at their reset terminals R and are reset together. In this case, the differentiating circuit 28 also receives this theoretical value "1", but as described above, the differentiating circuit 28 is configured to function with respect to the change from the logical value "1" to the theoretical value "0". Therefore, the differentiating circuit 28 does not operate and does not generate a pulse. Therefore, the shift register 4 maintains the reset state, and the output of each stage appearing on the output side of the shift register 4 is a theoretical value "0". Therefore, the logical value “1” is input to the input terminal C of the shift register 4 via the NOR circuit 31.

Next, when the performer turns on and sets at least one of the switches S1 to Sn and Sn + 1, the logical value "1" is input to the OR circuit 26. Here, as an example, it is assumed that the switch S1 is turned on and set. By setting the switch S1 to be turned on, the flip-flop 2
A logical value "1" is input to the reset terminal R of the flip-flop 27, whereby the flip-flop 27 is inverted and the output terminal Q outputs a logical value "0". Therefore, the logical value "0" is input to the reset terminal R of the oscillator 1 and the shift register 4, and the reset state of both is released.

At the same time, since the change from the logical value “1” of the output terminal Q of the flip-flop 27 to the logical value “0” is input to the differentiating circuit 28, the differentiating circuit 28 generates one pulse. This pulse is delayed for a minute time by the delay circuit 29 and then input to the shift input terminal S of the shift register 4 via the OR circuit 30. As described above, since the logical value "1" is input to the input terminal S of the shift register 4 via the NOR circuit 31, when the pulse is input to the shift input terminal C, the first stage of the shift register 4 is input. The logical value "1" is stored in. In this case, the delay circuit 29
Since the delay time due to is set to be extremely short, the logical value "1" is stored in the first stage of the shift register 4 almost at the same time when the switch S1 is turned on. Therefore, the shift register 4 outputs the address signal AD1 (logical value "1") to its first output line almost at the same time when the switch S1 is turned on.
Is output. This address signal AD1 causes n addresses (1,
1), (1, 2), ... (1, n) are designated to enable writing. In this case, since the switch S1 is turned on as described above, the logical value "1" is stored in the address (1, 1).

In the above description, the case where only the switch S1 is set to be turned on has been described, but even when a plurality of switches are set to be turned on, the output from these switches set to turn-on is performed toward the random access memory 6 in exactly the same manner. The logical value “1” is stored in each address (1, j) j = 1, 2, ... N in the first column of the random access memory 6. Here, in the switch Sn + 1, the first beat of the rhythm pattern is n
This is used when all types of rhythm sounds are rests.

In parallel with the above operation, the reset state of the oscillator 1 is released. Therefore, the oscillator 1 starts generating the clock pulse CP, and the generated clock pulse CP is generated by the OR circuit 3.
It is sequentially input to the shift input terminal S of the shift register 4 via 0. The shift register 4 uses this clock pulse C
According to P, the logical value "1" stored in the first stage is sequentially shifted to the second and third stages. As a result, the shift register 4 causes the address signals ADi, i =
2, 3 ... m are output one after another. At this time, at the input terminal C of the shift register 4, the address signals ADi, i = 1,
Since 2 ... m (logical value "1") is inverted by the NOR circuit 31, the logical value "0" is input. Therefore, only one initially written logical value "1" exists in the shift register 4, and as described above, this is sequentially shifted to form the address signal ADi.

The subsequent rhythm pattern writing operation is performed in exactly the same manner as in the first embodiment. That is, the performer operates the rhythm pattern forming switch 5 while observing the blinking of the light emitting diode 9 and the pronunciation of the cymbal sound that occur in synchronization with each other, and operates the rhythm pattern forming switch 5. The rhythm pattern for can be stored.

Rhythm Pattern Read Operation When the performer reads and plays a rhythm pattern from the random access memory 6, first, the write / read designation switch 8 is set to the fixed contact R side. As a result, the random access memory 6 is provided as in the first embodiment.
Is ready for reading. Next, the performer turns on and sets the start switch 2. As a result, the oscillator 1 and the shift register 4 are reset, just as in the rhythm pattern writing operation of the second embodiment. At this time, the output of each stage of the shift register 4 is all logical value "0".

Next, when the performer presses a key of the electronic musical instrument to start playing, at this moment, the electronic musical instrument sends a key-on signal KON to the signal line 25.
(Logical value "1") is output. This key-on signal KO
Since N is input to the reset terminal R of the flip-flop 27 via the OR circuit 26, the flip-flop 27 is inverted and its output terminal Q outputs a logical value "0". Therefore, the logical value "0" is input to the reset terminal R of the oscillator 1 and the shift register 4, and the reset state of both is released. At this time, since the change from the logical value "1" of the output terminal Q of the flip-flop 27 to the logical value "0" is input to the differentiating circuit 28, the differentiating circuit 28 generates one pulse. This pulse is input to the shift input terminal S of the shift register 4 via the delay circuit 29 and the OR circuit 30 in exactly the same manner as in the rhythm pattern writing operation described above, and the NOR circuit is input to the input terminal C of the shift register 4. Since the logical value “1” is input via 31, the logical value “1” is stored in the first stage of the shift register 4. In this case, since the delay time of the delay circuit 29 is set to be extremely short as described above, the shift register 4 outputs the address signal AD1 (logical value "1") at the same time as the key depression of the electronic musical instrument. This address signal AD1 causes n addresses (1,
1), (1, 2) ..., (1, n) are designated, and the contents are output as rhythm pattern signals RP1 to RPn.

In parallel with the above operation, the reset state of the oscillator 1 is released. Therefore, the shift register 4 starts generating the clock pulse CP, and the generated clock pulse CP is sequentially input to the shift input terminal S of the shift register 4 via the OR circuit 30. The shift register 4 sequentially shifts the logical value "1" stored in the first stage to the second and third stages according to the clock pulse CP.
As a result, the address signals ADi (i = 2, 3, ... M) are output one after another just as in the case of the rhythm pattern writing operation.

Address signals ADi, i = sequentially generated in this manner
The n kinds of rhythm patterns stored by the rhythm pattern writing operation in each column of the random access memory 6 by 2, 3, ... M are rhythm pattern signals RP1 to RPn.
Are read one after another. This rhythm pattern signal R
The rhythm sound source circuit 12 is driven by P1 to RPn,
The various rhythm sounds are generated from the sound system 13 as in the case of the first embodiment.

When the performance is finished, the logical value "1" is changed to the flip-flop 27 by pressing the stop switch 21.
Is input to the set terminal S of. Therefore, the flip-flop 27 is inverted and its output terminal Q outputs the logical value "1". As a result, the oscillator 1 and the shift register 4 are both reset again.

As is apparent from the above description, according to the second embodiment of the present invention, the key-on signal KON (logical value "1") is output to the signal line 25 at the same time as the key depression of the electronic musical instrument, which causes the shift register 4 to operate. Since the address signal AD1 is output from, the automatic rhythm playing device is driven at the same time when the key is pressed. Therefore, it is possible to surely perform the synchronized start with the so-called electronic musical instrument.

In the first and second embodiments of the present invention described in detail above, the pattern forming switch section 5 is specially provided as a manual switch or a foot switch of the main body of the electronic musical instrument so that the player can easily operate it. Is also good. Furthermore,
Each key of the electronic musical instrument may be made to correspond appropriately to a cymbal sound, a bass drum sound, etc., and each key may be used as the pattern forming switch section 5 only during the rhythm pattern writing operation. Further, in the present invention, not only is the rhythm pattern for one song stored by increasing the storage capacity of the random access memory 6 (for example, by configuring the random access memory 6 with a plurality of chips of memory),
It is also possible to store a plurality of different rhythm patterns so that the performer can play different songs in succession. In this case, the random access memory 6 is divided into a plurality of groups (for example, when the random access memory 6 is composed of a plurality of chips, each chip may be one group), and each group is divided. A designation switch for designating may be provided in the random access memory 6.

[Effects of the Invention] As is clear from the above description, the automatic rhythm playing device according to the present invention has the excellent effect that it is easy to grasp the accurate tempo and timing because the tempo is sensed by the sound in the written state. Further, since no sensed sound is generated during the performance, the performance is not disturbed in the read state.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a block diagram showing a first embodiment of the present invention,
FIG. 1B is an explanatory view showing the contents of the random access memory, and FIG. 2 is a block diagram showing the second embodiment of the present invention. 1 ... Clock generator, 2 ... Start switch, 4 ... Address generator, 5 ... Pattern formation switch section, 6 ... Random access memory, 7 ... Read-only memory, 8 ... Write / read designation switch, 9 ...... Light emitting diode, 10 …… and circuit,
11, 24, 26, 30 ... OR circuit, 12 ... Rhythm sound source circuit, 13 ... Sound system, 21 ... Stop switch, 28 ... Differentiation circuit, 29 ... Delay circuit, K
ON: key-on signal, ADi: address signal, RP
1 to RPn ... Rhythm pattern signal.

Claims (1)

[Claims] 1. A clock generation means for generating a clock signal of a predetermined cycle according to a set tempo, a performance operation switch means, a write / read switch means for switching between a writing state and a reading state, and performance data is written and read. Memory means for storing performance data in the memory means in real time on the basis of a clock signal generated by the clock generating means in response to an operation of the performance operation switch means when a write state is designated by the write / read switch means. Writing means for writing performance data, and reading means for reading performance data from the memory means based on a clock signal generated by the clock generating means when the reading state is designated by the writing / reading switch means, and the reading means. Based on the read performance data Sound source means for generating a musical sound, tempo sensed sound generation means for generating a tempo sensed sound based on a clock signal generated by the clock generation means, and in conjunction with the state of the write / read switch means, in the write state, An automatic rhythm playing device comprising: a tempo-sensing sound generating means; and a control means for controlling the tempo-sensing sound generating means so as not to generate the tempo-sensing sound in a read state. .