JPS6339151B2 - - Google Patents
Info
- Publication number
- JPS6339151B2 JPS6339151B2 JP55042989A JP4298980A JPS6339151B2 JP S6339151 B2 JPS6339151 B2 JP S6339151B2 JP 55042989 A JP55042989 A JP 55042989A JP 4298980 A JP4298980 A JP 4298980A JP S6339151 B2 JPS6339151 B2 JP S6339151B2
- Authority
- JP
- Japan
- Prior art keywords
- clamp
- circuit
- voltage
- control circuit
- video signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/57—Control of contrast or brightness
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Picture Signal Circuits (AREA)
- Television Receiver Circuits (AREA)
Description
【発明の詳細な説明】
本発明はテレビジヨン受像機の輝度制御回路に
関するものであり、映像信号や不要信号の影響を
受けずに良好な輝度制御を行なうことができる輝
度制御装置を提供しようとするものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a brightness control circuit for a television receiver, and an object thereof is to provide a brightness control device that can perform good brightness control without being affected by video signals or unnecessary signals. It is something to do.
第１図に従来の輝度制御回路を示す。まず、こ
の従来の輝度制御回路について説明する。入力端
子１に入つた映像信号は増幅器である制御回路２
を通つてエミツタホロワ回路を構成するトランジ
スタ３のベースに加えられる。この制御回路は端
子４に加えられる制御電圧によつて映像信号の直
流レベルを制御するものである。トランジスタ３
のエミツタは一対のスイツチングトランジスタ
５，６を通つてクランプ用コンデンサ７に加えら
れる。このトランジスタ５，６には抵抗８，９を
介して端子１０よりクランプパルスが加えられ、
映像信号のペデスタル期間のみトランジスタ５，
６を導通させて、コンデンサ７に電荷を蓄積す
る。トランジスタ３のエミツタの抵抗１１，１２
の接続点は抵抗１３を介してコンデンサ７に接続
されている。この抵抗１３による径路は空チヤン
ネルにテレビのチヤンネルがセツトされたときク
ランプパルスがなくなつてトランジスタ５，６が
導通せず、コンデンサ７の電圧がなくなるのを防
止するためである。コンデンサ７の電圧は差動増
幅器を構成する一方のトランジスタ１４の入力端
子であるベースに加えられる。一方、可変抵抗１
６に得られる輝度制御用電圧は他方のトランジス
タ１５の入力端子であるベースに加えられる。こ
のベースはコンデンサ１７を介して接地されてい
る。トランジスタ１５のコレクタより出力電圧が
取出され制御電圧として端子４に加えられ帰還回
路が構成される。この回路はトランジスタ１４の
ベースの加えられるクランプ電圧がトランジスタ
１５のベースに加えられる輝度制御電圧に一致す
るまで帰還回路が動作し、可変抵抗１６で調整さ
れた電圧に映像信号の直流レベルが設定される。 FIG. 1 shows a conventional brightness control circuit. First, this conventional brightness control circuit will be explained. The video signal input to input terminal 1 is sent to control circuit 2 which is an amplifier.
It is applied to the base of the transistor 3 constituting the emitter follower circuit. This control circuit controls the DC level of the video signal using a control voltage applied to the terminal 4. transistor 3
The emitter of is applied to a clamping capacitor 7 through a pair of switching transistors 5 and 6. A clamp pulse is applied to these transistors 5 and 6 from a terminal 10 via resistors 8 and 9.
Transistor 5 only during the pedestal period of the video signal,
6 is made conductive, and charge is accumulated in the capacitor 7. Emitter resistors 11 and 12 of transistor 3
The connection point of is connected to the capacitor 7 via the resistor 13. The purpose of this path through the resistor 13 is to prevent the voltage across the capacitor 7 from disappearing as the clamp pulse disappears when a television channel is set to an empty channel, causing the transistors 5 and 6 to become non-conducting. The voltage of the capacitor 7 is applied to the base, which is the input terminal, of one transistor 14 constituting the differential amplifier. On the other hand, variable resistor 1
The brightness control voltage obtained at transistor 6 is applied to the base, which is the input terminal of the other transistor 15. This base is grounded via a capacitor 17. An output voltage is taken out from the collector of the transistor 15 and applied to the terminal 4 as a control voltage to form a feedback circuit. In this circuit, the feedback circuit operates until the clamp voltage applied to the base of the transistor 14 matches the brightness control voltage applied to the base of the transistor 15, and the DC level of the video signal is set to the voltage adjusted by the variable resistor 16. Ru.
この回路は映像信号を抵抗１３とコンデンサ７
で積分しているため、コンデンサ７に得られるク
ランプ電圧が完全に直流にならず、垂直期間で観
測するとクランプ電圧は映像信号の影響を受け
る。また、トランジスタ１５のベースに不要信号
が混入すると、この不要信号による交流成分が帰
還されて受像機の画面に輝度むらとなつて現われ
る。 This circuit connects a video signal to a resistor 13 and a capacitor 7.
Since the clamp voltage obtained at the capacitor 7 is not completely DC, the clamp voltage is influenced by the video signal when observed in the vertical period. Further, when an unnecessary signal is mixed into the base of the transistor 15, the alternating current component due to this unnecessary signal is fed back and appears as uneven brightness on the screen of the receiver.
本発明は制御信号に交流成分が混入しないよう
にして良好な輝度制御を行なえるようにしようと
するものであり、以下本発明の一実施例について
図面を参照して説明する。 The present invention aims to perform good brightness control by preventing alternating current components from being mixed into the control signal, and one embodiment of the present invention will be described below with reference to the drawings.
第２図は本発明の一実施例であり、第１図の回
路とほとんど同じであり、同一番号を付してお
く。この回路の特徴とするところはコンデンサ７
をトランジスタ１４のベースとトランジスタ１５
のベースとの間に接続したことにある。このよう
に構成すると、交流成分はトランジスタ１４，１
５による差動増幅器によつてキヤンセルされ制御
電圧として現われなくなる。この結果受像機画面
の輝度むらの発生がなくなり良好な輝度制御をす
ることができる。 FIG. 2 shows an embodiment of the present invention, which is almost the same as the circuit shown in FIG. 1, and is given the same number. The feature of this circuit is that the capacitor 7
the base of transistor 14 and transistor 15
It is connected between the base and the base. With this configuration, the AC component is transmitted through the transistors 14 and 1.
It is canceled by the differential amplifier based on 5 and no longer appears as a control voltage. As a result, brightness unevenness on the receiver screen is eliminated, and good brightness control can be achieved.
以上のように本発明によればクランプ用コンデ
ンサの接続位置を工夫するだけで輝度むらをなく
すことができ、良好な輝度制御をすることができ
るものである。 As described above, according to the present invention, brightness unevenness can be eliminated simply by changing the connection position of the clamp capacitor, and good brightness control can be achieved.
第１図は従来例における輝度制御回路の回路
図、第２図は本発明の一実施例における輝度制御
回路の回路図である。
１……入力端子、２……制御回路、５，６……
クランプ用スイツチングトランジスタ、１０……
クランプパルス入力端子、１１，１２，１３……
抵抗、７……クランプ用コンデンサ、１４，１５
……差動増幅器用トランジスタ、１６……可変抵
抗、４……制御電圧印加端子。
FIG. 1 is a circuit diagram of a brightness control circuit in a conventional example, and FIG. 2 is a circuit diagram of a brightness control circuit in an embodiment of the present invention. 1...Input terminal, 2...Control circuit, 5, 6...
Switching transistor for clamp, 10...
Clamp pulse input terminals, 11, 12, 13...
Resistor, 7... Clamp capacitor, 14, 15
... Differential amplifier transistor, 16 ... Variable resistor, 4 ... Control voltage application terminal.
Claims (1)
と、この制御回路の出力である映像信号のペデス
タル期間の電圧をクランプするクランプ回路と、
一方のベース入力端子に上記クランプ回路のクラ
ンプ電圧が印加され、他方のベース入力端子に輝
度制御用電圧が印加された差動増幅器と、この差
動増幅器の出力電圧を上記制御回路に帰還してペ
デスタルクランプをする帰還回路とを備え、上記
クランプ回路はクランプパルス期間のみ導通して
映像信号をクランプ用コンデンサに蓄積するスイ
ツチング回路を備え、上記クランプ用コンデンサ
の両端を上記差動増幅器の両ベース入力端子間に
接続したことを特徴とする輝度制御回路。1. A control circuit that controls the DC level of the video signal, a clamp circuit that clamps the voltage during the pedestal period of the video signal that is the output of this control circuit,
A differential amplifier has one base input terminal applied with the clamp voltage of the clamp circuit, and the other base input terminal applied with the brightness control voltage, and the output voltage of this differential amplifier is fed back to the control circuit. The feedback circuit performs pedestal clamping, and the clamp circuit includes a switching circuit that conducts only during the clamp pulse period and stores the video signal in the clamp capacitor, and connects both ends of the clamp capacitor to both base inputs of the differential amplifier. A brightness control circuit characterized by being connected between terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4298980A JPS56140776A (en) | 1980-04-01 | 1980-04-01 | Luminance control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4298980A JPS56140776A (en) | 1980-04-01 | 1980-04-01 | Luminance control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56140776A JPS56140776A (en) | 1981-11-04 |
| JPS6339151B2 true JPS6339151B2 (en) | 1988-08-03 |
Family
ID=12651433
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4298980A Granted JPS56140776A (en) | 1980-04-01 | 1980-04-01 | Luminance control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56140776A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3714643A1 (en) * | 1987-05-02 | 1988-11-17 | Philips Patentverwaltung | CIRCUIT ARRANGEMENT FOR AMPLIFYING A TELEVISION SIGNAL |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54177852U (en) * | 1978-06-06 | 1979-12-15 |
-
1980
- 1980-04-01 JP JP4298980A patent/JPS56140776A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56140776A (en) | 1981-11-04 |
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