JPS6340499B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an echo suppressor, and more particularly to an improvement in a digital full echo suppressor having full mode functionality.

With the recent development of digital transmission lines and satellite lines, a commonly controlled digital echo suppressor inserted into the digital multiplexing line has been adopted in place of the conventionally used analog echo suppressor. It has become possible to achieve economical improvements in technology and performance. The echo suppressors generally used are differential half-echo suppressors that are placed at both ends of a long-distance line and are operated by the communication signals of the other party. However, since half-echo suppressors must be installed at both terminals, the equipment cost is high. Therefore, in domestic long-distance lines, etc., a so-called full echo suppressor, in which two half echo suppressors are installed back to back on one side of the terminal, is sometimes used for convenience.

FIG. 1 is a block diagram showing an example of the configuration of a conventional full-echo suppressor, in which a half-echo suppressor, in which a transmitting speech suppression switch _S1 and a receiving loss switch _S2 are controlled by a control circuit _C1 , are placed back to back. Two sets are connected to. A telephone terminal is connected to the left side of the figure, and a counterpart terminal is connected to the right side of the figure via a long-distance transmission path. For convenience, the left side in the figure will be referred to as the near end, and the right side in the figure will be referred to as the far end. The transmitting loss when the transmitting suppression switch _S1 is open is about 50 db, and the receiving loss when the receiving loss switch _S2 is open is about 6 db, either a constant loss or a non-linear loss that depends on the receiving level. The transmit suppression switch _S1 is normally open and the receive loss switch _S2 is normally closed. When a call is transmitted from the near end, this is detected by the control circuit _C1 of the half echo suppressor connected to the near end, and the transmit suppressor switch _S1 is activated.
By closing the reception loss switch S2 and opening the reception loss switch _S2 , the reverberation is reduced by imparting reception loss to the echo signal from the far end. The presence or absence of speech transmission is determined by comparing the level of the input on the near end side of the speech suppression switch _S1 and the input on the far end side of the reception loss switch _S2 .
Then, after a predetermined remaining time (usually 40 to 75 ms) has elapsed since there was no more transmission, the suppression switch is turned on.
_S1 is opened and the receive loss switch _S2 is closed to enter the receive state. The other half-echo suppressor connected back-to-back treats the transmitted signal as a received signal,
The received signal is regarded as a transmitted signal and the same operation as described above is performed.

Therefore, when the near-end speaker speaks, the near-end half-echo suppressor is in the transmitting state (switch _S1 is closed and switch _S2 is open), and the far-end half-echo suppressor is in the receiving state. (Switch _S2 is closed and switch _S1 is opened). Then, after a predetermined residual time (40 to 75ms) after speaking, the near-end echo suppressor enters the receiving state and closes _S2 .
The half-echo suppressor at the far end enters the transmitting state and closes the switch _S1 . Therefore, if there is a delay on the far end side that exceeds the predetermined residual time, echoes that reach the receiving side after this residual time cannot be suppressed by switch _S1 of the far end half echo suppressor. There is a drawback. In order to prevent this drawback, it is possible to lengthen the suppression residual time. However, if the residual time is lengthened, the time during which the suppression loss is added becomes longer, so that the far-end speaker can be interrupted by the near-end speaker. It becomes difficult to interrupt smoothly. Further, even when the far-end speaker speaks first and the near-end speaker begins speaking next, the suppression switch is activated in the same manner, making it difficult for interruptions to occur. In other words, it cannot be adopted because it makes it difficult for both parties to communicate smoothly.

Therefore, the use of the full echo suppressor as described above is conventionally limited to lines with relatively short delay times. The above-mentioned drawbacks are the same regardless of whether the type is analog or digital. Another drawback is that the call quality deteriorates due to frequent switching operations.

The purpose of the present invention is to solve the above-mentioned conventional drawbacks and
It is an object of the present invention to provide an economical digital full echo suppressor that can be applied to long-distance lines without being subject to the above-mentioned application restrictions.

The echo suppressor of the present invention includes a control loss circuit inserted in each of the transmitting side transmission line and the receiving side transmission line, and a first comparator that compares the instantaneous level of the transmitted signal and the peak level of the received signal with a threshold value. a second comparator that compares the peak level of the transmitted signal and the instantaneous level of the received signal with a threshold; and a second comparator that compares the peak level of the transmitted signal and the instantaneous level of the received signal, and a A digital full echo suppressor equipped with a control circuit that controls loss by a predetermined operation and residual time, a peak delay detection means for detecting the peak level of a transmitted signal with a delay, and an output of the peak delay detection means. a first variable loss circuit that controls and applies a loss to the second comparator; and a second variable loss circuit that applies a loss to the peak level of the received signal and applies it to the first comparator; The loss of the second variable loss circuit is variably controlled by the control circuit.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention. In other words, the bipolar digital multiplexed signals input from the near-end PCM transmission line are sent to the bipolar/unipolar conversion circuit (B/U conversion circuit) 1.
is converted into a unipolar signal by
The signal is converted into a parallel signal by a parallel conversion (S/P conversion) circuit 5, subjected to transmission suppression loss or reception loss through a control loss circuit 7, or inputted without loss to a parallel/serial conversion circuit 9. The signal is converted into a serial signal by the U/B conversion circuit 11, and converted into a bipolar signal again by the U/B conversion circuit 11, and sent to the far end side. The above-mentioned reception loss is a constant loss of about 6 dB or a non-linear loss that depends on the reception level, and the transmission suppression loss is about 50 dB. The bipolar signal received from the far end side is similarly
The signal is sent to the near end side through the conversion circuit 2, S/P conversion circuit 6, control loss circuit 8, P/S conversion circuit 10, and U/B conversion circuit 12. Timing regeneration synchronization circuit (SYNC) from the output of B/U conversion circuit 1 above
3, and SYNC3 generates various clocks, address signals, etc. for reproducing a synchronization clock, detecting frame synchronization, and performing time-division multiplexing of an echo suppressor, which will be described later. SYNC4
performs a similar operation based on the output signal of the B/U conversion circuit 2. The output signal of the S/P conversion circuit 5 is inputted to a buffer memory (BUFF) 13, and inputted to one side of the first comparator 14 in synchronization with the same channel of the received signal from the far end side. The received signal from the far end is inputted from the S/P conversion circuit 6 to the reception peak hold circuit (PEAK) 18 and passed through the second variable loss circuit 19 to the first
is input to the other comparator 14. The peak hold circuit 18 is a circuit that holds the maximum value of the received signal within a predetermined time window. Second variable loss circuit 1
9 is a circuit that provides a loss of about 0 db or 6 db under the control of the control circuit 23. First comparator 14
compares the instantaneous value of the transmitted signal with the output value of the second variable loss circuit 19 and the threshold value T _y . The threshold value T _y is given from the transmitting sensitivity threshold generation circuit 20 . On the other hand, the instantaneous value of the received signal is calculated from the output of the S/P conversion circuit 6 to the second comparator 1.
7 to input. The output value of the buffer 13 is connected to the other input of the second comparator 17 through a variable delay circuit.
The output of the peak hold circuit (PEAK) 15 is delayed by VD and held at the maximum value within a predetermined time window of the output value of the delay circuit VD.
It is input through 6. The delay time of the variable delay circuit VD is set to approximately twice (2D) the one-way delay amount D of the transmission path. In this embodiment, the variable delay circuit VD and the peak hold circuit 15 constitute peak delay detection means. Second comparator 17
compares the instantaneous value of the receiving side signal with the output value of the first variable loss circuit 16 and the threshold value T _Z given from the threshold generation circuit 21 . The outputs of the first comparator 14 and the second comparator 17 are input to the control circuit 23. The control circuit 23 is the comparison circuit 1
After an appropriate operating time and residual time are given according to the operation mode determined by the relationship between the transmitting side level and the receiving side level, which will be described later, by the outputs of the control loss circuits 7 and 8. The loss is controlled and the loss of the first and second variable loss circuits 16 and 19 is varied.

Next, the operation of this embodiment will be explained. Third
The figure shows an operating area determined by the relationship between the speech level of the far-end speaker and the speech level of the near-end speaker, and the horizontal axis represents the reception level L _R from the far-end speaker.
The vertical axis indicates the transmission level L _S from the near-end speaker. The near-end level L _S is the threshold of the threshold generation circuit 20
Region _X where the far end side level L _R is smaller than the threshold T _Z of the threshold generation circuit 21
is in a no-call state. If there is a call only on the transmitting side, it is the Y region, and based on the outputs of the comparators 14 and 17, the control circuit 23 sets the suppression loss and reception loss of the control loss circuit 7 (on the transmitting side) to 0,
In the control loss circuit 8 (on the receiver side), a suppression loss is inserted and the receiver loss is controlled to zero. The variable loss circuits 19 and 16 are set to 0 db. Conversely, when there is only a received signal, it is in the Z region and gives a suppression loss to the control loss circuit 7, and the control loss circuit 8
Both the suppression loss and the reception loss are controlled to 0, and the losses of the variable loss circuits 19 and 16 are assumed to be 0 db. That is, in region Y where the transmitting side level is higher than the receiving side level by more than a threshold value, the transmitting side loss is 0 and the receiving side suppression loss is about 50 db, and vice versa (area Z).
In this case, a suppression loss is inserted on the transmitting side, and the loss on the receiving side becomes 0.

By the way, since the variable delay circuit VD is inserted between the buffer 13 and the peak hold circuit 15, the second comparator 17 is able to control the delay time (approx.
The level of the transmitted signal and the received signal delayed by 2D) will be compared. Therefore, when transmission is started, there is a delay of 2D, and the control loss circuit 8 is detected by the level comparison of the second comparator 17 just before the reflected signal arrives (before the time corresponding to the near-end delay). The suppression switch opens and prevents the echo from returning to the near-end talker. When the transmission is finished, the transmission signal is delayed by a delay time of about 2D and the transmission level at which the peak was detected is changed to the transmission level at which the transmission signal is transmitted to the far end terminal with a delay time D. Then, the echo component delayed by the near-end delay amount a at the normal terminal part becomes the echo signal delayed by the delay time D (delay time 2D +
a) is compared with the second comparator 17. Now, after the second comparator 17 determines that the call is in the receiving state, the control circuit 23 switches the suppression switch of the control loss circuit 8 during a residual time a' (40 to 74 ms) corresponding to the normal near-end delay time a. Since the reverberation signal continues to be open, it is possible to suppress the echo signal. Above residual time
Setting of a' may be done by considering the normal near-end delay amount a, and there is no need to set a particularly long residual time.
However, essentially a residual time of 2D+a' is given. When applied to a line with a long propagation time, it is sufficient to simply set the delay time of the variable delay circuit VD to about twice the transmission delay of the applied transmission line. Note that this setting time is approximately sufficient and high precision is not required. In addition, the variable delay circuit is an LSI
Rapid advances in technology have made it possible to use devices such as large-capacity memories whose costs have been significantly reduced, and even delay circuits of several hundred milliseconds can be realized at low cost with a small number of components.

When simultaneous calls are received from the transmitting and receiving sides, the system is in the W region, and both control loss circuits 7 and 8 are in a state where a receiving loss (approximately 6 dB) is inserted. The state of simultaneous communication is determined by the fact that the level difference between the transmitted and received signals is within the threshold level and by the second comparator 1.
4,17.

However, for example, when moving from the transmitting state (Y region) to the Z region of the receiving state, when the transmitting and receiving levels become approximately the same and the W region is reached, about 6 dB is applied to the second loss circuit 19. By applying a loss, the first comparator 14 determines that the receiving level is higher than the transmitting level after passing through the hysteresis region V _R shown in FIG. 3. In this case, the control circuit 23 determines that it is a two-way call in the above region _VR ,
The reception loss of both control loss circuits 7 and 8 is assumed to be 6 db, and the suppression loss is assumed to be 0. That is, the same control as in the area W is performed. Then, when the signal passes through the region _VR , the first comparator 14 determines that the call is in the receiving state, and the control circuit 23 controls the Z region by referring to the outputs of the first and second comparators. That is, the suppression loss and reception loss of the control loss circuit 8 are set to 0, and the suppression loss of the control loss circuit 7 is inserted. At the same time, the loss of the second variable loss circuit 19 is returned to zero. However, since the judgment of the second comparator 17 is delayed by the delay time 2D after the transmission signal disappears, the suppression loss of the control loss circuit 8 is not reduced to zero during this time.

Conversely, when moving from region Z in the receiving state to region Y in the transmitting state, since both the comparison circuits 14 and 17 judge that the receiving signal is large in the state of the region V _R , the control is naturally performed. The call remains in the receiving state.
Then, in the region W, the comparison circuits 14 and 17 determine that there is a two-way call, and the control circuit 23 inserts the reception losses of the control loss circuits 7 and 8, and sets the suppression loss of the control loss circuit 7 to zero. At the same time, the first variable loss circuit 1
The loss of 6 is approximately 6db. In the region V _S , the second comparator 17 determines that the received signal is still larger due to the approximately 6 dB loss of the first variable loss circuit 16. In this state, the control circuit 23 performs the same control as during bidirectional communication. And the area
When it passes through V _S and enters area Y, and the transmit signal level becomes high, it is determined that the transmit signal is in the transmit state, and the suppression loss and reception loss of the control loss circuit 7 are set to 0, and the reception loss of the control loss circuit 8 is set to 0. Insert suppression loss. At the same time, the first variable loss circuit 16 is set to zero. The above regions V _S and _VR are called hysteresis regions, and by providing them, it is possible to stabilize the operation of the echo suppressor and to smoothly change calls.

In the above embodiment, the variable delay circuit VD is inserted between the buffer 13 and the peak hold circuit 15, but it may also be placed after the peak hold circuit 15 in order to substantially delay the output of the peak hold circuit 15. Of course, similar effects can be obtained. Further, the buffer memory 13 may be configured to output the received signal after the parallel/serial conversion circuit 6 on the receiving side in accordance with the timing of the same channel on the transmitting side.

As described above, in the present invention, a peak delay detection means for detecting the peak level of each transmitted signal with a delay is provided, and the level of a signal obtained by delaying each transmitted signal by approximately the round-trip propagation time of a long-distance transmission line is provided. Since it is configured to compare the signal level and the received signal level to determine whether it is in a transmitting state or a receiving state, it is possible to suppress echo signals even when used in a satellite line etc. with a long propagation time. Further, since it is not necessary to set the suppression residual time particularly long for this purpose, there is an effect that interruption of a call can be smoothly performed. Furthermore, by providing a hysteresis region and configuring the operation mode at the time of call switching to be switched through a region similar to the two-way compatible state, operation can be stabilized and call switching can be performed smoothly. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional full echo suppressor, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is an operating area diagram for explaining the operation of the above embodiment. be. In the figure, 1, 2... bipolar/unipolar signal conversion circuit, 3, 4... timing reproduction synchronization circuit, 5, 6... serial/parallel conversion circuit, 7, 8... control loss circuit, 9, 10... ...Parallel/serial conversion circuit, 11, 12... Unipolar/bipolar conversion circuit, 13... Buffer memory, 14, 17... Comparator, 15, 18... Peak hold circuit, 16, 19... Variable loss circuit, 20 , 21... Threshold generation circuit, 23...
Control circuit, VD...variable delay circuit.

Claims (1)

[Claims] 1. Control loss circuits 7 and 8 inserted into the transmission line on the transmitting side and the transmission line on the receiving side, respectively, and a circuit for comparing the instantaneous level of the transmitted signal and the peak level of the received signal with a threshold value. 1 comparator 14; a second comparator 17 that compares the peak level of the transmitted signal and the instantaneous level of the received signal with a threshold; and based on the outputs of the first comparator and the second comparator. and a control circuit 23 for controlling the loss of the control loss circuit by a predetermined operation and residual time, the digital full echo suppressor comprising: peak delay detection means VD for detecting the peak level of the transmission signal with a delay; 15, and a first variable loss circuit 16 that controls the output of the peak delay detection means and supplies it to the second comparator.
and adding a loss to the peak level of the received signal,
a second variable loss circuit 19 for providing a signal to a comparator, wherein losses of the first and second variable loss circuits are variably controlled by the control circuit. .