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JPS6341228B2 - - Google Patents
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JPS6341228B2 - - Google Patents

Info

Publication number
JPS6341228B2
JPS6341228B2 JP55008543A JP854380A JPS6341228B2 JP S6341228 B2 JPS6341228 B2 JP S6341228B2 JP 55008543 A JP55008543 A JP 55008543A JP 854380 A JP854380 A JP 854380A JP S6341228 B2 JPS6341228 B2 JP S6341228B2
Authority
JP
Japan
Prior art keywords
mask
mesa
oxide film
etching
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55008543A
Other languages
Japanese (ja)
Other versions
JPS56105669A (en
Inventor
Toshihiko Aimi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP854380A priority Critical patent/JPS56105669A/en
Publication of JPS56105669A publication Critical patent/JPS56105669A/en
Publication of JPS6341228B2 publication Critical patent/JPS6341228B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00Cutting or separating of wafers, substrates or parts of devices

Landscapes

  • Bipolar Transistors (AREA)
  • Thyristors (AREA)
  • Weting (AREA)

Description

【発明の詳細な説明】 この発明はメサ型半導体ペレツトの製造方法に
係り、特にメサ型半導体チツプのメサエツチ工程
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing mesa semiconductor pellets, and more particularly to a mesa etching process for mesa semiconductor chips.

シリコン半導体基板の片側(又は両側)よりメ
サ溝を設けたいわゆるメサ型半導体装置の製造工
程においてメサ溝を形成する場合、従来はあらか
じめシリコン基板表面に高温においてシリコン酸
化皮膜を設け公知の光学的手法を用いて選択的に
メサ溝となる部分の酸化膜をとり除いて後弗酸系
のエツチング液にてシリコン酸化膜をマスクとし
てメサエツチングを行つてメサ溝を形成してい
た。
When forming a mesa groove in the manufacturing process of a so-called mesa-type semiconductor device in which a mesa groove is provided from one side (or both sides) of a silicon semiconductor substrate, conventionally, a silicon oxide film is formed on the surface of the silicon substrate at high temperature and a known optical method is used. The oxide film was selectively removed from the portion that would become the mesa groove using a etchant, and then mesa etching was performed using a hydrofluoric acid etching solution using the silicon oxide film as a mask to form the mesa groove.

この場合、シリコン酸化膜には光学的手法で選
択的に酸化膜を除去する際にフオトレジスト膜に
あるピンホール、シリコン酸化膜の欠陥等により
マスクとなるべき酸化膜に微少なピンホールが生
じ、これがメサエツチングの際に穴となりペレツ
トの電気的特性をそこない、外観不良となる等の
欠点を有していた。又酸化膜をマスクとせず金属
膜を蒸着等で設けこれをフオトレジストで同様に
選択的に除去することによりマスクとする方法が
あるがこれもフオトレジストのピンホールによる
金属膜の欠陥は同様に起り同じ欠点を有してい
る。又ワツクス等を選択的に塗布してこれをマス
クとして用いる方法もあるがペレツト周辺がワツ
クスが流れるために直線とならず凸凹となり、耐
圧特性が劣化してしまい好ましくない。
In this case, when the silicon oxide film is selectively removed using an optical method, minute pinholes are created in the oxide film that is supposed to be a mask due to pinholes in the photoresist film or defects in the silicon oxide film. This has disadvantages such as forming holes during mesa etching, impairing the electrical properties of the pellet and causing poor appearance. Alternatively, instead of using an oxide film as a mask, there is a method of using a metal film as a mask by vapor deposition or the like and selectively removing it using a photoresist, but this also has the same effect on defects in the metal film due to pinholes in the photoresist. Both have the same drawbacks. There is also a method of selectively applying wax or the like and using this as a mask, but since the wax flows around the pellet, it becomes uneven instead of straight, which deteriorates the withstand voltage characteristics, which is not preferable.

本発明はかかる欠点を除去し、ペレツト表面に
穴の発生を押えることにより耐圧、外観の歩留り
わ向上させるための製造方法を提供することにあ
る。
The object of the present invention is to provide a manufacturing method that eliminates such drawbacks and improves the pressure resistance and appearance yield by suppressing the formation of holes on the pellet surface.

本発明によればかかる欠点をなくすため、ペレ
ツト周辺部を直線性を得るためにフオトレジスト
等の光学的手法を用いて第1のマスクを構造し、
その上にさらにスクリーン印刷法等を用いてワツ
クスを第1のマスクよりメサエツチ後にシリコン
基板が横方向にサイドエツチされる量とほぼ等し
く内側に入る様に第2のマスクを形成するしかる
後に溝部のエツチングを行うとペレツト周辺部は
光学的手法により形成された第1のマスクにより
直線が維持され又第1のマスク上にあるピンホー
ル等の欠陥は第2のマスクがカバーするために穴
の発生がなく歩留りよくメサ型半導体ペレツトを
製造できる。又この際第1のマスクより第2のマ
スクをメサエツチ工程で起るシリコン基板の横方
向のエツチング(サイドエツチ)の量とほぼ同じ
程度内側に入れることがマスク精度からして最大
の効果を上げることが判つた。すなわち、アピエ
ゾンワツクス等のワツクスをスクリーン印刷法を
用いて目合せ印刷を行うときの目合せ精度とシリ
コン基板のサイドエツチ量はほぼ同じ大きさであ
るから、第2のマスクが第1のマスクより内側に
入る量がサイドエツチ量より少ないときは、スク
リーン印刷時に印刷用のマスクがずれて、第2の
マスクが第1のマスクからはみだして印刷されて
しまう。このため、メサエツチ後のペレツト周辺
がワツクスが流れるため直線とならず凹凸とな
り、耐圧特性が劣化してしまう。
According to the present invention, in order to eliminate such drawbacks, the first mask is structured using an optical method such as a photoresist in order to obtain linearity in the peripheral part of the pellet,
On top of that, a second mask is formed using a screen printing method or the like so that the wax is etched from the first mask, and then the silicon substrate is etched inward by approximately the same amount as the side etching in the lateral direction.Then, the grooves are etched. When this is done, the peripheral part of the pellet is maintained in a straight line by the first mask formed by an optical method, and defects such as pinholes on the first mask are covered by the second mask, so that holes do not occur. Mesa-shaped semiconductor pellets can be manufactured with high yield without any problems. Also, in this case, placing the second mask inward from the first mask by approximately the same amount as the amount of lateral etching (side etching) of the silicon substrate that occurs in the mesa etching process will maximize the effect in terms of mask accuracy. I found out. In other words, the alignment accuracy when alignment printing is performed using a screen printing method for wax such as Apiezon wax and the amount of side etching of the silicon substrate are approximately the same, so the second mask is the same as the first mask. If the amount that goes further inside is smaller than the side etching amount, the printing mask will shift during screen printing, and the second mask will be printed extending beyond the first mask. For this reason, the wax flows around the pellet after mesa-etching, so that it is not straight but uneven, and the withstand voltage characteristics deteriorate.

一方、第2のマスクが第1のマスクより内側に
入る量がサイドエツチ量より多いときは、第2の
マスクが第1のマスクからはみ出して印刷される
ことはないが、第1のマスクが第2のマスクに覆
われていない領域が増加し、第1のマスクに生じ
たピンホール等の影響によりシリコン基板に穴が
あき特性不良を生じさせてしまう。
On the other hand, if the amount of the second mask that goes inside the first mask is greater than the side etching amount, the second mask will not be printed protruding from the first mask, but the first mask will be The area not covered by the second mask increases, and holes are formed in the silicon substrate due to the effects of pinholes and the like generated in the first mask, resulting in poor characteristics.

これに対して、第2のマスクが第1のマスクよ
り内側に入る量がサイドエツチ量とほぼ等しいと
きは、第2のマスクが第1のマスクからはみ出し
て印刷されることもなく、第1のマスクに生じた
ピンホールをほとんど覆うことにもなるため、メ
サエツチ後の良品率が最大となる。
On the other hand, if the amount of the second mask that goes inside the first mask is approximately equal to the side etching amount, the second mask will not be printed protruding from the first mask, and the second mask will not be printed outside the first mask. Since it also covers most of the pinholes that occur in the mask, the rate of good products after Mesa etching is maximized.

次に本発明の一実施例について図面を参照して
説明する。ガリウム及びリンを用いてP−N−P
−N接合3、1、2、4を形成したシリコン基板
1第1図を高温で酸化し、シリコン酸化膜5を設
け、フオトレジストを用いて開口部6を設ける。
この際にフオトレジストのピンホールによつて酸
化膜が部分的にとられた酸化膜穴部7が生ずるこ
とがある。これを従来の様にこのままエツチング
を行うと第2図で示すように穴部7はエツチング
後にエグレを生じ、シリコン穴8を生ずることと
なる。従つて本発明では、例えばアピエゾンワツ
クスを用いてスクリーン印刷機にて目合せ印刷を
行い、マスク9を表裏より設けて後エツチングを
行う。この様にすると酸化膜上の穴部7等はエツ
チングされることはない。さらに電気泳動法を用
いてガラス10をつけると接合が完全にパツシベ
ーシヨンが行われ歩留りも非常に良好であつた。
Next, an embodiment of the present invention will be described with reference to the drawings. P-N-P using gallium and phosphorus
The silicon substrate 1 (FIG. 1) on which the -N junctions 3, 1, 2, and 4 have been formed is oxidized at high temperature to form a silicon oxide film 5, and an opening 6 is formed using photoresist.
At this time, oxide film holes 7 may be formed where the oxide film is partially removed due to pinholes in the photoresist. If this is etched as is in the conventional manner, the hole 7 will be eroded after etching, resulting in the formation of a silicon hole 8, as shown in FIG. Accordingly, in the present invention, alignment printing is performed using a screen printing machine using, for example, Apiezon wax, the mask 9 is provided from the front and back, and post-etching is performed. In this way, the hole 7 etc. on the oxide film will not be etched. Furthermore, when the glass 10 was attached using electrophoresis, the bonding was completely bonded and the yield was very good.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の光学的手法にてシリコン酸化膜
上に選択的なマスクを設けたシリコン基板、第2
図はそれをエツチングした後ガラスを塗布したシ
リコン基板、第3図は本発明の実施例によるシリ
コン酸化膜及びアピエゾンワツクスの2重のマス
クを設けたシリコン基板、第4図はそれをエツチ
ングした後ガラスを塗布したシリコン基板をそれ
ぞれ示す断面図である。 なお図において、1……N型シリコン基板、2
……P型ベース拡散層、3……アノードP型拡散
層、4……カソードN型拡散層、5……シリコン
酸化膜マスク、6……酸化膜開口部、7……酸化
膜上ピンホール、8……シリコンピンホール、9
……アピエゾンワツクスマスク、10……ガラ
ス。
Figure 1 shows a silicon substrate with a selective mask provided on the silicon oxide film using a conventional optical method;
The figure shows a silicon substrate coated with glass after etching, Figure 3 shows a silicon substrate with a double mask of silicon oxide film and Apiezon wax according to an embodiment of the present invention, and Figure 4 shows a silicon substrate after etching it. FIG. 3 is a cross-sectional view showing a silicon substrate coated with glass after the above-mentioned steps. In the figure, 1...N-type silicon substrate, 2
... P-type base diffusion layer, 3 ... Anode P-type diffusion layer, 4 ... Cathode N-type diffusion layer, 5 ... Silicon oxide film mask, 6 ... Oxide film opening, 7 ... Pinhole on oxide film , 8... Silicon pinhole, 9
...Apiezon Wax Mask, 10...Glass.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基体に溝を設けてメサ型半導体ペレツ
トを製造する際に、光学的手法を用いて形成した
第1のマスクの上に、さらにスクリーン印刷法を
用いて、メサエツチ後に前記第1のマスクの周縁
から横方向に前記半導体基体がサイドエツチされ
る量とほぼ等しい長さだけ前記第1のマスクから
内側に入る様にワツクスからなる第2のマスクを
形成し、その後前記半導体基体をエツチングして
溝を設けることを特徴とするメサ型半導体ペレツ
トの製造方法。
1. When producing a mesa-shaped semiconductor pellet by forming a groove in a semiconductor substrate, a screen printing method is further used to form a mesa-shaped semiconductor pellet on top of the first mask formed using an optical method, and after mesa etching, the first mask is A second mask made of wax is formed inward from the first mask by a length approximately equal to the amount by which the semiconductor substrate is side-etched in the lateral direction from the periphery, and then the semiconductor substrate is etched to form a groove. 1. A method for producing a mesa-shaped semiconductor pellet, the method comprising: providing a mesa-shaped semiconductor pellet;
JP854380A 1980-01-28 1980-01-28 Manufacture of mesa type semiconductor pellet Granted JPS56105669A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP854380A JPS56105669A (en) 1980-01-28 1980-01-28 Manufacture of mesa type semiconductor pellet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP854380A JPS56105669A (en) 1980-01-28 1980-01-28 Manufacture of mesa type semiconductor pellet

Publications (2)

Publication Number Publication Date
JPS56105669A JPS56105669A (en) 1981-08-22
JPS6341228B2 true JPS6341228B2 (en) 1988-08-16

Family

ID=11696051

Family Applications (1)

Application Number Title Priority Date Filing Date
JP854380A Granted JPS56105669A (en) 1980-01-28 1980-01-28 Manufacture of mesa type semiconductor pellet

Country Status (1)

Country Link
JP (1) JPS56105669A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04295217A (en) * 1990-12-17 1992-10-20 Heidelberger Druckmas Ag Cable drawing apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04295217A (en) * 1990-12-17 1992-10-20 Heidelberger Druckmas Ag Cable drawing apparatus

Also Published As

Publication number Publication date
JPS56105669A (en) 1981-08-22

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