JPS6341229B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a MOS semiconductor integrated circuit in which an insulated gate type semiconductor memory cell array having a floating gate electrode and its peripheral circuitry are formed on the same substrate.

Floating gate semiconductor memory (SAMOS) is an electrically rewritable nonvolatile semiconductor memory.

This type of semiconductor memory is easy to integrate, write, erase, and read information, and has recently been widely used in various applications such as microcomputers. Semiconductor memories used for these applications are usually integrated with their peripheral circuits, such as decoder circuits and buffer circuits, on the same semiconductor substrate to reduce costs.

By the way, when manufacturing this type of semiconductor chip, it is desirable to have a high yield, but defective chips are produced due to various reasons.

Among these problems, one problem that has been particularly difficult to solve is the phenomenon in which information spontaneously disappears after writing.

A particular object of the present invention is to provide a MOS semiconductor integrated circuit that prevents such information loss phenomenon.

As a result of various tests and research conducted by the inventors to find out the causes of information loss mentioned above, MOS
Strain generated around the semiconductor memory cell array during the assembly (manufacturing) process of semiconductor integrated circuits, such as mounting, bonding, scribing, and sieving, can cause damage to the field oxide film and the semiconductor substrate, or the field oxide film and the passivation film (PSG film). It was presumed that the strain spread through the interface with the memory cell, causing strain in the gate insulating film of the memory element in the memory array, for example, and that this was the cause of the release of the accumulated carriers.

Therefore, in order to prevent the spread of such strain into the semiconductor memory cell array, a region of the opposite conductivity type to the substrate was formed on the surface of the semiconductor substrate under the field insulating film around the memory cell array, which prevented information loss. It was confirmed that there were almost no The reason for this is that there is strain in the region of the opposite conductivity type.
This is thought to be because stress tends to concentrate in this region or the interface between it and the substrate, and this serves to prevent the spread of strain.

Therefore, the present invention combines an electrically rewritable insulated gate type semiconductor memory cell eye having a floating gate electrode and a peripheral circuit including the function of selecting, writing and reading a desired cell from this semiconductor memory cell eye. In a MOS semiconductor integrated circuit formed on a substrate, a region having a conductivity type opposite to that of the substrate is formed in the substrate below a field insulating film formation region formed on the substrate around the semiconductor memory cell eye. The present invention provides a MOS semiconductor integrated circuit characterized by:

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view schematically showing an embodiment of the present invention.

In the center of the P-type semiconductor substrate 10, cell arrays 3a and 3b of insulated gate semiconductor memory (SAMOS) having floating gate electrodes for writing using impact ionization are formed. A row decoder circuit and a row selection circuit 6 are provided between memory cell arrays 3a and 3b. Column selection circuits 7a and 7b are provided adjacent to one end of each memory cell array 3a and 3b, respectively, and a column decoder circuit is provided between these column selection circuits 7a and 3b. Here, the memory cell arrays 3a and 3b each consist of 4 blocks,
The specific structure of each block is as shown in FIG. That is, in each block, insulated gate type semiconductor memory elements 2a to 2i having floating gate electrodes constituting one cell are arranged in rows and columns. The gates of the elements forming each row are commonly connected to control lines 5a to 5c from the row selection circuit 6, and the drains of the elements forming each column are commonly connected to the MOS transistors forming the column selection circuits 7a and 7b. Connected to sources 8a to 8c. M.O.S.
The drains of transistors 8a to 8c are commonly connected to input and output signals to and from data input/output buffer circuit 9 of FIG. 1. MOS transistor 8a
Each gate of ~8c is connected to the control line 4 from the column decoder 8.
Connected to a to 4c. The gates of the memory elements 2a to 2i constituting each row are commonly connected to the sources of the load MOS transistors 3a to 3c, and the drains of the MOS transistors 3a to 3c are commonly connected to the readout from the control circuit 4 in FIG. It is connected to the write control line 6. In this way, high voltages and low voltages corresponding to writing and reading are applied to the gates of the memory elements 2a to 2i, respectively.

FIG. 3 shows a circuit of a part of the array of memory elements 2a to 2i arranged in rows and columns, and FIG. 4 shows the circuit of FIG. 3 actually integrated into a planar pattern. It is.

In these figures, S is a source, D is a drain, G is a control gate electrode, F is a floating gate electrode, C is a column control line, and L is a row control line.

Next, the explanation will be given by returning to FIG.

On the semiconductor substrate 10, around the memory cell arrays 3a and 3b, there are a row address buffer circuit 2, a column address buffer circuit 5, a data input/output buffer circuit 9, a control signal buffer circuit, and a read/write control circuit 4. is formed. Row and column address buffer circuits 2 and 5 are on the board 1
The signals sent from address signal input bonding pads 1a to 1h and 1U to 1W provided around the address signal input circuit 0 are converted into signals for driving the row and column decoder circuits 6 and 8. The data input/output buffer circuit 9 uses signals sent from data input/output bonding pads 1i to 1k, 1m to 1q provided on the periphery of the substrate 10 to buffer the memory cell array 3.
It selects eight blocks among a and 3b according to the data and performs a write operation, and reads out the data stored in the eight blocks and sends it to the bonding pads 1i to 1k and 1m to 1q. be. The control signal buffer circuit 4 processes the signals sent from the control signal input bonding pads 1r, 1s and the program voltage application bonding pad 1t provided around the substrate 10, and processes the signals sent from the memory cell array 3a,
It controls writing, reading, etc. to 3b.

In addition, 1x is a bonding pad for applying a power supply voltage, and 1l is a bonding pad for grounding. On the substrate 10, a field insulating film, for example, an oxide film, is formed between each element constituting the above-mentioned MOS circuit, and wiring of aluminum or the like is formed on this insulating film. In the field insulating film, the insulating film around the circuit blocks including the memory cell arrays 3a and 3b, the row decoder circuit and the row selection circuit 6, the column decoder circuit 8 and the column selection circuits 7a and 7b has a groove extending to the surface of the substrate 10. 30 are provided. This situation will be explained with reference to FIG. 5, which shows the AA cross section of FIG. 1.

As described above, the memory cell array 3a or the column address buffer circuit 5 is formed on the P-type semiconductor substrate 10.
A field insulating film 31 is formed between the insulated gate type semiconductor memory element 1 having a floating gate electrode constituting a and the MOS transistor 50 constituting the column address buffer circuit 5 to provide isolation between the elements. Here, S1 and D1 are the source and drain of element 1, respectively, G1 and F1 are the control gate electrode and floating gate electrode of element 1, and 3
2 and 33 are gate oxide films. Further, S2 and D2 are the source and drain of the transistor 50, G1 and 3
4 is an electrode and a gate oxide film of the transistor 50. The method of providing the groove 30 in the field insulating film 31 differs depending on the method of forming the insulating film 31, but for example, when the insulating film 31 is formed by vapor phase growth over the entire surface of the substrate 10, the groove 30 is formed in the area where the device is to be formed. At the same time, groove 3 is removed by selective etching.
0 may be formed by selective etching. When the insulating (oxide) film 31 is formed by thermal oxidation of the surface of the substrate 10 using the so-called coplanar method, silicon nitride or the like is applied in advance to the area where the elements are to be formed and the area where the grooves 30 are to be formed. An oxidation-resistant mask may be formed in advance, and the mask may be removed after thermal oxidation is completed. Further, in FIG. 5, as a feature of the present invention, an N-type high impurity concentration region 35 of opposite conductivity type to the substrate 10 is formed on the surface of the substrate 10 under the groove 30, and the strained memory cell arrays 3a, 3b are It reliably prevents inward transmission. This is the N type region 35
When the N-type region 35 is formed by ion plantation or diffusion, strain occurs in the N-type region 35, and subsequent strain generation also tends to be concentrated in the N-type region 35 and its surroundings, so that the strain does not spread. This is thought to be because it is effectively prevented. The N-type region 35 is preferably held at the same potential as the substrate 10 in order to prevent juncture leak from affecting other elements. This N-type region 35 is the semiconductor memory element 1
and the source regions S1 and S of the MOS transistor 50
If the drain regions D1 and D2 are formed simultaneously by ion plantation or diffusion, the process can be simplified.

By forming the N-type region 35 as described above, it is possible to effectively prevent distortion generated during the assembly process from spreading into the memory cell arrays 3a and 3b, and when using a memory, natural loss of information after writing can be prevented. This phenomenon can be definitely prevented.

Note that in the embodiment described above, the memory cell array 3
a, 3b, a row decoder circuit and a row selection circuit 6;
An N-type region 3 surrounds the block including the row decoder circuit 8 and column selection circuits 7a and 7b in a closed loop.
However, in consideration of the fact that the strain generated during the assembly process is particularly along the bonding pads 1a to 1x or along the scribe line (outer edge) of the substrate 10, the substrate surface under the field insulating film surrounding these bonding pads is Alternatively, an N-type region may be formed in the memory cell array 3.
Even if an N-type region is provided on the substrate surface of any field insulating film located between a and 3b, the bonding pad, and the scribe line, the spread of strain can be sufficiently prevented.

In addition, in FIG. 4, strain is applied to the gate insulating film of the memory element through the field insulating film that exists in a direction (in the direction of arrow A) that is almost perpendicular to the opposing direction of the source S and drain D of the floating gate type semiconductor memory element. In consideration of spreading and causing information loss, arrow A is drawn around the memory cell arrays 3a and 3b.
Even if an N-type region is formed under the field insulating film existing in the direction, the data loss phenomenon can be effectively prevented.

According to the present invention described in detail above, the information loss phenomenon can be effectively prevented and an excellent yield can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a plan view schematically showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific configuration of a memory cell array, and FIG. 3 is a circuit diagram showing a part of FIG. FIG. 4 is a plan view showing a pattern obtained by integrating the circuit shown in FIG. 3, and FIG. 5 is a cross-sectional view taken along the line AA in FIG. 1. 10...P-type semiconductor substrate, 3a, 3b...memory cell array, 1a to 1x...bonding pad, 6...row decoder circuit and row selection circuit, 8...
... Column decoder circuit, 7a, 8a... Column selection circuit,
2, 5... Address buffer circuit, 9... Data input/output buffer circuit, 31... Field insulating film, 30... Groove, 35... N type region, 1... Memory element, 50... MOS transistor.

Claims (1)

[Claims] 1. An electrically rewritable insulated gate type semiconductor memory cell array having a floating gate electrode and a peripheral circuit including a function of selecting, writing and reading a desired cell from this semiconductor memory cell array are the same. In a MOS semiconductor integrated circuit formed on a substrate, a region having a conductivity type opposite to that of the substrate is formed in the substrate under a field insulating film formation region formed on the substrate around the semiconductor memory cell array. Characteristics of MOS semiconductor integrated circuits. 2. The MOS semiconductor integrated circuit according to claim 1, wherein the region of opposite conductivity type is formed to surround the semiconductor memory cell array. 3. An electrically rewritable insulated gate type semiconductor memory cell array having a floating gate electrode and a peripheral circuit including a function of selecting, writing and reading a desired cell from this semiconductor memory cell array are placed on the same P-type substrate. In the formed MOS semiconductor integrated circuit, an n-type region is formed in the P-type substrate below a field insulating film formation region formed on the P-type substrate around the semiconductor memory cell array. Semiconductor integrated circuit. 4. The MOS semiconductor integrated circuit according to claim 3, wherein the n-type region is formed to surround the semiconductor memory cell array.