JPS6343893B2

JPS6343893B2 -

Info

Publication number: JPS6343893B2
Application number: JP57119310A
Authority: JP
Inventors: Nobuaki Yamamori
Original assignee: Nippon Electric Co Ltd
Current assignee: NEC Corp
Priority date: 1982-07-09
Filing date: 1982-07-09
Publication date: 1988-09-01
Also published as: JPS5910232A

Description

【発明の詳細な説明】本発明は、半導体装置の製造方法に係り、特に
金属配線形成に有力な効果を有する、スクライブ
線の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a scribe line structure that has a powerful effect on metal wiring formation.

最近、集積回路の微細化が進み、従来にも増し
て、高信頼性、高歩留りの金属配線を形成するこ
とが求められてきている。 Recently, as integrated circuits have become smaller and smaller, there has been a greater demand than ever before to form metal interconnections with high reliability and high yield.

第１図は一般的なスクライブ線の構造を持つ、
半導体装置及びその形成方法である。半導体基板
１上にｎ型エピタキシヤル層２を形成し、その後
フオトリソグラフイ技術及び拡散技術をもちい、
ｎ型エピタキシヤル層２内に、スクライブ線領域
のn⁺型層６、ｐ型最低電位層７、n⁺型コレクタ
層８、ｐ型ベース領域３、n⁺型エミツタ領域９、
p⁺型高濃度ベース領域１０を形成する。その後、
絶縁膜４を形成し、所要の部分にのみ、フオトリ
ソグラフイ技術を用いて、電極引出し部（コンタ
クト穴）を形成する。しかる後、真空蒸着法等に
より、金属層５を形成する（第１図ａ）。その後、
フオトリソグラフイ技術により、所要のレジスト
パターン１１を形成する（第１図ｂ）。しかる後、
リン酸等の溶液を用いた湿式エツチ法又は四塩化
炭素等のガスプラズマを用いた乾式エツチ法によ
り、不要な部分の金属層を除去する（第１図ｃ）。
その後、フオトレジストを除去し、金属配線の形
成が完了する（第１図ｄ）。ここで従来のスクラ
イブ線の構造では、スクライブ線上の絶縁膜はと
り除かれている為、金属層のエツチング中にスク
ライブ線と、最低電位層の間に起電力が生じ、ル
ープ電流が発生し、これにより、最低電位層上の
金属配線の腐触し、またはなはだしい場合は断線
を生じていた。 Figure 1 shows the structure of a general scribe line.
A semiconductor device and a method for forming the same. An n-type epitaxial layer 2 is formed on a semiconductor substrate 1, and then using photolithography technology and diffusion technology,
In the n-type epitaxial layer 2, an n ⁺ -type layer 6 in the scribe line region, a p-type lowest potential layer 7, an n ⁺ -type collector layer 8, a p-type base region 3, an n ⁺ -type emitter region 9,
A p ⁺ type high concentration base region 10 is formed. after that,
An insulating film 4 is formed, and electrode extension portions (contact holes) are formed only in required portions using photolithography. Thereafter, a metal layer 5 is formed by vacuum evaporation or the like (FIG. 1a). after that,
A required resist pattern 11 is formed by photolithography (FIG. 1b). After that,
Unnecessary portions of the metal layer are removed by a wet etching method using a solution such as phosphoric acid or a dry etching method using gas plasma such as carbon tetrachloride (FIG. 1c).
Thereafter, the photoresist is removed and the formation of the metal wiring is completed (FIG. 1d). In the conventional scribe line structure, since the insulating film on the scribe line is removed, an electromotive force is generated between the scribe line and the lowest potential layer during etching of the metal layer, and a loop current is generated. This resulted in corrosion of the metal wiring on the lowest potential layer, or in extreme cases, disconnection.

本発明は、上記の問題を解決したスクライブ線
の構造を提供することを目的とする。 An object of the present invention is to provide a scribe line structure that solves the above problems.

すなわち本発明は、一導電型半導体基板上に逆
導電型エピタキシヤル層を形成し、前記エピタキ
シヤル層内に前記エピタキシヤル層を貫通して基
板に達する一導電型の最低電位層を形成し、前記
最低電位層で電気的に分離されたエピタキシヤル
層の一方にスクライブ線領域を形成し、他方にト
ランジスタの活性化領域を形成し、スクライブ線
領域内に逆導電型の高濃度層を形成し、トランジ
スタの活性化領域内には逆導電型高濃度コレクタ
層及び一導電型ベース領域を形成し、前記一導電
型ベース領域内にさらに一導電型高濃度ベース領
域と逆導電型高濃度エミツタ領域とを形成した
後、全面に絶縁膜を形成する工程と、スクライブ
線領域上及びその内部に形成した高濃度層上の絶
縁膜を残し、最低電位層上ならびにトランジスタ
の活性領域内の高濃度コレクタ層、高濃度エミツ
タ領域及び高濃度ベース領域上の各電極引出し部
のみの絶縁膜を除去してコンタクト穴を形成する
工程と、コンタクト穴をふくむ前記絶縁膜表面に
金属層を被着する工程と、金属層表面に所望のフ
オトレジストパターンを形成する工程と、しかる後前記フオトレジストパターンをマスク
として四塩化炭素等のガスプラズマを用いたドラ
イエツチング法により前記金属層を加工して金属
配線を形成する工程とを含み、これにより、金属配線形成工程においてスクラ
イブ線と最低電位層との間を局部電池による電流
が流れることにより前記最低電位層上の金属配線
が腐蝕されることを防ぐことを特徴とする半導体
装置の製造方法に関する。 That is, the present invention forms an epitaxial layer of an opposite conductivity type on a semiconductor substrate of one conductivity type, and forms within the epitaxial layer a lowest potential layer of one conductivity type that penetrates the epitaxial layer and reaches the substrate, A scribe line region is formed in one of the epitaxial layers electrically isolated by the lowest potential layer, a transistor activation region is formed in the other, and a high concentration layer of an opposite conductivity type is formed in the scribe line region. , a highly doped collector layer of opposite conductivity type and a base region of one conductivity type are formed in the active region of the transistor, and a highly doped base region of one conductivity type and a highly doped emitter region of opposite conductivity type are further formed in the base region of one conductivity type. and then forming an insulating film on the entire surface, leaving the insulating film on the high concentration layer formed on and inside the scribe line region, and forming the high concentration collector on the lowest potential layer and in the active region of the transistor. a step of forming a contact hole by removing the insulating film only from each electrode lead-out portion on the layer, the high concentration emitter region and the high concentration base region, and a step of depositing a metal layer on the surface of the insulating film including the contact hole. , forming a desired photoresist pattern on the surface of the metal layer, and then processing the metal layer by dry etching using gas plasma such as carbon tetrachloride using the photoresist pattern as a mask to form metal wiring. This method is characterized in that the metal wiring on the lowest potential layer is prevented from being corroded by a current caused by a local battery flowing between the scribe line and the lowest potential layer in the metal wiring forming step. The present invention relates to a method for manufacturing a semiconductor device.

以下、本発明の実施例を第２図を参照にして説
明する。まず半導体基板２１上にｎ型エピタキシ
ヤル層２２を形成し、その後フオトリソグラフイ
技術及び拡散技術をもちい、ｎ型エピタキシヤル
層２２内にスクライブ線内のｎ型層２６，ｐ型最
低電位層２７，n⁺型コレクタ層２８，ｐ型ベー
ス領域２３，n⁺型エミツタ領域２９，p⁺型高濃
度ベース領域３０，を形成する。その後絶縁膜２
４を形成し、所要の部分にのみ、フオトリソング
ラフイ技術をもちいて、コンタクト穴を形成す
る。この時、スクライブ線領域のｎ型層２６はエ
ツチングせず、絶縁膜を残すことが本発明の特徴
である。しかる後、真空蒸着法等により、金属層
２５を形成する（第２図ａ）。その後、フオトリ
ソグラフイ技術により、所要のレジストパターン
３１を形成する（第２図ｂ）。しかる後、四塩化
炭素等のガスプラズマを用いたドライエツチ法に
より不要な部分の金属層を除去する（第２図ｃ）。
この時、スクライブ線上には絶縁膜が形成されて
いいる為、スクライブ線と、最低電位層の間でル
ープ電流が流れることもなく、従つて金属配線が
腐触されることもない。その後、フオトレジスト
３１を除去し、金属配線の形成が完成する（第２
図ｄ）。 Hereinafter, embodiments of the present invention will be described with reference to FIG. First, an n-type epitaxial layer 22 is formed on a semiconductor substrate 21, and then a photolithography technique and a diffusion technique are used to form an n-type layer 26 within a scribe line and a p-type lowest potential layer 27 within the n-type epitaxial layer 22. , an n ⁺ type collector layer 28, a p type base region 23, an n ⁺ type emitter region 29, and a p ⁺ type high concentration base region 30. Then insulating film 2
4, and contact holes are formed only in required portions using photolithography technology. At this time, the feature of the present invention is that the n-type layer 26 in the scribe line region is not etched and the insulating film remains. Thereafter, a metal layer 25 is formed by vacuum evaporation or the like (FIG. 2a). Thereafter, a required resist pattern 31 is formed by photolithography (FIG. 2b). Thereafter, unnecessary portions of the metal layer are removed by a dry etching method using gas plasma of carbon tetrachloride or the like (FIG. 2c).
At this time, since an insulating film is formed on the scribe line, no loop current flows between the scribe line and the lowest potential layer, and therefore the metal wiring is not corroded. After that, the photoresist 31 is removed and the formation of metal wiring is completed (second
Figure d).

このようにして、腐触のない高信頼性の金属配
線の形成が可能となつた。 In this way, it has become possible to form highly reliable metal wiring free from corrosion.

[Brief explanation of drawings]

第１図は、従来のスクライブ線構造を有する半
導体装置の断面図である。第２図は、本発明の実
施例の断面図である。なお図中の記号は、１，２１……半導体基板、
２，１２……ｎ型エピタキシヤル層、３，１３…
…ｐ型ベース領域、４，１４……絶縁膜、５，１
５……金属配線層、６，１６……スクライブ線内
のｎ型層、７，１７……ｐ型最低電位層、８，
１８……n⁺型コレクタ層、９，１９……n⁺型エ
ミツタ層、１０，３０……p⁺型高濃度ベース領
域、１１，３１……フオトレジスト層、１２……
金属配線腐触部である。 FIG. 1 is a sectional view of a semiconductor device having a conventional scribe line structure. FIG. 2 is a cross-sectional view of an embodiment of the invention. The symbols in the figure are 1, 21...semiconductor substrate,
2, 12... n-type epitaxial layer, 3, 13...
...p-type base region, 4,14...insulating film, 5,1
5... Metal wiring layer, 6, 16... N-type layer in the scribe line, 7, 17... P-type lowest potential layer, 8,
18...n ⁺ type collector layer, 9, 19... n ⁺ type emitter layer, 10, 30... p ⁺ type high concentration base region, 11, 31... photoresist layer, 12...
This is a corroded part of the metal wiring.

Claims

[Claims] 1. An opposite conductivity type epitaxial layer is formed on a semiconductor substrate of one conductivity type, and a lowest potential layer of one conductivity type is formed in the epitaxial layer, penetrating the epitaxial layer and reaching the substrate. A scribe line region is formed in one of the epitaxial layers electrically isolated by the lowest potential layer, a transistor activation region is formed in the other, and a high concentration layer of an opposite conductivity type is formed in the scribe line region. A highly doped collector layer of opposite conductivity type and a base region of one conductivity type are formed in the active region of the transistor, and a highly doped base region of one conductivity type and a highly doped base region of opposite conductivity type are further formed in the base region of one conductivity type. After forming the emitter region, there is a process of forming an insulating film on the entire surface, leaving the insulating film on the high concentration layer formed on the scribe line region and inside the scribe line region, and leaving the insulating film on the lowest potential layer and the high concentration layer in the active region of the transistor. forming a contact hole by removing the insulating film only from each electrode lead-out portion on the concentrated collector layer, the highly concentrated emitter region, and the highly concentrated base region; and depositing a metal layer on the surface of the insulating film including the contact hole. a step of forming a desired photoresist pattern on the surface of the metal layer, and then processing the metal layer by a dry etching method using gas plasma such as carbon tetrachloride using the photoresist pattern as a mask to form metal wiring. and thereby preventing the metal wiring on the lowest potential layer from being corroded due to a current caused by a local battery flowing between the scribe line and the lowest potential layer in the metal wiring forming step. A method for manufacturing a semiconductor device, characterized by: