JPH0251252B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to the manufacture of semiconductor devices, and more particularly to improvements in methods for forming metal wiring patterns.

[Technical background of the invention]

2. Description of the Related Art Semiconductor devices are configured to have various impurity regions formed in a semiconductor layer such as silicon, and to connect these impurity regions with a wiring layer to perform a predetermined function. For example, bipolar type
Figure 2 shows a cross-sectional view of the NPN transistor portion of the IC.

As shown in the figure, an N-type epitaxial layer 2 grown on a P-type silicon substrate 1 includes a P-type base region 3, an N ⁺ -type emitter region 4, a P ⁺ -type base contact region 5, and an N ⁺ -type collector contact. A region 6 is formed, and various impurity regions such as a P ⁺ type isolation diffusion layer 7 and an N ⁺ type buried region 8 for isolating the N type collector region are further formed. These impurity regions have conductivity types depending on their respective functions, and are formed with different impurity concentrations and diffusion depths. Further, the surface of the epitaxial layer is covered with a field oxide film 9, and aluminum wiring layers such as electrodes 10 ₁ to 10 ₄ are patterned on the field oxide film.

10 ₁ is the emitter electrode, 10 ₂ is the base electrode, 1
0 ₃ is a collector electrode, which is in ohmic contact with the corresponding impurity region through a contact hole.

By the way, the aluminum wiring layer in the above-mentioned semiconductor device is formed by forming a field oxide film 9 and opening a contact hole, then depositing an aluminum film thereon, and selectively etching this by photolithography. It is formed by patterning into a predetermined shape. In this case, as an etching method when a metal film such as aluminum is used as a wiring material, wet etching, which is performed by immersing the film in an etching solution, is mainly adopted.

[Problems with background technology]

As mentioned above, various impurity regions in a semiconductor device are formed with different conductivity types and different impurity concentrations depending on their functions, so there is a potential difference of about 0.01 mV between these impurity regions. ing. As a result, the following problems occur in the conventional wiring formation method using wet etching.

In the conventional wiring forming method, first, as shown in FIG. 3A, an aluminum evaporated film 10 is formed on the field oxide film 9, and then a resist pattern 11 is formed to cover the planned wiring pattern area. Wet etching is performed on the aluminum vapor deposited film 10 using 11 as a mask. Note that an impurity region A with a high internal potential and an impurity region B with a low internal potential are formed in the silicon substrate under the field oxide film 9, and the aluminum vapor deposited film 10 is applied to both the impurity regions A and B through the contact hole. We are in contact with each other. In this case, in a state where the aluminum film 10 is still continuous without being divided into individual patterns as shown in FIG. 3A, the aluminum film 10 has a uniform potential, and therefore the resist pattern 11... Etching progresses at a uniform speed in areas not masked.

However, as selective etching progresses and the aluminum film 10 is divided into a wiring portion 10a in contact with impurity region A and a wiring portion 10b in contact with impurity region B, both wiring portions 10a,
A potential difference occurs in the wiring pattern 10b corresponding to the internal potential of the impurity regions A and B, and the wiring pattern 10a has a high potential.
will be etched faster. the result,
When etching is continued to form a wiring pattern with a predetermined width, the wiring pattern 10b is formed to have a predetermined width as shown in FIG. This will cause variations in the results.

When we specifically investigated this problem with respect to the width of the aluminum wiring layer formed by wet etching, we found that the width of the wiring pattern 10b was 3.477μ, while the width of the wiring pattern 10a, which has a high potential, was 3.477μ.
At 3.13μ, a thinning of 0.34μ occurred.

Furthermore, in recent semiconductor devices where the width of wiring patterns has become significantly narrower due to the progress of miniaturization of elements, the above problem can be caused by open wiring defects or by complete disappearance of wiring patterns as shown in Figure 4. (The missing wiring is indicated by a broken line in the diagram)
It became clear that this would lead to a serious situation.

[Object of the Invention] The present invention has been made in view of the above circumstances, and improves the method of forming metal wiring patterns in semiconductor devices by wet etching. The present invention provides a method for forming a metal wiring pattern for a semiconductor device, which can form a metal wiring pattern with a uniform width.

[Summary of the invention]

A method for forming a metal wiring pattern for a semiconductor device according to the present invention includes forming a metal wiring pattern on an insulating film formed to cover a surface of a semiconductor layer in which various impurity regions are formed, through contact holes formed in the insulating film. A method of depositing a metal film in ohmic contact with an impurity region, and then patterning the metal film by selectively wet etching to form a plurality of interconnect patterns separated from each other and having a predetermined width, The method is characterized in that, after the metal film is separated corresponding to at least the individual wiring patterns, substantially the same voltage is applied to the separated metal films.

The method of the present invention will now be described with reference to FIGS. 1A to 1C.

The present invention prevents potential differences from occurring between separated patterns by applying a constant voltage to a metal film to be patterned.
Figure A shows the principle. This figure is drawn corresponding to FIG. 3B, where A is an impurity region with a high internal potential, and B is an impurity region with a low internal potential.
Therefore, as in the case of FIG. 3B, the internal potentials of the divided aluminum wiring portions 10a and 10b are similarly different. However, in the present invention, both wiring patterns 10a and 10b are connected to the external power source 1.
2, the wiring patterns 10a and 10b are fixed at the same potential _E0 .
can be formed with a uniform width.

Wiring portions 10a, 10 divided as above
For example, as shown in FIG. _1B , when the semiconductor wafer 22 is immersed in a quartz beaker 21 filled with an etching solution to perform etching, the wafer 22 is connected to an external power supply. 12 should be connected. Furthermore, instead of connecting the semiconductor wafer to an external power source, a platinum electrode 23 may be immersed in an etching solution and connected to the external power source 12 as shown in FIG. 1C.

Note that the application of the potential E ₀ by the external power source 12 may be performed from the beginning of etching, or may be applied from the time when the aluminum deposited film 10 is divided into each wiring pattern portion.

[Embodiments of the invention]

Examples of the present invention will be described below.

A semiconductor wafer on which a wiring aluminum film having a thickness of 1.0 .mu.m was deposited and a predetermined resist pattern formed thereon was subjected to wet etching by the method described with reference to FIG. 1B to form an aluminum wiring layer.

Note that an orthophosphoric acid solution was used as the etching solution, and the etching temperature was 50°C. In addition, when the voltage E ₀ of the external power supply 12 is +0.6V and -
Etching was conducted for both cases at 0.6 V, and as a comparative example, the same wafer was etched without using an external power source.

As a result of the above example, in the comparative example in which the external power supply 12 was not used, open failures and thinning occurred in the special wiring pattern that contacted the impurity region with a high internal potential, but in the example in which it was connected to an external power supply, A uniform acid ray pattern was obtained in all cases.

When the etching rate was measured in each case, the following results were obtained.

(1) When external power supply potential E ₀ = +0.6V: 1368.25Å/min (2) When external power supply potential E ₀ = -0.6V: 1046Å/min (3) When external power supply potential E ₀ = 0: 1112.5Å/min min The reason for this difference in etching speed is
This is because the Al dissolution reaction described below differs depending on the voltage/current in the etching solution.

H ₃ PO ₄ 3H ⁺ +PO ₄ ^--- AlAl ⁺⁺⁺ +3e ^-The above results mean that the etching speed can be controlled at the same time as making the wiring pattern width uniform as described above.

Note that the voltage of the external power supply is the difference between the internal potentials.
It is desirable to make it 100 times or more.

〔Effect of the invention〕

As detailed above, according to the present invention, when forming a metal wiring pattern in a semiconductor device by wet etching, the metal wiring pattern connected to various impurity regions having different internal potentials is formed with a uniform width. In addition, remarkable effects such as being able to control the patterning speed can be obtained.

[Brief explanation of drawings]

1A is an explanatory diagram showing the principle of a method for forming a metal wiring pattern in a semiconductor device according to the present invention, FIG. 3A and 3B are cross-sectional views showing an example of a pattern, and FIG. 3A and B are cross-sectional views for explaining a conventional wiring pattern forming method and its problems, and FIG. It is a wiring pattern diagram shown in FIG. 10... Aluminum vapor deposited film, 10a, 10b
...Wiring pattern, 11...Resist pattern,
12... External power supply, 21... Quartz beaker filled with etching solution, 22... Semiconductor wafer, 23...
...Platinum electrode.

Claims (1)

[Claims] 1. On an insulating film formed covering the surface of a semiconductor layer on which various impurity regions are formed, a metal film is vapor-deposited in ohmic contact with the various impurity regions through contact holes opened in the insulating film. After that, the metal film is patterned by selective wet etching to form a plurality of wiring patterns that are separated from each other and have a predetermined width. 1. A method for forming a metal wiring pattern for a semiconductor device, which comprises applying substantially the same voltage to the separated metal films after they are separated in accordance with the wiring pattern.