JPS6344307B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a nonvolatile semiconductor memory device,
In particular, the present invention relates to an electrically rewritable nonvolatile semiconductor memory device having a novel structure.

Conventional non-volatile semiconductor memory devices of this type include what is generally called a stacked gate type memory; for example, ISSCC'77 Digest of
One example is given in Technical Papers, 15-4. As stated in this reference,
This stacked gate memory has gates arranged at intervals near the main surface of a P-type semiconductor substrate.
It has a pair of source and drain N-type regions, a floating gate electrode wrapped in a SiO ₂ film on the main surface between these regions, and a control gate electrode thereon. In this stacked gate type memory, at the time of fabrication, that is, when the floating gate electrode is in a neutral state, the initial threshold voltage as seen from the control gate electrode, e.g.
V _T0 =2V exists. In the write operation, when the substrate and the source terminal are grounded and a positive pulse high voltage, for example 25V, is applied to the control gate electrode and the drain terminal, a channel current flows, and this current reduces the high energy generated in the pinch-off region near the drain. Electrons are injected into the floating gate electrode through a so-called channel, and the threshold voltage shifts to, for example, V _T =10V. The erase operation is performed by irradiating the written memory with ultraviolet light to excite the injected electrons in the floating gate to energy, which is emitted into the substrate and returns the threshold voltage of the memory to V _T0 . Therefore, when reading, for example, the control gate electrode
When 5V is applied, the erased memory becomes conductive and
The written memory is non-conductive, and from this “1”,
A storage state of “0” can be detected. However, when attempting to add the function of electrical erasing to such a memory device, the biggest problem that arises no matter what method or mechanism is used is the difficulty of recovering the initial threshold voltage by erasing. In other words, it often happens that the threshold voltage cannot be returned to the initial value due to erasing, or it may return too much than the initial value, and this phenomenon becomes more and more noticeable especially when a large number of memories are integrated. , is a factor that hinders practical application.

The purpose of the present invention is to make it possible to stably and easily add electrical erasing characteristics to the stacked gate memory as described above, to simplify the manufacturing process, and to avoid the above-mentioned problems. It is an object of the present invention to provide a nonvolatile semiconductor memory device that has advantages such as improved integration, improved reliability, and stabilized characteristics.

In the nonvolatile semiconductor memory device of the present invention, source and drain regions of conductivity type opposite to that of the substrate are provided at intervals near the main surface of the semiconductor substrate, and a first drain region is provided on the main surface of the substrate between these regions. A stacked gate MOS type memory comprising a gate insulating film, a floating gate electrode made of a conductive film on top of this, a second gate insulating film on top of this, and a control gate electrode made of a conductive film on top of this. a transistor, and a MOS transistor connected in series to the memory transistor, having the drain region of the memory transistor as a common source region, and having a gate electrode commonly connected to the control gate electrode of the memory transistor, and having a common gate electrode as the entire device. The threshold voltage seen from the data is determined by the stacked gate MOS type transistor in the write state and by the MOS transistor in the erase state. In another device of the invention, the first gate insulator of the stacked gate MOS memory transistor is thinner than the gate insulator of the MOS transistor. In another device of the invention, the floating gate electrode of the stacked gate MOS memory transistor is shaped at least partially in self-alignment with the control gate electrode. Furthermore, in another device of the present invention, the floating gate electrode and control gate electrode of the stacked gate MOS type memory transistor and the gate electrode of the MOS transistor are all made of polycrystalline silicon.

In the nonvolatile semiconductor memory device of the present invention, a so-called channel injection method can be used for write operations.
That is, by injecting electrons into the floating gate electrode of the channel current of the stacked gate MOS type memory transistor to increase the threshold voltage, the threshold voltage of the entire device can be increased. Also, so-called avalanche injection can be used for the erase operation. In other words, stacked
By avalanche-breaking down the P-N junction between the source and substrate of a gate MOS type memory transistor and injecting the high-energy holes generated at this time into the floating gate electrode, stacked
By lowering the threshold voltage of the gate MOS type memory transistor and setting conditions so that this threshold voltage becomes a value lower than the threshold voltage of the MOS transistors connected in series, the threshold voltage of the entire device after erasing is set as follows. The threshold voltage of the MOS transistor can always be ensured.

As explained above, in the nonvolatile semiconductor memory device of the present invention, not only can writing and erasing operations be performed electrically, but also the threshold voltage of the entire device after erasing can be set as a threshold voltage regardless of the storage state of the device. A fixed value can be secured. It is easy to understand that this not only guarantees the stability and ease of implementation of this device, but also serves as the biggest factor in making the electrical erasing operation itself possible. Further, the nonvolatile semiconductor memory device of the present invention includes:
Although it is composed of a stacked gate MOS type memory transistor and a MOS transistor, it can be realized substantially as one element, thereby ensuring a high degree of integration and a high manufacturing yield.

Next, in order to make the features of the present invention easier to understand, embodiments will be described in detail with reference to the drawings.

FIG. 1 is a plan view of an embodiment of the nonvolatile semiconductor memory device of the present invention, and FIG. 2 is an A of FIG.
-A sectional model diagram of the device at section A'. In these figures, the same parts of the apparatus are labeled with the same symbols. In Figures 1 and 2, 1 is about a specific resistance of 10
Ω-cm P-type single crystal Si semiconductor substrate, 2 is the main surface of 1 having a plane index (100), 3 is a first gate with a thickness of about 300 Å formed by thermal oxidation of the Si substrate
SiO ₂ film, 4 is a floating gate electrode made of polycrystalline Si with a thickness of about 0.3 μm doped with phosphorus, and 5 is a second gate with a thickness of about 1000 Å formed by the thermal oxidation method of 4.
SiO ₂ film, 6 is a polycrystalline film with a thickness of approximately 0.5μ with phosphorus added.
Control gate electrodes 7 and 8 made of Si are N-type source and drain regions formed by diffusing phosphorus into 1 near 2. These constitute a so-called stacked gate MOS type memory transistor, in which the planar shape of the floating gate electrode 4 is partially determined in a self-aligned manner by etching polycrystalline Si using the control gate electrode 6 as a mask. In addition, source region 7 and drain region 8 are formed by diffusing phosphorus in a self-aligned manner with respect to both gate electrodes 4 and 5. In the device of this invention, the above-mentioned stacked
MOS in series with gate MOS type memory transistor
A transistor is formed, and 9 is a gate with a thickness of about 1000 Å grown by thermal oxidation of the Si substrate 1.
SiO ₂ film, 10 is a gate electrode made of polycrystalline Si with a thickness of about 0.5 μm doped with phosphorus, 11 is a gate electrode made of polycrystalline Si with phosphorus added to the main surface 2
This is a drain region formed by diffusing phosphorus into the nearby Si substrate 1. In this MOS transistor, the source region is common to the drain region 8 of the stacked gate MOS memory transistor, and the source region 8 and drain region 11 diffuse phosphorus in a self-aligned manner with respect to the gate electrode 10. As is clear from FIG. 1, the gate electrode 10 is commonly connected to the control gate electrode 6 of the stacked gate MOS type memory transistor. The source lead-out A1 electrode 12 of the device as a whole is connected to the source region 7 through a contact hole 13, and the drain lead-out A1 electrode 14 is connected to the drain region 11 through a contact hole 15, and is further connected to the control gate of the stacked gate MOS type memory transistor. A common gate lead-out A1 electrode 16 for the electrode 6 and the gate electrode 10 of the MOS transistor is connected to both gate electrodes through a contact hole 17.
FIG. 3A is a symbolic diagram of the nonvolatile semiconductor memory device of the present invention, where _T1 indicates a stacked gate MOS type memory transistor section, _T2 indicates a MOS transistor section, and each terminal of the base, source, gate, and drain. The voltages applied to are indicated by the symbols V _B , V _S , V _G , and V _D, respectively. FIG. 3B shows one typical example of the terminal voltages during write and erase operations. In the write operation, the gate electrode V _G =
Due to 25V, both T ₁ and T ₂ are in conduction state,
A divided voltage of V ₁ = 25V is applied to the drain of the memory transistor T ₁ according to the conductance ratio of T ₁ and T ₂ , and at this time, electrons are injected into the floating gate electrode by the channel current flowing through T ₁ . A so-called channel injection write occurs. This channel injection increases the threshold voltage V _T of the memory transistor T ₁ . Next, in the erase operation, the voltage applied to the source of the memory transistor _T1 is
V _S = 25V causes avalanche breakdown in the gate control diode between the source N-type region and the P-type substrate, and the generated high-energy holes are injected into the floating gate electrode, increasing the threshold of the memory transistor _T1. The voltage will drop.
Figure 3C shows the voltage conditions shown in Figure 3B.
One typical characteristic diagram is shown when the erasing time is set to T _W =1 ms and T _E =10 ms, respectively. In this figure, the threshold voltage is 1V due to the characteristics of the MOS transistor _T2 . Also, the threshold voltages are +10V and -5V, respectively, based on the characteristics after writing and erasing of the stacked gate MOS type memory transistor. Therefore, the threshold voltage of the entire device is +10V determined by the stacked gate MOS type memory transistor _T1 after writing, and +10V determined by the MOS transistor T1 after erasing.
It is determined by T ₂ and becomes +1V. This device also has excellent characteristics in terms of reliability and stability, such as repeated memory retention/writing/erasing operations.

The embodiments described above are merely illustrative;
It is clear from the above description that the present invention is not limited to this. That is, the material and manufacturing method of each part of the device can be changed, and the conductivity type and conductivity type impurity can be freely selected. It is also possible to change the dimensions of each part of the device within a certain range. In short, various modifications can be made by those skilled in the art without departing from the spirit and scope of the invention as described in this specification and the appended claims.

[Brief explanation of drawings]

FIG. 1 is a plan view of a nonvolatile semiconductor memory device of the present invention, and FIG. 2 is a cross-sectional view taken along the line AA' in FIG. FIG. 3A is an equivalent circuit diagram of the device of the present invention, FIG. 3B is a diagram showing typical terminal voltage conditions during writing and erasing, and FIG. 3C is a typical characteristic diagram. In addition, in FIGS. 1 and 2, 1... Si single crystal semiconductor substrate, 2... Main surface of 1, 3... Thin first
Gate SiO ₂ film, 4...polycrystalline Si floating gate electrode,
5... Second gate SiO ₂ film, 6... Polycrystalline Si control gate electrode, 7, 8, 11... Source, drain region, 9... Gate SiO ₂ film, 10... Polycrystalline Si
Gate electrode, 12, 14, 16... Source, drain, gate A1 extraction electrode, 13, 15, 1
7... Source, drain, and gate contact holes.

Claims (1)

[Scope of Claims] 1. A pair of source and drain regions of opposite conductivity types provided at a distance from each other near the main surface of a semiconductor substrate of one conductivity type, and on the main surface of the substrate between the two regions. a first gate insulating film provided on the floating gate electrode, a floating gate electrode made of a metal or semiconductor layer provided thereon, a second gate insulating film provided on the floating gate electrode, and a floating gate electrode provided on the floating gate electrode made of a metal or semiconductor layer; It has a stacked gate MOS type memory transistor having a control gate electrode made of a metal or semiconductor provided on a gate insulating film, and further has a MOS transistor connected in series to the memory transistor, and a gate electrode of the MOS transistor. A nonvolatile semiconductor memory device in which a gate electrode and a source region are commonly connected to a control gate electrode and a drain region of the stacked gate MOS memory transistor, respectively,
A high voltage is applied to the drain electrode of the MOS transistor for writing, a low voltage is applied to the gate electrode, and a high voltage is applied to the source electrode of the stacked gate type MOS memory transistor for erasing, thereby setting the threshold of the memory device. 1. A nonvolatile semiconductor memory device characterized in that a voltage is determined by the stacked gate MOS type memory transistor in a write state and by the MOS transistor in an erase state. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the first gate insulating film of the stacked gate MOS type memory transistor is thinner than the gate insulating film of the MOS transistor. 3. The nonvolatile device according to claim 1 or 2, wherein the floating gate electrode and the control gate electrode of the stacked gate MOS type memory transistor have at least a partially identical planar arrangement shape. Semiconductor storage device. 4. Claims 1, 2, or 4, wherein each of the floating gate electrode and control gate electrode of the stacked gate MOS type memory transistor and the gate electrode of the MOS transistor are made of polycrystalline silicon. 4. The nonvolatile semiconductor memory device according to item 3.