JPS6346676B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an electric motor control apparatus, and more particularly to an electric motor control apparatus for digitally controlling an inverter-driven electric motor using a digital arithmetic circuit. In recent years, demand for variable speed electric motors has increased as electric motors or devices incorporating electric motors have become more sophisticated, and various attempts have been made to improve their control accuracy. One method uses an inverter that employs a power element with a high switching speed in the power supply circuit for controlling the speed of the electric motor, and controls the input of the electric motor by pulse width modulation or chopper control. In controlling such a variable speed electric motor, a control circuit is generally configured for each control target. Recently, a control device using a microcomputer has been announced for the purpose of increasing the functionality of the control device, and when configuring the control device using this microcomputer, it is necessary to control many control objects at once. Therefore, when using a microcomputer to control an electric motor, for example, it is desirable to comprehensively control each control object. However, if the motor is controlled by a pulse width modulation signal as described above, the effective time width of pulse processing becomes small, making it difficult to increase the processing speed. . The present invention has been made in view of these problems, and its purpose is to increase the frequency of the clock signal by expanding the effective time width of pulse processing in the processing time determined by the clock signal. The purpose of this is to increase the processing speed and enable high-speed processing. The present invention uses input information representing the operating state of the electric motor, digitally processes this input information, and uses a plurality of registers that can hold the processed data according to each processing content. We are prepared. Each of these registers not only holds data obtained through arithmetic processing, but also includes registers that hold data representing predetermined values. What the data held in these registers have in common is that these data are used as reference values for comparison operations.
Therefore, these registers will hereinafter be referred to as a reference register group, and the data held within this reference register group will be referred to as a reference register. Furthermore, it is equipped with a plurality of registers that hold data representing the instantaneous state of the motor and other objects, and these registers are hereinafter simply referred to as the instantaneous register group, and the data held in this instantaneous register group is referred to as instantaneous data. I'll decide. In the present invention, a reference register group, an instantaneous register group, an incrementer/decrementer for increasing or decreasing data by 1 or setting data to 0, and an incrementer/decrementer for controlling the incrementer/decrementer. It includes a decrementer controller, a comparison circuit, a holding circuit for holding the comparison results from the comparison circuit, and a stage counter. This allows each stage to be processed economically in the order predetermined by the stage counter. At each stage, in order to perform the work determined at that stage, a predetermined register is selected from the reference register group and the instantaneous register group, and the reference data and instantaneous data from each register are sent to the comparator circuit, This comparison result is held by the holding circuit. That is, the present invention provides a speed command means for giving a speed command to an electric motor, a plurality of detection means for detecting the speed of the motor or the position of a rotor, and arithmetic processing of the output signals of these plurality of detection means as digital control variables. a digital arithmetic circuit that converts the output of the digital arithmetic circuit into a predetermined pulse output, a pulse input/output circuit that converts the output of the digital arithmetic circuit into a predetermined pulse output, and a control means for controlling a plurality of digital control amounts of the electric motor based on the output of the pulse input/output circuit. A reference register group for holding the output of the digital arithmetic circuit, an instantaneous register group for holding the detection signals of the plurality of detection means, and an output register group for sampling the output of the instantaneous register group. , a comparison circuit for comparing the data held in each register selected from the reference register group and the instantaneous register group, a comparison output latch circuit for holding the comparison result by the comparison circuit, and a comparison circuit for comparing the data held in each register selected from the reference register group and the instantaneous register group; The data in the instantaneous register is +1, -1, or cleared, and returned to the instantaneous register again.Incrementer/decrementer for updating the instantaneous register data, and stage counter for time-division control of each process. The stage counter is controlled by predetermined first and second clock signals, the counting operation of the stage counter is started by the first clock signal, and the stage latch is started in synchronization with the second clock signal. A control device for an electric motor is characterized in that it is configured to hold a stage signal in a circuit. Furthermore, at each stage, the instantaneous data held in the instantaneous register related to that stage is rewritten in accordance with the actual instantaneous state of the motor, etc. This rewriting operation is performed by an incrementer/decrementer and an incrementer/decrementer controller. In other words, data representing instantaneous time or data representing instantaneous rotation angle of phase angle rotation should be increased depending on the generation state of the time signal representing the standard unit of time or the phase angle signal representing the rotation angle unit of the motor shaft. The incrementer/decrementer controller determines whether the value should be decreased. Based on this judgment result, the incrementer/decrementer specifically increases or decreases the instantaneous data. In this way, the instantaneous data is rewritten with new values from time to time, and a comparison operation is performed using this data. Through this comparison, a pulse output commensurate with the reference data can be generated. By adopting such a configuration, complex control is possible with a relatively simple circuit configuration. Furthermore, since irregularly input pulse signals are synchronized and detected, each signal can be detected accurately and the incrementer/decrementer can operate accurately. Next, an embodiment of the present invention of a motor with a phase detector (non-commutator motor) will be described with reference to the drawings. 1st
The figure shows the circuit configuration of a control device for a motor with a phase detector. The microcomputer is composed of a central processor (hereinafter referred to as CPU) 114, a random access memory (hereinafter referred to as RAM) 116, and a read-on memory (hereinafter referred to as ROM) 118. The input/output circuit 120 includes an interface circuit 123 with the CPU 114, an analog/digital conversion circuit 124 (hereinafter referred to as an A/D converter) equipped with a multiplexer 122, an A/D converter 127 without a multiplexer, and a pulse output circuit. 126,
It has a pulse input circuit 128 and a discrete input/output circuit 125. 6 thyristors 186
~191, 6 flywheel diodes 19
3-phase inverter 160 composed of 2 to 197
The electric motor 100 is varied by. In addition, the DC power source connects the commercial AC power source 185 to the diode 176 to
179 and a smoothing capacitor 135. Further, a phase detector 150 is attached to the electric motor 100, and the phases of the windings U-phase, V-phase, and W-phase are detected. Its phase detection signal PU, PV, PW
Output. Furthermore, pulse outputs U ⁺ , U ^- , V ⁺ , V ^- , W ⁺ , W ^- output from the input/output circuit 120
ignites and extinguishes the thyristors 186 to 191 via the gate driver 130. The power device used here is a self-extinguishing thyristor, such as a gate turn-off thyristor GTO.
This is convenient in terms of circuit configuration. The microcomputer and input/output circuit 120 interfaces are connected by a data bus 162, an address bus 164, and a control bus 166. The microcomputer and input/output circuit 120 receive an enable signal E from the CPU 114.
is applied and synchronization is achieved. As analog inputs, two resistors 137 and 1
DC voltage E _D divided by 38, shunt resistor 1
_DC current ID of 36, motor temperature T _M of temperature sensor 104 attached to motor 100, speed command S _P
There is. Among these inputs, the important analog input is the _DC current ID. This DC current ID is passed through an amplifier 131 to an A/ _D converter without a multiplexer.
It is input to converter 127. Other DC voltages
E _D , motor temperature T _M , and speed command S _P are input to A/D converter 124 via amplifiers 132 to 134 and multiplexer 122, respectively. The multiplexer 122 selects one of the analog inputs commanded by the CPU 114 and inputs it to the A/D converter 124 . These inputs are input to the CPU 11 based on the instruction program stored in the ROM 118.
The address of 4 is specified via the address bus, and the specified analog input is taken in. Further, the digitally converted values are held in registers corresponding to the respective inputs, and are sent via the data bus 164 as necessary. Phase signals PU, PV, and PW are inputted to the pulse input circuit 128 from the phase detector 150 and synchronized with the enable signal E. Furthermore, data processed by the CPU 114 is taken into the interface 123 and held in the pulse output circuit 126. The output from the pulse output circuit 126 generates a signal with a pulse width corresponding to the signal inputted by the interface 123, and the output is a pulse width modulated signal U ⁺ , V ⁺ ,
These signals are W ⁺ , U ^- , V ^- , and W ^- , and these signals are designed to generate outputs after a start command is input to the discrete input/output circuit 125. FIG. 2 is a diagram showing the timing at which the pulse width modulation signals U ⁺ , V ⁺ , W ⁺ , U ^- , V ^- , W ^- are generated by the pulse output circuit 126, and the signal PWM is generated by the pulse output circuit 126. The generated carrier signal is reset at the rising and falling edges of the phase detection signals PU, PV, and PW, and increases and decreases with a certain slope.
Compare with the data D1 level from CPU114,
Modulation is applied only to the latter 60 degrees of 120 degrees of energization. Similarly, for the data D2 level of the CPU 114, the pulse width is narrowed only at the rising edge of the first half of 60 degrees, and the respective pulse width modulation signals U ⁺ , V ⁺ , W ⁺ , U ^- , V ^- , W ^- are generated. FIG. 3 shows the circuit configuration of a motor (induction motor) without a phase detector. FIG. 3 is almost the same as FIG. 1, with a pulse generator 152 replacing the phase detector 150 of FIG. A thyristor 198 and a resistor 181 are provided for voltage control, and voltage control is performed by chopping the thyristor 198. For this purpose, the chopper signal CHOP of the pulse output circuit 126 of the input/output circuit 120 is used. FIG. 4 shows that the pulse output circuit 126 generates 15 unequal pulse width modulated signals U ⁺ , V ⁺ , W ⁺ ,
It indicates the timing of creating U ^- , V ^- , W ^- .
It is created from carrier signal PWM and modulated waves SU, SV, and SW. FIG. 5 shows a specific circuit of the pulse output circuit 126, and the register group 570 is the reference register group mentioned above, and is used to hold data processed by the CPU 114 or to store a predetermined constant value. Holds data that indicates a value. This data is
The data is sent from the CPU 114 via the data latch 802 and write bus 806 as shown in FIG. The designation of each register holding data in the reference register group 570 is performed from the address bus 164 via the address decoder 906.
The above data is input to the designated register and held. The register group 572 is a momentary register group and holds the instantaneous state of the electric motor and the like. The instantaneous register group 572, latch circuit 576, and incrementer/decrementer 578 provide a so-called counter function. The output register group 574 includes, for example, a register that holds the rotational speed of the motor and a register that holds the period of pulse input. These values are obtained by reading the values of instantaneous registers when certain conditions are met. Output register group 574
A related register is selected by signals sent from the CPU via an address bus and a control bus, and the data held in the CPU 114 is sent from this register via a read bus 808 to the CPU 114. Comparator circuit 580 receives reference data from a selected register of reference register group 570 and instantaneous data from a selected register of instantaneous register group 572 at inputs 582 and 584, respectively;
Perform a comparison operation. The comparison result is output from output terminal 586. The output terminal is set to a predetermined latch in a first comparison output latch group 602 which acts as a comparison result holding circuit. Furthermore, it is then set in a predetermined latch of the second comparison output latch group 604. Reference register group 570, instantaneous register group 57
2. Read and write operations of the output register group 574, operations of the incrementer/decrementer 578 and comparison circuit 580, first comparison output latch group 60
2. The output setting operation to the second comparison output latch group 604 is processed within a predetermined time. Further, various processes are performed in a time-sharing manner according to the stage order of the stage counter 670. A reference register group 570 and an instantaneous register group 5 for each stage
a predetermined register of each of the 72 register groups;
A predetermined latch in the first comparison output latch group 602 and, if necessary, a predetermined register in the output register group 574 is selected. Also the incrementer/
Decrementer 578 and comparator circuit 580 are commonly used for each register in reference register group 570 and instantaneous register group 572. FIG. 6 is a diagram for explaining the timing of FIG. 5. An enable signal E is supplied from the CPU 114 to the input/output circuit 120. This signal is shown in A. This enable signal E generates non-overlapping two-phase clock signals φ ₁ and φ ₂ by the non-overlap circuit 701 shown in FIG. This signal is shown in C and B. The circuit shown in FIG. 5 operates according to these clock signals _φ1 and _φ2 . FIG. 6D shows the output signal of the stage counter 670, which is counted at the rising edge of the clock signal _φ1 . However, the output signal of the stage counter 670 is established in the shaded area due to wiring and gate delays. The stage counter 670
The stage decoder 672 generates a processed signal for each stage. but,
Since the processed signals of each stage are delayed considerably from φ ₁ , the effective time of each process is shortened. In order to extend the effective time of each process, the stage latch 674
The output signal of the stage latch 674 is shown in E. In FIG. 6, "T" indicates that the latch circuit or register circuit is in an enabled state, indicating that the output of these circuits is dependent on the input. Further, "L" indicates that these circuits hold certain data and that the output of this circuit does not depend on the input. Stage latch 67 becomes “T” when φ ₂ =1
4 holds the output signal of the stage decoder 672, and E becomes the stage processing signal, which is switched at the rising edge of the clock signal _φ2 , and the processing of each stage is performed in synchronization with _φ2 . The stage signal shown in E becomes a readout signal for the reference register group 570 and instantaneous register group 572, and reads the data from a selected predetermined register. The bottom and the bottom show the operation of the reference register group 570 and the instantaneous register group 572, respectively. Reading of the reference register group 570 and the instantaneous register group 572 is performed by the stage signal E. Also, writing is performed with reference register group 570 and instantaneous register group 57 at φ ₁ =1.
This is done by setting 2 to "T", and is done in synchronization with _φ1 . The operation of data latch circuit 576 is shown in FIG.
This circuit is set to “T” by clock signal φ ₂ =1,
The data of a certain register read from the instantaneous register group 572 is written, and the clock signal φ ₂ =
When it is 0, it becomes “L”. In this way, data in a predetermined register in the instantaneous register group 572 corresponding to that stage is held. The data held in data latch circuit 576 is modified based on various conditions by incrementer/decrementer 578, which is not synchronized to the clock signal. Here, the incrementer/decrementer 578 is the incrementer/decrementer controller 5
It has the following functions based on the output signal 500 from the control signal generation circuit 591. The first function is an increment/decrement function that increases or decreases the value indicated by input data by one. The second function is a non-increment/decrement function, which allows input data to pass through without being increased or decreased. Third
The function is a reset function that changes all input data to data indicating a value of 0. Looking at the data flow of each register in the instantaneous register group 572, one of the instantaneous register group 572
One register is selected by the stage counter 672, and the data held therein is sent to the data latch circuit 5.
76 and an incrementer/decrementer 578 to a comparison circuit 580. Additionally, a closed loop is created from the output of incrementer/decrementer 578 back to the originally selected register. Therefore, when the incrementer/decrementer 578 functions to increment or decrement data by one, this closed loop functions as a counter. However, in this closed loop, the instantaneous register group 57
If a situation occurs in which the data of 2 is being output from a specific selected register, and the data is input in a loop, it will no longer have a counter function and will malfunction. Therefore, a data latch circuit 576 is provided to cut off the data. data·
The latch circuit 576 becomes “T” when the clock signal φ ₂ =1.
On the other hand, in the state "T" in which input data is written to the instantaneous register, the clock signal φ ₁ =1, so even if the data in a specific register in the instantaneous register group 572 is changed, the data latch circuit 576
The output of does not change. Its operation is shown in Figure 1. In other words, data cutting is performed with φ ₂ =0. Furthermore, the output data of the incrementer/decrementer 578 that is not synchronized with the clock signal is established as shown in the shaded area due to delays in wiring and gates. Similar to incrementer/decrementer 578, comparison circuit 580 also operates out of synchronization with the clock signal. The input of the comparison circuit 580 is the reference register group 57
0, the reference data of one reference register selected by the stage signal E and the instantaneous register group 57
2, a data latch circuit 576 for instantaneous data of one register selected by the stage signal H
and data communicated via incrementer/decrementer 578. The comparison result of these two data is “T” when the clock signal φ ₁ =1.
Among the first comparison output latch group 602, the latch selected by the stage signal H is set. At this time, the comparison result output signal of the comparator circuit 580 is shown in the blank, and the area where the signal is established is the shaded area. Further, the output of the first comparison output latch group 602 is set to the second comparison output latch group 604 which becomes "T" when the clock signal φ ₂ =1. These first and second comparison output latch groups 602,
The operations of 604 are shown in FIGS. Also, the output of the second comparison output latch group 604 is the motor inverter gate signal UP, VP,
It becomes the output signal of WP, UN, VN, WN and the chopper signal CH, becomes each condition of the instantaneous register group 572, and becomes the input signal of the incrementer/decrementer controller 590. Further, the output signal of the second comparison output latch group 604 is transferred from the instantaneous register group 572 to the output register group 57.
It also serves as a transfer signal for writing to 4. The operation of the output register group 574 is shown in FIG. Out of the output register group 574, the output register selected by the stage signal H outputs the instantaneous data of the instantaneous register selected by the stage signal H among the instantaneous register group 572 at "T" when the clock signal φ ₁ =1. is written, and becomes "L" when the clock signal φ ₁ =0. When the CPU 114 reads data held in the output register group 574, the CPU 114 specifies the register via the read bus 808, and
Data is taken in in synchronization with the clock signal E shown in FIG. Therefore, for example, the interface between the input/output circuit 123 and the CPU 114 is made by Hitachi.
When using the HD46800, the timing shown in FIG. 6 differs between the reference register group 570 to which data is written from the CPU 114 and the output register group 574 to which data is read to the CPU 114. Block diagrams of the data and addresses are shown in FIGS. Write data 806 written from the CPU 114 is held in the write latch circuit 802 which becomes “T” when φ ₂ =1, and is held by the write latch circuit 802 which becomes “T” when φ ₂ =1.
Then, data is written into the reference register selected by the address signal of the reference register group 570. Further, read data to be read to the CPU 114 is sent to the data bus 162 by the read bus 808 and the tri-state buffer circuit 804 which is enabled by the enable signal E=1 of the CPU 114, and is taken into the CPU 114. Further, the reference register group 570 and the output register group 574 are selected by an address signal from the CPU 114. As in the case of data, the timing of the register selection signal SEL differs between the reference register group 570 and the output register group 574. The reference register group 570 is held in an address latch circuit 902 that becomes "T" when φ ₂ =1, and then a chip select write signal is generated to determine whether write data or read data is to be written by a signal on the control bus. CSW, chip select read signal CSR
The output signal of the address latch circuit 902 or the address signal on the address bus 164 is selected depending on the address latch circuit 902 . Address latch circuit 90 for CSW
Select the output signal of 2, and select the address signal in the case of CSR. A register is selected by an address decoder 906 via this selection circuit 904. Furthermore, as described in FIGS. 1 and 3, since a controlled rectifying element is used in the inverter, the magnitude of the current of the element may become a problem, and the current may be further limited. Therefore, the input/output circuit 120 includes an A/D converter 124 to convert an analog quantity into a digital quantity. Other analog quantities required to control the electric motor include DC voltage and speed command. However, among the element current, DC voltage, speed command, etc., the most important analog quantity is the current of the control rectifier element.
Therefore, in FIG. 5, two A/D converters, an A/D converter 127 dedicated to the element current and an A/D converter 124 with a multiplexer 122, are connected to the input/output circuit 1.
20 have. Further, data converted into a digital amount by the current-only A/D converter 127 is stored in a digital 0 register 546, and data converted into a digital amount by the multiplexer-equipped A/D converter 124 is stored in a digital 1 register. 548
is maintained. However, digital 0 register 5
Since there is not enough time to process the current value of 46 by the CPU 114, the input/output circuit 1
Process within 20 seconds. Specifically, processing is performed to reduce the voltage applied to the motor. The digital data of the digital 0 register 546, which holds the digital amount obtained by A/D conversion of the current, is compared with the reference data of the reference register group 570, which holds the data equivalent to the current limit value. However, the A/D converter 127 operates independently of the stage signal (E) in FIG. Therefore, each process generates a stage signal E in a certain order, and a processing stage is provided for comparing the current value with this stage signal. This is a kind of stage interrupt function. The interrupt function to the stage is requested by the A/D conversion end signal (f) in FIG. 6, which is generated at the rising edge of _φ1 . At that time, the stage latch 674 does not hold the output signal of the stage decoder 672, but holds the A/D conversion end signal, and holds the digital data of the current value in the digital 0 register 546 and all current values. It is determined whether the current of the element has reached the limit value by comparing the current value with the reference data of the reference register group 570. At this time, the stage counter 670 does not count, and the stage _decoder 67
By holding the output signal No. 2 in the stage latch 674, the processing stages before the interrupt processing are performed, and each processing is subsequently performed in a certain fixed order. In addition, an A/D converter 124 with a multiplexer
The digital data converted by
The data is taken into the CPU 114 as data. The digital signal converted by the current-only A/D converter 540
Data is also taken into the CPU 114. The input/output circuit 120 includes a status register 550 that serves as an interrupt request signal to the CPU 114, and a mask register 552 that masks the interrupt request signal. Status register 55
0 holds the internal state of the motor and input/output circuit 120. The contents are shown in Table 1.

[Table] Figure 10 shows the status register 550, mask register 552, and interrupt controller 554.
shows. The status register 550 is the CPU 114
It serves as a read register for the CPU 114 in order to perform interrupt factor analysis. Further, the mask register 552 is a write register for designation from the CPU 114. The output signals of status register 550 and mask register 552 are AND-ornoted corresponding to each bit, and the output thereof becomes an interrupt request signal.
810 is a signal that causes an interrupt. Further, the registers for specifying the mode from the CPU 114 to the input/output circuit 120 include a mode 0 register 556, a mode 1 register 558, and a mode 2 register 560. The contents are shown in Table 2.

[Table] Mode 0 register 556, mode 1 register 558, mode 2 register 560 are all
It serves as a write register for specifying each mode from the CPU 114. The control signal generation circuit 591 generates a count signal, an increment/decrement function, and an increment/decrement function by an incrementer/decrementer controller 590 to control the increment/decrement function, non-increment/decrement function, and reset function, which are the functions of the incrementer/decrementer 578. Generates a decrement signal and a reset signal. The comparison controller 581 also controls the comparison circuit 58
This is for controlling the comparison result (≧,≦,=) of 0. The output controller 666 controls the maximum on time and minimum off time of the power element, and prevents lag between the P-side arm and the N-side arm, and protects and compensates the power element. Trigger counters 660 and 661 are counters for generating time for protection and compensation, trigger decoders 662 and 663 generate time for protection and compensation, and trigger latches 664 and 6
65 generates a trigger pulse. FIG. 11 shows a generation circuit for stage signal E.
When the clock signal φ ₁ from the non-overlap circuit 701 in FIG. 7 is 1, the stage counter 67
0 starts counting and its stage counter 67
0 outputs C ₀ to C ₉ and M ₂ of bit 2 of mode ₀ register 556 in FIG _.
Stage decoder 672 with T ₁ and T ₂ as input
added to. Stage decoder 672 generates signals O ₀ -O ₂₃ as outputs. This output signal
O ₀ to _{O 23} are input to a stage latch circuit 674, and the stage latch circuit 674 is set to "T" by clock signal φ ₂ =1 to hold the outputs O ₀ to O ₂₃ of the stage decoder 672. Further, the reset input R of the stage latch circuit 674 receives the M ₀ signal of bit ₀ of the mode 0 register 556 in FIG. The output becomes "0" (low level) and all processing operations are stopped. On the other hand, the mode 0 register 556
When the signal M ₀ of bit 0 becomes 1, stage signals are output in a certain order, and processing is performed based on this. The stage decoder 672 can be easily realized by using a read-only memory or the like, and can also be implemented using a micro-programming method. In addition, the interrupt function to the stage is
This is done by the latch 1102 of the stage latch circuit 674 which outputs CMT-P. First, all the latch groups 1104 other than the latch 1102 of the stage latch circuit 674 are reset with the A/D conversion end signal, and operations other than interrupt operations are stopped. and,
Latch 110 the A/D conversion end signal (FIG. 6 F)
2 and performs an interrupt operation. Incidentally, detailed processing contents of the stage signal which is the output of the stage latch circuit 674 are shown in Table 3.

【table】

【table】

[Table] Next, the stage signal and stage counter 67
0 and the outputs of registers 556 and 558 are shown in Table 4.

【table】

[Table] First, the general reset signal GR is input to the reset terminal of the stage counter 670 shown in FIG. 11, so that the counter outputs C ₀ to _{C 9} all become 0. This general reset signal GR is sent from the CPU 114 when this control circuit is activated.
In this state, the counter of the stage counter 670
C ₀ to C ₃ are 0, and when T ₀ of bit 0, T ₁ of bit 1, and T ₂ of bit 2 of the mode 1 register are all 0, when clock signal φ ₂ is input, φ ₂ At the rising edge of , the PWM8-P stage signal is output.
PWM8 processing is performed using this stage signal.
Next, the stage counter 670 counts by one when the clock signal φ ₁ =1, and furthermore, the next stage signal PN-P is outputted at the rising edge of the clock signal φ ₂ , and the processing of PN is performed by this stage signal. It will be done. In this way, the stage counter 67
When 0 continues to be counted with φ ₁ =1, a stage signal is output at the rising edge of φ ₂ and processing is performed in accordance with this signal. C ₀ to _{C 9} of stage counter 670 are all 1
Then, the stage signal PGN-P is output (however, when M ₂ = 0 in the mode 0 register),
PGN processing is performed, and all the processing in Table 4 is completed. When the next clock signal φ ₁ =1, all C ₀ to C ₉ of the stage counter 670 become 0, and if the output of the mode 1 register 558 is 0, the stage signal PWM8-P is output when the clock signal φ ₂ =1. is,
PWM processing is performed. In this way, the processing in Table 4 is repeated. Therefore, the system flow of the input/output circuit 120 is shown in FIG. The register group and stage counter 670 are all set to 0 by the general reset signal GR=0. When the general reset signal GR becomes 1, first bit 0 of the mode 0 register 556 specifies start/stop of the input/output circuit 120.
It is determined whether M ₀ is 1, and when M ₀ =0, the input/output circuit 120 is in a stopped state until M ₀ =1. With M ₀ = 1, stage counter 6
The output of 70 is 0, that is, the n=0th stage signal is generated. From here, the actual processing begins. First, when M ₀ =1, the nth stage signal is held in the stage latch circuit 674 and at the same time the following operation occurs. (i) The output signal of the first comparison output latch group 602 is held in the second comparison output latch group 604. (ii) The contents of the instantaneous register selected from the instantaneous register group 572 by the stage signal are held in the latch circuit 576. Next, it is determined whether the transfer signal MOVE is 0 or 1, and if MOVE=0, the stage counter 6
70 is counted, and the output of the latch circuit 576 is passed through an incrementer/decrementer 578.
The output is written to the selected instantaneous register and at the same time is compared with a reference register selected by the stage signal from the reference register group 570;
The comparison result is set in the first comparison output latch selected from the first comparison output latch group 602 by the stage signal. After that, A/D conversion end signal
Determine ADE. Also, the transfer signal MOVE=1
At the same time as the stage counter 670 counts, the contents of the instantaneous register are transferred from the output register group 574 to the output register selected by the stage signal, and all instantaneous registers are set to 0. Depending on whether the A/D conversion end signal ADE is 0 or 1, an interrupt to the stage is requested. ADE
When = 0, it returns to the original state and performs the next process, but when ADE = 1, mode 0 register 5
It is determined whether M ₃ of bit 3 of 56, that is, the interrupt mask bit to the stage, is 0 or 1, and when M ₃ =0, the process returns to the original state and performs the next process. When M ₃ =1, interrupt processing to the stage is performed. For this purpose, the A/D conversion end signal ADE is held in the stage latch circuit 674, and the stage signal CMT-P
, compares the contents of the digital 0 register with the contents of the current-related reference register of the reference register group 570, sets the comparison result in the first comparison output latch related to the current of the first comparison output latch group 602, and again The process before returning to the original stage and interrupting the stage will be performed thereafter. The flow at the upper right of FIG. 12 is the flow when M ₀ =0 in mode 0 register 556, and at the same time as the input/output circuit 120 stops operating, M ₀ =0.
It will wait until the activation command becomes 1. Next, a circuit diagram for synchronizing the contents and operations of external pulse signals PU, PV, and PW is shown in FIG. 13, and timing is shown in FIG. 14. Output of stage latch circuit 674 in FIG.
Using STAGE3-P and STAGE2-P, enable signal E and the above external pulse signals PU, PV, PW
A synchronized signal (Fig. 14) is generated. External pulse signal PU for motor phase detector, etc.
PV and PW are connected to the latch circuit 130 in Fig. 13 by a signal that is a combination of STAGE3-P and _φ2 in Fig. 11.
2, 1304, and 1306, respectively. In Fig. 14, B is the clock signal φ ₂ , C is the clock signal φ ₁ , ta is the external pulse signal PU, PV, PW,
Re and G are stage signals STAGE3-P, STAGE2
-P. This stage signal is generated in synchronization with φ ₂ =1, as explained in FIG. The external pulse signal T and the stage signals R and S have no relationship in terms of time. Now, as shown in FIG. 14, the external pulse signal is connected to the latch circuits 1302, 1304, 130 in FIG.
6, the stage signal
AND signal of STAGE3-P and clock signal _φ2
STAGE3-P and φ are _respectively latched. Therefore, latch circuits 1302, 1304,
The output signals PU1, PV1, and PW1 of 1306 are the 14th
The result will be as shown in Figure N. latch circuit 1308,
1310, 1312 are output signals PU1, PV1,
In order to latch PW1 with AND signals STAGE2-P and _φ2 of stage signal STAGE2-P and clock signal _φ2 , latch circuits 1308 and 131
The output signals PU2, PV2, and PW2 of 0 and 1312 are as shown in A of FIG. Exclusive OR circuit 1314, 1316, 1318
are the signals PU1 and PU2, the signals PV1 and PV2, respectively,
Signals PW1 and PW2 are input, external pulse signal
PU, PV, PW rising and falling detection signals
PUS, PVS, and PWS are generated (Fig. 13), and the pulse width becomes the stage signal STAGE3-P to STAGE2-P. According to the synchronization circuit 680 in FIG. 13, the rise and fall of the external pulse signal can be detected as pulses with a constant width, and this pulse width is determined by the stage signal.
It is determined by the time difference between STAGE3-P and STAGE2-P.
Therefore, latch circuits 1302, 1304, 1306
By changing the stage signals input to 1308, 1310, and 1312, the pulse width can be adjusted and changed. This pulse width is determined in relation to the stage signal assignments in Table 4. That is, in addition to STAGE2-P, which does not require an external pulse signal for processing, detection signals for rising and falling external pulses are established. This detection signal is the incrementer/decrementer controller 59.
The control signal becomes 0. Furthermore, the external pulse signals PU, PV, and PW of the synchronization circuit 680 shown in FIG. By inputting 60 to the 3-input OR circuit 1320 and inputting its output to the NOT circuit 1322,
You can get a pulse of 100 degrees. Furthermore, instead of using three inputs, the output of the pulse generator 152 can be input to any one of the external pulse signals PU, PV, and PW of this synchronization circuit 680 as shown in FIG. The number of rotations can be detected. In addition, synchronization is reliably applied to external pulse signals from phase detectors, etc., and synchronization pulses PUS, PVS,
In order to reliably generate PWS, it is necessary that the output from the phase detector etc. mentioned above has a pulse width of 8 μs or more (in this example, the enable signal E from the CPU 114 is 1 μs, and the stages shown in Table 4 are Signals PG-P and PULS-P are output every 8 μs). For example, if a pulse generator that outputs 500 pulses per revolution is input to the synchronization circuit 680 instead of a phase detector, the number of revolutions at which the pulse width is 8 μs is 7500 revolutions/minute. In order to follow higher rotational speeds, it is necessary to shorten this 8μs. Table 5 shows the detailed contents of the reference register group 570, which holds reference data corresponding to each pulse output that receives input data from an electric motor, etc., and is processed in the CPU 114. Further, its configuration diagram is shown in FIG. 15.

【table】

[Table] Table 6 shows the detailed contents of the instantaneous register group 572 that holds the instantaneous state of the electric motor etc. and has a counter function. Its configuration diagram is shown in FIG.

【table】

[Table] Table 7 shows detailed contents of the output register group 574 holding measured data. Its configuration diagram is shown in FIG.

【table】

[Table] First comparison output latch group 602 and second comparison output latch group 60 that hold the comparison output of comparison circuit 580
The detailed contents of 4 are shown in Table 8, and its configuration diagram is shown in FIG.

【table】

【table】

[Table] FIG. 19 is a diagram illustrating the generation of a pulse width modulation signal that is the gate signal of the inverter of the motor with a phase detector (non-commutator motor) shown in FIG. The carrier wave PWM of the pulse width modulation signal is generated by processing the stage signal PWM-P. The carrier wave is PWMT REG732 of instantaneous register group 572
and P0 REG 702 of the reference register group 570,
Made by P1 REG704. stage signal
During PWM-P processing, the PWMT REG 732 is unconditionally incremented or decremented by the incrementer/decrementer 578. Also, the output signal of the phase detector 150 is
PU, PV, and PW are input as external pulse signals to the input/output circuit 120, and the synchronized external pulse signal PS indicating their rise and fall is "1".
At this time, PWMT REG 732 is reset. Increment and decrement control is performed by the second
P0 BE910 and P1BF of comparison output latch group 604
912. DEC/INC of the output of the flip-flop (not shown) which is reset when P0 BF=1 and set when P1 BF=1 is “0”
When , PWMT REG732 is incremented, and when DEC/INC is “1”, PWMT REG732 is incremented.
REG732 is decremented. Also, when decremented, P0 REG7
02 and the retained data of P0 REG702 is
When the held data of PWMT REG 732 or more satisfies the condition, P0 of the first comparison output latch group 602
Latch “1” to FF754. Furthermore, the second
P0 BE910 of comparison output latch 604 is P0 FF
The output of P0 BF910 becomes "1". When incremented, P1 REG704
The retained data of P1 REG704 is compared with
When the following conditions are satisfied for the held data of PWMT REG732, P1 of the first comparison output latch group 602
Latch “1” to FF756. Furthermore, P1 BF912 of the second comparison output latch group 604 is P1 FF.
The output of P1 BF912 becomes "1". PWMT as shown in Figure 19
The data held in REG 732 changes over time. Next, the PN-P process of counting the number of pulses of the pulse modulation signal is performed by the instantaneous register group 572.
PNC REG734 is incremented when P0 BE910 is “1”, and when the synchronized external pulse signal PS is “1”, the data held in PNC REG734 is incremented by CPN REG7 of output register group 574.
52 (Fig. 19A), written, and PNC
REG 734 is reset. Therefore CPU11
4 can read the number of pulses. When processing stage signal OP-P, PWMT
REG732 is unconditionally non-incremented,
It is compared with D2 REG708 of the reference register group 570, and the data held in D2 REG708 is PWMT
When the following conditions are satisfied for the held data of REG732, the UP FF7 of the first comparison output latch group 574
60, VP FF762, WP FF764, UN FF
766, VN FF768, WN FF770 as the second
0, and latches "1" in the first comparison output latch group 602. Furthermore, UP BF916 and VP BF of the second comparison output latch group 604
918, WP BF920, UN BF922, VN
BF924, WN BF926 are each UP FF7
60, VP FF762, WP FF764, UN FF
766, VN FF768, and WN FF770 outputs are latched. Also, when processing the stage signal DP-P,
PWMT REG732 is unconditionally non-incremented, and D1 REG70 of the reference register group 570
6 and the retained data of D1 REG706 is
When the conditions equal to or higher than the data held in PWMT REG 732 are satisfied, the first comparison output latch group 574
UP FF760, VP FF762, WP FF764,
UN FF766, VN FF768, WN FF770
is selected by the selection circuit shown in FIG. 20, and "1" is latched in the first comparison output latch group 602. Second
Comparison output latch group 604 UP BF916, VP
BF918, WP BF920, UN BF922,
VN BF924 and WN BF926 are each UP
FF760, VP FF762, WP FF764, UN
Latch the outputs of FF766, VN FF768, and WN FF770. UP BF916, VP BF918, WP BF92
0, UN BF922, VN BF924, WN BF
The output signal of 926 becomes the pulse width modulation signal of the arm. FIG. 20 shows a selection circuit for the first comparison output latch group 602 necessary for processing the stage signals OP-P and DP-P using signals PU1, PV1, and PW1 that are synchronized with the phase detection signals shown in FIG. show. Table 9 is a selection table for the first comparison output latch group 602 according to the phase modes of PU1, PV1, and PW1.

[Table] Figure 20 shows the signal obtained by latching the phase detection signal, which is an external pulse signal, with STAGE3-P・φ ₂ =1.
Using PU1, PV1, and PW1 as input, the phase signals PHASE0, PHASE1, and
PHASE2, PHASE3, PHASE4, PHASE5,
PHASE6 and PHASE7 are generated via a phase decoder 302 and a phase latch circuit 304. The latch selected in the first comparison output latch group is selected for each process of OP-P and DP-P as shown in Table 9 in accordance with the phase signal. Here, PHASE0, PHASE7
This state indicates a failure of the phase detector 150 and is an impossible state. PHASE0, like this
In PHASE7, all arms are blocked and protected.
FIG. 20 has a failure diagnosis function for the phase detector 150. Also, PHASE0,
In PHASE7, "1" is written to S4 of bit ₄ of the status register 550, which serves as an interrupt request signal to the CPU 114, making it possible to protect the power element. FIG. 21 is a diagram illustrating the generation of a pulse modulation signal PWM, which is a gate signal of an inverter of unequal pulses in a motor (induction motor) without a phase detector as shown in FIG. The carrier wave PWM of the pulse width modulation signal is generated by processing the stage signal PWM-P. The carrier wave PWM is the PWMT of the instantaneous register group 572,
REG732 and P0 REG of reference register group 570
702, made by P1 REG704. When processing stage signal PWM-P, PWMT REG
732 is unconditionally incremented or decremented by incrementer/decrementer 578. Increment and decrement control is performed by P0 BF9 of the second comparison output latch group 604.
10 and P1 BF912. P0BF
DEC/ of the output of the flip-flop (not shown) which is reset when = 1, P1 BF = 1
When INC is “0”, PWMT REG732 is incremented, and when DEC/INC is “1”,
PWMT REG 732 is decremented. Also, when decremented, P0 REG7
02 and the retained data of P0 REG702 is
When the conditions equal to or higher than the data held in PWMT REG 732 are satisfied, P0 of the first comparison output latch group 602 is
Latch “1” to FF754. Furthermore, the second
P0 of comparison output latch group 604 BF910 is P0
The output of FF754 is latched, and the output of P0 BF910 becomes "1". When incremented, P1 REG704
The retained data of P1 REG704 is compared with
PWMT REG held data When the following conditions are satisfied, P1 FF7 of the first comparison output latch group 602
Latch "1" to 56. Furthermore, P1 BF912 of the second comparison output latch group 604 is P1 FF75.
The output of P1 BF912 becomes "1". PWMT as shown in Figure 21
The data held in REG 732 changes over time. Next, bit 4 of mode 0 register 556
Control of the number of unequal pulses when M ₄ is set to "1" will be explained. PN that counts the number of pulses in a pulse modulation signal
-P processing is the PNC of the instantaneous register group 572.
REG734 is incremented when P0 BF910 is “1”, and PN of reference register group 570
REG720, and if the held data of PN REG720 satisfies the condition below the held data of PNC REG734, the first comparison output latch group 574
Latch “1” to PN FF758. moreover,
PN BF912 of the second comparison output latch group 604 is
Latch the output of PN FF758 and PN BF912
The output of is "1". Also, PNC REG734
is reset when the output of PN BF912 is "1". The number of pulses is controlled by this PN BF912. FIG. 22 shows the phase detection signal of the phase detector 150.
A phase generation circuit 306 of PU1, PV1, and PW1 corresponding to PU, PV, and PW is shown. The phase generation circuit 306 is a three-stage shift register, and when PN BF=1,
It is shifted step by step, and the shift state is shown in Table 10. There are 6 phase modes, PHASE1,
PHASE2, PHASE3, PHASE4, PHASE5,
It is PHASE6.

[Table] Next, the pulse width modulation signals of each arm of the unequal pulse are the stage signals UTM-P, VTM-P, WTM.
- This is done by processing P. During UTM-P processing, PWMT REG732 is unconditionally non-incremented, and the reference register group 5 in FIG.
70 selection circuit reference register selection latch 312
Register (D1) related to the modulated wave selected by
REG706, D2 REG708, D3 REG710,
D4 REG712, D5 REG714, D6 REG71
6, compared with the retained data of D7 REG718),
The comparison result is shown in the comparison result selection latch 3 in Figure 23.
Comparison output selected by 10 (reference register ≦
Instantaneous register, reference register ≧ instantaneous register, phase signal) to the UP of the first comparison output latch group 602
At the same time as latching to FF 760, the inverted signal of the comparison output is applied to UN of the first comparison output latch group 602.
FF766 is latched, and UP BF916 and UN BF922 of the second comparison output latch group 604 are latched.
UP FF760 and UN FF766 outputs are latched respectively. In addition, the stage signal VTM-P,
WTM-P processing operates similarly. FIG. 23 shows a pulse width modulation control circuit.
P0 BF910 output is counted as “1” and PN
The outputs SC ₀ , SC ₁ , SC ₂ , of the PN stage counter 314 are reset when the output of the BF 914 is “1”.
A pulse width modulation decoder 308 that receives SC ₃ and phase signals PU1, PV1, and PW1 selects a reference register of the reference register group 570 and selects a comparison result. Stage signal UTM-P,
Reference register selection latch 312 and comparison result selection latch 31 latched by VTM-P and WTM-P
By 0, the reference register selection signal shown in Table 11
D1 REG SEL，D2 REG SEL，D3 REG SEL，
D4 REG SEL，D5 REG SEL，D6 REG SEL，
D7 REG SEL and comparison result selection signals GE SEL (data held in the reference register ≦ data held in the instantaneous register), LE SEL (data held in the reference register ≧ data held in the instantaneous register), and PHASE SEL (phase signal) are generated.

【table】

【table】

[Table] As a result, UP BF916, VP shown in Figure 21
BF918, WP BF920 UN BF922,
VN BF924 and WN BF926 signals are created,
A gate signal is provided to each arm. 15 shown in Figure 21
A pulse width modulated signal of unequal pulses can be generated. In addition, the nine unequal pulses and the three unequal pulses are also input to the PN REG of the reference register group 570.
This is possible by changing the data of 720 from the CPU 114, and it is preferable to change it according to the frequency of the inverter. Furthermore, for equal pulses, by setting M4 of bit ₄ of mode 0 register 556 to “0”, D1 REG 706 of reference register 570 is set to “0”.
This is possible by selecting only . Also, bit 6 of mode 0 register 556
Setting M ₆ to “0” generates a pulse width modulation signal for the motor with phase detector (non-commutator motor) shown in Figure 19, and setting M ₆ to “1” generates the unequal pulse width modulation signal for the induction motor shown in Figure 21. This results in the generation of a pulse width modulated signal. FIG. 24 is a diagram illustrating the generation of the chopper signal CH. The chopper signal CH performs duty control. The reference register group 570 includes a CHP REG 724 that holds synchronous data as shown in FIG.
and CHD REG72 that holds on-time data
There are 6. Also, as a timer, instantaneous register group 5
Made by CHT REG740 of 72. When processing stage signal CHP-P, CHT
REG740 is unconditionally incremented and also compared with CHP REG724, and CHP REG72
When the held data of No. 4 satisfies the following conditions below the held data of CHT REG 740, “1” is latched in CHP FF 774 of first comparison output latch group 602. Furthermore, the second comparison output latch group 604
CHP BF930 latches the output of CHP FF774, and the output of CHP BF930 becomes "1". When processing stage signal CHD-P, CHT
REG740 is unconditionally non-incremented. Also, the output of CHP BF930 is “1”.
CHT REG 740 is reset. In this process, the data held in CHD REG726 is
When the following conditions are satisfied for the held data of REG740, CHD FF of the first comparison output latch group 602
CHD BF 932 of the second comparison output latch group 604 latches the output of CHD FF 776, and the output of CHD BF 932 becomes "1". The inverted output of this CHD BF932 is the chopper signal CH. Figure 25 shows the synchronized external pulse signal PS
There are two processes to measure the pulse time width: PG process,
FIG. 7 is a diagram illustrating the state of PGN processing when M ₂ =0 in the mode 0 register 556. The measurement method is a synchronized external pulse signal PS
Measurement starts when =1. The time width to be measured is determined by PG REG 738 of instantaneous register group 572. PG REG738 is the PGT REG73 of the instantaneous register group 572 when processing the stage signal PG-P.
8 is unconditionally incremented. However, if the pulse time width of the synchronized external pulse signal PS becomes longer, the PGT REG 738 will overflow (point B in FIG. 25). Therefore, P.G.T.
There is a stage signal PGM-P process that counts the number of overflows of REG738. Additionally, the data held in PGT REG738 is compared with the data held in P0 REG702 of the reference register group 570 (usually all 0), and the data held in P0 REG702 of the reference register group 570 is compared
When the held data of 02 satisfies the condition greater than or equal to the held data of PGT REG 738, “1” is latched in PG FF 780 of first comparison output latch group 602. Furthermore, the PG of the second comparison output latch group 604
BF936 latches the output of PG FF780,
The output of PG BF780 becomes “1” and PGT
It can be seen that REG738 has overflowed.
In addition, the processing of the stage signal PGN-P that counts the number of overflows is
Under the condition that BF is “1”, instantaneous register group 57
PGNC REG 740 of 2 is incremented. With the synchronized external pulse signal PS=1,
By processing stage signal PG-P, PGT REG73
PG of the register group 574 outputs the retained data of 8.
Transfer to REG748 (Figure 25C) and write PG
REG 738 is reset. In addition, by processing the stage signal PGN-P, data held in PGNC REG 740 is output to PGN REG of output register group 574.
Transfer to 750 (Fig. 25D), write, PGNC
REG 740 is reset. PG REG748 of output register group 574 and
It is possible to measure the pulse time width of the external pulse signal PS synchronized with the data held by each PGN REG750. FIG. 26 shows M=1 in mode 0 register 556.
FIG. 3 is a diagram illustrating a method and process for counting synchronized external pulse signals PS within a certain time width in the state of FIG. of the instantaneous register group 572 that measures the time width.
PULSWT REG736 is a stage signal
It is unconditionally incremented by PULSW-P, and PLUSW BF of the second comparison output latch group 604
It is reset when 928 is "1". In addition, the data held in PULSW REG722 of the reference register group 570 and the PULSWT of the instantaneous register group 572
Compared with the retained data of REG736,
The data held in PULSWREG722 is PULSWT
When the following conditions are satisfied for the held data of REG736, RULSW of the first comparison output latch group 602
Latch “1” to FF772. Furthermore, the second
PULSW BF928 of comparison output latch group 604 is
Latch the output of PULSW FF772, and
The output of BF928 becomes "1" and a certain time width can be obtained. PULSWD showing the rise of PULSW BF928
= 1, the data held in PULSC REG738 of instantaneous register group 572, which counted the external pulse signal PS synchronized by the processing of stage signal PULS-P, is output to PULS REG74 of register group 574.
8 (Fig. 26E) and write. Also,
When PULSW BF928 is “1”,
PULSCREG 738 is reset and a count of synchronized external pulse signals PS within a certain time span is obtained. The PG-P, PGN-P processing in Figure 25 and the PULS-P processing in Figure 26 both indicate the rotational speed of the motor, and the PG-P, PGN-P processing has good accuracy at low speeds.
PULS-P processing has good accuracy at high speed.
Mode 0 in Table 2 written by CPU114
Switched by register _M2 . Figure 27 shows a stage signal that operates as a timer and requests an interrupt to the CPU 114 at certain intervals.
It is a figure explaining the processing of INTV-P. of the instantaneous register group 572 that measures the time width.
INTVT REG742 is the stage signal INTV-
It is unconditionally incremented by the processing of P, and is reset when INTV BF934 of the second comparison output latch group 604 is "1". Also, the data held in INTV REG728 of the reference register group 570 is compared with INTVT-REG744 of the instantaneous register group 572, and the data held in INTV REG728 is
Data held in INTVT REG 744 When the following conditions are satisfied, the first comparison output latch group 602
Latch “1” to INTV FF778. Furthermore, INTV BF9 of the second comparison output latch group 604
34 latches the output of INTV FF778,
The output of INTV BF934 becomes "1". INTVD indicating the rise of this INTV BF934
By writing 1 to S5 of bit ₅ of the stator register 550 when S5=1, it becomes an interrupt request signal to the CPU 114. FIG. 28 is a diagram illustrating an interrupt to a stage for current limitation. The stage signal CMT-P is not processed after a certain period of time, but by the current-only A/D converter 546.
This is generated by the A/D conversion end signal ADE=1. Stage signal CMT-P is processed by current-only A/
The DGTLO REG 546 holding the A/D converted digital data of the D converter 546 is compared with the data held in the CMT REG 730 of the reference register group 570, and the condition that the data held in the CMT REG 730 ≦ the data held in the DGTLO REG 546 is satisfied. When the first comparison output latch group 602
Latch “1” to CMT FF782. Furthermore, CMT BF9 of the second comparison output latch group 604
37 latches the output of CMT FF782 and
The output of BF937 becomes "1". CMTD= which shows the rise of this CMT BF937
Writing 1 to bit 3 _S3 of the status register 550 becomes an interrupt request signal to the CPU 114. Also, when CMTD=1, the output pulse is turned off. FIG. 29 shows trigger pulse signals TRG0-P and TRG1- for controlling the output controller 666.
FIG. 2 is a detailed circuit diagram for generating P. This trigger pulse signal TRG0-P and TRG1P
is used to protect the power elements of each arm of the inverter. The output controller 666 has a protection function of compensating for the minimum on time and minimum off time of the power devices, and preventing overlap between the power devices of the P side arm and the power device of the N side arm of the inverter. Triggered by stage signal STAGE3-P・φ ₁ = 1
0. Counter 660 is counted and its output is
Trigger 0 inputs R ₀₀ , R ₀₁ , R ₀₂ , R ₀₃ , R ₀₄ and C ₀ , C ₁ , C ₂ of mode 2 register 560. Output signals TGG0-8, TRG0 are generated by decoder 662.
−16, TRG0−32, TRG0−64, and TRG0−128 are produced. The contents of trigger 0 decoder 662 are
Shown in Table 12. Output signal TRG0-8, TRG0-16,
TRG0-20, TRG0-64, and TRG0-128 are passed through a 5-input NOR circuit 412, and a latch circuit 664 that becomes "T" when φ ₂ =1 latches the output of the NOR circuit 412, and the clock signal φ ₂ and latch circuit 66
The output of the 2-input NOR circuit 420 which receives the output of 4 becomes TRG0-P.

【table】

[Table] TRG1-P is also output by trigger 1 decoder 663 as shown in Table 13.
This is the same operation as TRG0-P. Also, TRG0-8, TRG1-8 every 8μs,
TRG0−16, TRG1−16 every 16 μs, TRG1−32,
TRG1-32 is every 32μs, TRG0-64, TRG1-64 is
Every 64μs, TRG0-128, TRG1-128 are pulses that are generated every 128μs, but in order to generate finer pulses, TRG0-P, TRG1 are added to the stage signal.
It is also possible to provide -P. This time span becomes the time for compensation and protection. FIG. 30 is a detailed circuit diagram of the output controller 666, and FIG. 31 is its timing diagram. Two of the pulse width modulated signals of the second comparison output latch group 604, UP BF 916 and UN BF 922, will be described. The output signal of the UP BF916 is input to the latch circuit 430 which becomes "Through" when the trigger 0 and the pulse signal TRG0-P=1. The output signal UPS1 of the latch circuit 430 has a waveform as shown in FIG. Since it is shorter than the pulse width of TRG0-P of α of the UP BF916 output signal,
It does not appear as a pulse on UPS1. Here, compensation for the minimum on-time of the power element can be performed. The output signal of UN BF 922 is the input to latch circuit 432, which operates in the same manner as latch circuit 430. The output signal of the latch circuit 432
UNS1 also has a waveform as shown in FIG. 13.
Similar to UPS1, this UNS1 also does not have a pulse corresponding to α. Here, compensation for the minimum on-time of the power element can be performed. Furthermore, trigger 1/pulse signal TRG1-P=1
The input to the latch circuit 442 which becomes "T" is the output signal UPS1 of the latch circuit 430, and its output signal becomes UPS2. The output signal of the AND circuit 466 which receives UPS1 and UPS2 as input is U.
In addition, the input of the latch circuit 444 that becomes “T” when the trigger 1/pulse signal TRG1-P=1 is as follows.
This is the output signal UNS1 of the latch circuit 432, and becomes its output signal UNS2. The output signal of the AND circuit 468 inputting UNS1 and UNS2 is U ^- . U ^+, which is the gate signal for the P side arm of the inverter, and U ^- , which is the gate signal for the N side arm, have a non-overlap of time τ _Lag as shown in Figure 31, and the off signal of U ^- is input. , when the time τ _Lag has passed, the power element of the N-side arm is completely off, so an on signal is generated at U ⁺ , turning on the power element of the P-side arm. Also, VP BF918 of the second comparison output latch group
The relationship between and VN BP924, and WP BF920
The relationship with WN BF926 is UP BF916 and UN
It's the same with my relationship with BF. Furthermore, the relationship between the output of CHD BF932 and the signal CHOP is UP.The output of BF918 and the latch circuit 430
Same as the relationship with the output signal UPS1, it is possible to compensate for the minimum on time and minimum off time. Selectors 458, 460, 46 in Figure 30
2,464 is controlled by bit 7 of mode 0 register 556, _M7 . When M ₇ = 0
U ⁺ and U ^- have the outputs of UP BF916 and UN BF922, and W ⁺ and W ^- have the outputs of WP BF920 and WN BF.
The output of 926 is involved, and the motor rotates in the normal direction. However, when M ₇ = 1, for U ⁺ and U ^- , WP BF92
0 and WN The output of BF926 is W ⁺ , W ^- ,
The outputs of UP BF916 and UN BF922 are related,
The electric motor is reversed. In this way, the gate signals U ⁺ , U ^- , V ⁺ , V ^- , W ⁺ , W ^- of the pulse width modulation of the output pulse signal and the chopper signal CHOP are completely compensated and protected before being applied to the gate driver. 130. Next, a method for setting reference data in the reference register group 570 will be explained. For example, in order to generate the pulse width modulation signal shown in Fig. 4, the speed command S _P is A/D converted and the CPU
Based on the data, the effective voltage applied to the motor 152 and the number of unequal pulses are obtained by calculation processing or from information stored in a map form with respect to the frequency from the speed command _SP . Set data in P0 REG702 and P1 REG704 for the frequency, and also set the number of pulses.
PN REG720 and the modulation wave that determines the effective voltage.
D1-D7 Set data in REGs 706-718. Once these data are set, the pulse width modulated signal of FIG. 4 is generated. Further, when changing the effective voltage to the motor 152, the CPU performs calculation processing and sets the data of D1 to D7 REGs 706 to 718, thereby generating a pulse width modulation signal. As shown in FIG. 24, the chopper signal CHOP outputs cycle and on-time data obtained from calculation processing in the CPU 114 or based on map-like information according to the state of the motor, respectively, to CHP REG.
724 and CHD REG 726, a signal is generated to control the energization time of the power element. FIG. 25 and FIG. 26 show the measurement of the rotational speed. Figure 25 shows the case where the motor is running at a low speed, and the time width of the external pulse signal is measured, and the output register group is
Data is held in PG REG 748 and PGN REG 750 and taken into CPU 114. Time width T T = (PGN REG750 retention data) × 2048 μs + (PG REG
748 held data) x 8 μs, and the number of rotations can be measured. In FIG. 26, the number of external pulses within a certain time width is counted, the data is held in the PULS REG 748, and is taken into the CPU 114. Further, the time width is determined by setting data to the PULSW REG 722. A timer interrupt request from the CPU 114 is used when a timer is required in program creation, and an interrupt request is generated by setting data of the necessary time in INTV REG 728. Current limiting is performed by interrupting the stage and by setting limit value data in CMT REG 730. Further, an interrupt to the stage occurs after the A/D conversion is completed. According to the present invention, accurate detection is possible because the external pulse signal that is input irregularly is synchronized with the stage signal. Furthermore, in the embodiment described above, the detection stage can be shortened depending on the accuracy of the stage order, and since a synchronization signal is included in each process, accurate detection is possible even when the motor rotates at high speed. As explained above, the present invention provides a speed command means for giving a speed command to an electric motor, a plurality of detection means for detecting the speed of the electric motor or the position of the rotor, and digital control of the output signals of these plurality of detection means. A digital arithmetic circuit that performs arithmetic processing as a quantity,
A pulse input/output circuit that converts the output of the digital arithmetic circuit into a predetermined pulse output, and a control means for controlling a plurality of digital control amounts of the electric motor based on the output of the pulse input/output circuit, a group of reference registers for holding the output of the digital arithmetic circuit, a group of instantaneous registers for holding the detection signals of the plurality of detection means, a group of output registers for sampling the output of the group of instantaneous registers, and a group of the reference registers. a comparison circuit for comparing data held in each register selected from the group and the instantaneous register group, and a comparison output latch circuit for holding the comparison result by the comparison circuit;
An incrementer/decrementer for adding +1, -1, or clearing the data of an instantaneous register selected from the instantaneous register group, returning it to the instantaneous register again, and updating the data of this instantaneous register, and time-sharing control of each process. The stage counter is controlled by predetermined first and second clock signals.
The counting operation of the stage counter is started by the second clock signal, and the stage signal is held in the stage latch circuit in synchronization with the second clock signal. The effective time width for pulse processing can be expanded, and processing speed can be increased by using a high frequency clock signal.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a control device for a motor with a phase detector (non-commutator motor), which is an embodiment of the present invention, and FIG. 2 is a diagram illustrating pulse width modulated waves of each phase in FIG. 1. , Fig. 3 is a circuit configuration diagram of a control device for a motor without a phase detector (induction motor), and Fig. 4 is a circuit diagram of a control device for a motor without a phase detector (induction motor).
Figure 5 is a detailed circuit diagram of the input/output circuit; Figure 6 is a timing diagram of the input/output circuit; Figure 7 is a non-overlap circuit diagram; The figure is a block diagram of the data bus.
Figure 9 is a block diagram of the address bus.
Figure 0 is an explanatory diagram of the status register and mask register, Figure 11 is a stage signal generation circuit diagram,
Figure 12 is a system flow diagram of the input/output circuit, Figure 13 is an external pulse synchronization circuit diagram, Figure 14 is a timing diagram of Figure 13, Figure 15 is a detailed register configuration diagram of the reference register group, and Figure 15 is a detailed register configuration diagram of the reference register group. Figure 16 is a detailed register configuration diagram of the instantaneous register group, Figure 17 is a detailed register configuration diagram of the output register group, and Figure 18 is the detailed register configuration diagram of the output register group.
and a latch configuration diagram of the second comparison output latch group, FIG. 19 is a timing diagram of the generation process of the pulse width modulation signal in FIG. 2, and FIG. 20 is a selection circuit diagram of the first comparison output latch group in FIG. Figure 21 is a timing diagram of the generation process of the unequal pulse width modulation signal in Figure 4, Figure 22 is a phase generation circuit diagram, Figure 23 is a pulse width modulation control circuit diagram, and Figure 24 is a timing diagram of the chopper signal generation process. , FIG. 25 is a timing diagram of pulse time width measurement processing of an external pulse signal, and FIG.
The figure is a timing diagram for counting pulses within a certain time width, Figure 27 is a timing diagram for timer interrupt generation processing, Figure 28 is a processing timing diagram for current limiting, and Figure 29 is a signal generation circuit diagram for the output controller. , Figure 30 is a detailed circuit diagram of the output controller,
FIG. 31 is a timing diagram of FIG. 30. 100...Motor with phase detector (non-commutator motor), 102...Motor without phase detector (induction motor), 104...Temperature sensor, 114...
CPU, 116...RAM, 118...ROM, 1
20... Input/output circuit, 122... Multiplexer, 123... Interface circuit, 124,
127...Analog-digital conversion circuit, 12
5...Discrete input/output circuit, 126...Pulse output circuit, 128...Pulse input circuit, 13
0...Gate driver, 131-134...
Amplifier, 135... Smoothing capacitor, 136...
Shunt resistance, 137, 138...Voltage division resistance, 1
50... Phase detector, 152... Pulse generator, 160... Inverter, 162... Data bus, 164... Address bus, 166...
...Control bus, 175... Rectifier circuit, 17
6 to 179...Diode, 181...Resistance, 1
85...power supply, 186-191...thyristor,
192-197... Diode, 198... Thyristor, 302... Phase decoder, 304... Phase latch circuit, 306... Phase generation circuit, 308
...Pulse width modulation decoder, 310...Comparison result selection latch, 312...Reference register selection latch, 314...PN stage counter, 41
2,414...NOR circuit, 420,422...
NOR circuit, 430, 432, 434, 436,
438, 440, 442, 444, 446, 44
8,450,452,454...Ratsuchi, 456
...NOT gate, 458, 460, 462, 4
64...AND-OR gate, 466,468,4
70,472,474,476...AND circuit,
500... Incrementer/decrementer control bus, 540, 542... Analog-to-digital conversion circuit, 544... Multiplexer, 546, 548... Digital register,
550...Status register, 552...Mask register, 554...Interrupt controller, 556...Mode 0 register, 558...
Mode 1 register, 560...Mode 2 register, 570...Reference register group, 572...Momentary register group, 574...Output register group, 57
6...Latch circuit, 578...Incrementer/
Decrementer, 580... Comparison circuit, 581...
Comparison result controller, 590... Incrementer/decrementer controller, 591... Controller generation circuit, 602... First comparison output latch group, 604... Second comparison output latch group, 66
0,661...Trigger counter, 662,66
3...Trigger decoder, 664, 665...Latch, 666...Output controller, 670...
Stage counter, 672... Stage decoder, 674... Stage latch circuit, 680
... Synchronization circuit, 701 ... Non-overlap circuit, 702, 704, 706, 708, 71
0,712,714,716,718,720,
722, 724, 726, 728, 730, 73
2,734,736,738,740,742,
744, 748, 750, 752... register,
754, 756, 758, 760, 762, 76
4,766,768,770,772,774,
776,778,780,782...Ratsuchi, 8
02...Data latch, 804...Tri-state buffer, 806...Write bus, 80
8... Read bus, 810... Interrupt factor signal,
902... Address latch circuit, 904... Address selector, 906... Address decoder, 910, 912, 914, 916, 91
8,920,922,924,926,928,
930, 932, 934, 936, 938... Latch, 1102, 1104... Latch circuit, 13
02,1304,1306,1308,131
0,1312...Latch, 1314,1316,
1318...EXCLUSIVE OR circuit, 1320
...NOR circuit, 1322...NOT circuit.

Claims (1)

[Claims] 1. A speed command means for giving a speed command to the electric motor, a plurality of detection means for detecting the speed of the motor or the position of the rotor, and output signals of these plurality of detection means as digital control variables. A digital arithmetic circuit that performs arithmetic processing, a pulse input/output circuit that converts the output of the digital arithmetic circuit into a predetermined pulse output, and control for controlling a plurality of digital control amounts of the electric motor based on the output of the pulse input/output circuit. A reference register group for holding the output of the digital arithmetic circuit, an instantaneous register group for holding the detection signals of the plurality of detection means, and an output for sampling the output of the instantaneous register group. a comparison circuit for comparing the data held in each register selected from the reference register group and the instantaneous register group with the register group; a comparison output latch circuit for holding the comparison result by the comparison circuit; and the instantaneous register group. An incrementer/decrementer for adding +1, -1 or clearing the data of the instantaneous register selected from the above, returning it to the instantaneous register again, and updating the data of this instantaneous register, and a stage for time-division control of each process. The stage counter is controlled by predetermined first and second clock signals, and the counting operation of the stage counter is started by the first clock signal and in synchronization with the second clock signal. A control device for an electric motor, characterized in that the stage latch circuit is configured to hold a stage signal.