JPS6346678B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an electric motor control apparatus, and more particularly to an electric motor control apparatus for digitally controlling an inverter-driven electric motor using a digital arithmetic circuit. In recent years, demand for variable speed motors has been increasing as electric motors or devices incorporating electric motors have become more sophisticated, and various attempts have been made to improve the control accuracy of these motors. One method is to use an inverter that employs a power element with a high switching speed in the power supply circuit for controlling the speed of the motor, and to control the input of the motor by pulse width modulation or chopper control. In controlling such a variable speed electric motor, a control circuit is generally configured for each control target. In addition, recently, devices that use microcomputers to control devices have been announced in order to improve the functionality of control devices.When configuring a control device using this microcomputer, it is possible to control many control objects at once. Therefore, when using a microcomputer to control an electric motor, for example, it is desirable to comprehensively control each control object. However, when many control objects are controlled by a control device having a pulse input/output processing circuit, if the counter function malfunctions, there is a problem in that the controllability of the various motor operations associated with this is impaired. . The present invention has focused on such problems, and its purpose is to prevent malfunction of the counter function,
An object of the present invention is to provide a control device for an electric motor that does not impair controllability. The present invention uses input information representing the operating state of the electric motor, digitally processes this input information, and uses a plurality of registers so that the processed data can be held according to each processing content. Each of these registers includes a register that not only holds data obtained by performing arithmetic processing but also holds data representing a predetermined value. What the data held in these registers have in common is that these data are used as reference values for comparison operations.
Therefore, these registers will hereinafter be referred to as a reference register group, and the data held within this reference register group will be referred to as reference data. Furthermore, it is equipped with a plurality of registers that hold data representing the instantaneous state of the motor, and these registers will hereinafter be simply referred to as the instantaneous register group, and the data held in this instantaneous register group will be referred to as instantaneous data. do. In the present invention, a reference register group, an instantaneous register group, an incrementer/decrementer for increasing or decreasing data by 1 or setting data to 0, and an incrementer/decrementer for controlling this incrementer/decrementer - Equipped with a controller, a comparison circuit, a holding circuit for holding the output of the comparison circuit, and a stage counter. Then, each stage is processed over time in a predetermined order by the stage counter, and in each stage, in order to perform the work determined at that stage, the reference register group and the instantaneous register group are processed. A predetermined register is selected from each register, reference data and instantaneous data are sent from each register to a comparison circuit, and the comparison result is held by a holding circuit. That is, the present invention provides a speed command means for giving a speed command to an electric motor, a plurality of detection means for detecting the speed of the motor or the position of a rotor, and arithmetic processing of the output signals of these plurality of detection means as digital control variables. a digital arithmetic circuit that converts the output of the digital arithmetic circuit into a predetermined pulse output; and a control means that controls a plurality of digital control variables of the electric motor based on the output of the pulse input/output circuit. In what you have prepared,
a reference register group for holding the output of the digital arithmetic circuit; an instantaneous register group for holding the detection signals of the plurality of detection means; an output register group for sampling the output of the instantaneous register group; and the reference register. a comparison circuit that compares the data held in each register selected from the group and the instantaneous register group, a group of comparison output latches that holds the output of the comparison circuit, and a stage counter for time-division control of each process; The data held in the instantaneous register group is selected by a stage signal of a stage counter, and the selected held data is held in the instantaneous register again via an incrementer/decrementer, and firstly, the comparison The output latch group includes a first comparison output latch group and a second comparison output latch group that holds the output of the first comparison output latch group, and outputs the output signal of the second comparison output latch group to the electric motor. The control signal is output as a control signal for the incrementer/decrementer controller, and the output signal of one of the second comparison latch groups selected according to the stage signal of each stage is applied to the incrementer/decrementer controller. Second, a data latch circuit for holding instantaneous data of the instantaneous register group is provided between the instantaneous register group and the incrementer/decrementer. . Furthermore, at each stage, the instantaneous data held in the instantaneous register related to that stage is rewritten in accordance with the actual instantaneous state of the motor, etc. This rewriting operation is performed by an incrementer/decrementer and an incrementer/decrementer controller. In other words, data representing instantaneous time or data representing instantaneous rotation angle of phase angle rotation should be increased depending on the generation state of the time signal representing the standard unit of time or the phase angle signal representing the rotation angle unit of the motor shaft. The incrementer/decrementer controller determines whether the value should be decreased. Based on this judgment result, the incrementer/decrementer specifically increases or decreases the instantaneous data. In this way, the instantaneous data is rewritten with new values from time to time, and a comparison operation is performed using this data. Through this comparison, a pulse output commensurate with the reference data can be generated. By adopting such a configuration, complex control is possible with a relatively simple circuit configuration. Furthermore, since irregularly input pulse signals are synchronized and detected, each signal can be detected accurately and the incrementer/decrementer can operate accurately. Next, an embodiment of the present invention of a motor with a phase detector (non-commutator motor) will be described with reference to the drawings. 1st
The figure shows the circuit configuration of a control device for a motor with a phase detector. The microcomputer is composed of a central processor (hereinafter referred to as CPU) 114, a random access memory (hereinafter referred to as RAM) 116, and a read only memory (hereinafter referred to as ROM) 118. The input/output circuit 120 includes an interface circuit 123 with the CPU 114, an analog/digital conversion circuit 124 (hereinafter referred to as an A/D converter) equipped with a multiplexer 122, an A/D converter 127 without a multiplexer, and a pulse output circuit. 126,
It has a pulse input circuit 128 and a discrete input/output circuit 125. 6 thyristors 136
~191, 6 flywheel diodes 19
3-phase inverter 160 composed of 2 to 197
The electric motor 100 is varied by. In addition, the DC power source connects the commercial AC power source 185 to the diode 176 to
179 and a smoothing capacitor 135. Further, a phase detector 150 is attached to the electric motor 100, and the phases of the windings U-phase, V-phase, and W-phase are detected. Its phase detection signal PU, PV, PW
Output. Furthermore, pulse outputs U ⁺ , U ^- , V ⁺ , V ^- , W ⁺ , W ^- output from the input/output circuit 120
ignites and extinguishes the thyristors 186 to 191 via the gate driver 130. The power device used here is a self-extinguishing thyristor, such as a gate turn-off thyristor GT0.
This is convenient in terms of circuit configuration. The microcomputer and input/output circuit 120 interfaces are connected by a data bus 162, an address bus 164, and a control bus 166. The microcomputer and input/output circuit 120 receive an enable signal E from the CPU 114.
is applied and synchronization is achieved. As analog input/output, two resistors 137 and 1
DC voltage E _D divided by 38, shunt resistor 1
_DC current ID of 36, motor temperature T _M of temperature sensor 104 attached to motor 100, speed command S _P
There is. Among these inputs, the important analog input is the _DC current ID. This DC current ID is passed through an amplifier 131 to an A/ _D converter without a multiplexer.
It is input to converter 127. Other DC voltages
E _D , motor temperature T _M , and speed command S _P are input to A/D converter 124 via amplifiers 132 to 134 and multiplexer 122, respectively. The multiplexer 122 selects one of the analog inputs commanded by the CPU 114 and inputs it to the A/D converter 124 . These inputs are input to the OPU 11 based on the instruction program stored in the ROM 118.
4 is designated via the address bus, and the designated analog input is taken in. Further, the digitally converted values are held in registers corresponding to the respective inputs, and are sent via the data bus 164 as necessary. Phase signals PU, PV, and PW are inputted to the pulse input circuit 128 from the phase detector 150 and synchronized with the enable signal E. Furthermore, data processed by the CPU 114 is taken into the interface 123 and held in the pulse output circuit 126. The output from the pulse output circuit 126 generates a signal with a pulse width corresponding to the signal inputted by the interface 123, and the output is a pulse width modulated signal U ⁺ , V ⁺ ,
These signals are W ⁺ , U ^- , V ^- , and W ^- , and these signals are designed to generate outputs after a start command is input to the discrete input/output circuit 125. FIG. 2 is a diagram showing the timing at which the pulse width modulation signals U ⁺ , V ⁺ , W ⁺ , U ^- , V ^- , W ^- are generated by the pulse output circuit 126. A carrier wave signal generated by
Compare with the data D1 level from CPU114,
Modulation is applied only to the latter 60 degrees of 120 degrees of energization. Similarly, for the data D2 level of the CPU 114, the pulse width is narrowed only at the rising edge of the first half of 60 degrees, and the respective pulse width modulation signals U ⁺ , V ⁺ , W ⁺ , U ^- , V ^- , W ^- are generated. FIG. 3 shows the circuit configuration of an electric motor (induction motor) without a phase detector. FIG. 3 is almost the same as FIG. 1, except that the phase detector 150 in FIG. 1 is replaced by a pulse generator 152. Further, a thyristor 198 and a resistor 181 are provided for voltage control, and voltage control is performed by chopping the thyristor 198. For this purpose, input/output circuit 1
Chopper signal of 20 pulse output circuits 126
Use CHOP. FIG. 4 shows that the pulse output circuit 126 generates 15 unequal pulse width modulated signals U ⁺ , V ⁺ , W ⁺ ,
It indicates the timing of creating U ^- , V ^- , W ^- .
It is created from carrier signal PWM and modulated waves SU, SV, and SW. FIG. 5 shows a specific circuit of the pulse output circuit 126, and the register group 570 is the reference register group mentioned above, and is used to hold data processed by the CPU 114 or to store a predetermined constant value. Holds data that indicates a value. This data is
The data is sent from the CPU 114 via the data latch 802 and write bus 806 as shown in FIG. The designation of each register holding data in the reference register group 570 is performed from the address bus 164 via the address decoder 906.
The above data is input to the designated register and held. The register group 572 is a momentary register group and holds the instantaneous state of the electric motor and the like. The instantaneous register group 572, latch circuit 576, and incrementer/decrementer 578 provide a so-called counter function. The output register group 574 includes, for example, a register that holds the rotational speed of the electric motor and a register that holds the period of pulse input. These values are obtained by reading the values of instantaneous registers when certain conditions are met. Output register group 57
The data held in 808 is sent to a related register by a signal sent from the CPU via an address bus and a control bus, and is sent from this register to the CPU 114 via a read bus 808. Comparison circuit 580 receives reference data from a selected register of reference register group 570 and instantaneous data from a selected register of instantaneous register group 572 at inputs 582 and 584, respectively;
Perform a comparison operation. The comparison result is output from output terminal 586. The output terminal is set to a predetermined latch in a first comparison output latch group 602 which acts as a comparison result holding circuit. Furthermore, it is then set in a predetermined latch of the second comparison output latch group 604. Reference register group 570, instantaneous register group 57
2. Read and write operations of the output register group 574, operations of the incrementer/decrementer 578 and comparison circuit 580, first comparison output latch group 60
2. The output setting operation to the second comparison output latch group 604 is processed within a predetermined time. Further, various processes are performed in a time-sharing manner according to the stage order of the stage counter 670. A reference register group 570 and an instantaneous register group 5 for each stage
a predetermined register of each of the 72 register groups;
A predetermined latch in the first comparison output latch group 602 and, if necessary, a predetermined register in the output register group 574 is selected. Also the incrementer/
Decrementer 578 and comparator circuit 580 are commonly used for each register in reference register group 570 and instantaneous register group 572. FIG. 6 is a diagram for explaining the timing of FIG. 5. An enable signal E is supplied from the CPU 114 to the input/output circuit 120. This signal is shown in A. This enable signal E generates non-overlapping two-phase clock signals φ ₁ and φ ₂ by the non-overlap circuit 701 shown in FIG. This signal is shown in C and B. The circuit shown in FIG. 5 operates according to these clock signals _φ1 and _φ2 . FIG. 6D shows the output signal of the stage counter 670, which is counted at the rising edge of the clock signal _φ1 . However, the output signal of the stage counter 670 is established in the shaded area due to wiring and gate delays. The stage counter 670
The stage decoder 672 generates a processed signal for each stage. but,
Since the processed signals of each stage are delayed considerably from φ ₁ , the effective time of each process is shortened. In order to extend the effective time of each process, the stage latch 674
The output signal of the stage latch 674 is shown in E. In FIG. 6, "T" indicates that the latch circuit or register circuit is in an enabled state, indicating that the output of these circuits is dependent on the input. Further, "L" indicates that these circuits hold certain data and that the output of this circuit does not depend on the input. Stage latch 67 becomes “T” when φ ₂ =1
4 holds the output signal of the stage decoder 672, and E becomes the stage processing signal, which is switched at the rising edge of the clock signal _φ2 , and the processing of each stage is performed in synchronization with _φ2 . The stage signal shown in E becomes a readout signal for the reference register group 570 and instantaneous register group 572, and reads the data from a selected predetermined register. H and H illustrate the operation of a reference register group 570 and an instantaneous register group 572, respectively. Reading of the reference register group 570 and the instantaneous register group 572 is performed by the stage signal E. Also, writing is performed with reference register group 570 and instantaneous register group 57 at φ ₁ =1.
This is done by setting 2 to "T", and is done in synchronization with _φ1 . The operation of data latch circuit 576 is shown in FIG.
This circuit is set to “T” by clock signal φ ₂ =1,
The data of a certain register read from the instantaneous register group 572 is written, and the clock signal φ ₂ =
When it is 0, it becomes “L”. In this way, data in a predetermined register in the instantaneous register group 572 corresponding to that stage is held. The data held in data latch circuit 576 is modified based on various conditions by incrementer/decrementer 578, which is not synchronized to the clock signal. Here, the incrementer/decrementer 578 is the incrementer/decrementer controller 5
It has the following functions based on the output signal 500 from the control signal generation circuit 591. The first function is an increment/decrement function that increases or decreases the value indicated by input data by one. The second function is a non-increment/decrement function, which allows input data to pass through without being increased or decreased. Third
The function is a reset function that changes all input data to data indicating a value of 0. Looking at the data flow of each register in the instantaneous register group 572, one of the instantaneous register group 572
One register is selected by the stage counter 672, and its held data is sent to the data latch circuit 5.
76 and an incrementer/decrementer 578 to a comparison circuit 580. Additionally, a closed loop is created from the output of incrementer/decrementer 578 back to the originally selected register. Therefore, when incrementer/decrementer 578 functions to increment or decrement data by one, this closed loop functions as a count. However, in this closed loop, the instantaneous register group 57
If a situation occurs in which the data of 2 is being output from a specific selected register, and the data is input in a loop, it will no longer have a counter function and will malfunction. Therefore, a data latch circuit 576 is provided to cut off the data. data·
The latch circuit 576 becomes “T” when the clock signal φ ₂ =1.
On the other hand, in the state "T" in which input data is written to the instantaneous register, the clock signal φ ₁ =1, so even if the data in a specific register in the instantaneous register group 572 is changed, the data latch circuit 576
The output of does not change. The operation is shown in q. In other words, data can be cut when φ ₂ =0. Furthermore, the output data of the incrementer/decrementer 578 that is not synchronized with the clock signal is established as shown in the shaded area due to delays in wiring and gates. Similar to incrementer/decrementer 578, comparison circuit 580 also operates out of synchronization with the clock signal. The input of the comparison circuit 580 is the reference register group 57
0, the reference data of one reference register selected by the stage signal E and the instantaneous register group 57
2, a data latch circuit 576 for instantaneous data of one register selected by the stage signal H
and data communicated via incrementer/decrementer 578. The comparison result of these two data is “T” when the clock signal φ ₁ =1.
Among the first comparison output latch group 602, the latch selected by the stage signal H is set. At this time, the comparison result output signal of the comparator circuit 580 is shown in the blank, and the area where the signal is established is the shaded area. Further, the output of the first comparison output latch group 602 is set to the second comparison output latch group 604 which becomes "T" when the clock signal φ ₂ =1. These first and second comparison output latch groups 602,
The operations of 604 are shown in FIGS. Also, the output of the second comparison output latch group 604 is the motor inverter gate signal UP, VP,
It becomes the output signal of WP, UN, VN, WN and the chopper signal CH, becomes each condition of the instantaneous register group 572, and becomes the input signal of the incrementer/decrementer controller 590. Further, the output signal of the second comparison output latch group 604 is transferred from the instantaneous register group 572 to the output register group 57.
It also serves as a transfer signal for writing to 4. The operation of the output register group 574 is shown in FIG. Out of the output register group 574, the output register selected by the stage signal H outputs the instantaneous data of the instantaneous register selected by the stage signal H among the instantaneous register group 572 at "T" when the clock signal φ ₁ =1. is written, and becomes "L" when the clock signal φ ₁ =0. When the CPU 114 reads data held in the output register group 574, the CPU 114 specifies the register via the read bus 808, and
Data is taken in in synchronization with clock signal E shown in FIG. Therefore, the interface between the input/output circuit 123 and the CPU 114 (for example, when Hitachi HD46800 is used as the CPU 114), at the timing shown in FIG. The timing differs depending on the output register group 574. Block diagrams of the data and addresses are shown in FIGS. Write data 806 written from the CPU 114 is held in the write latch circuit 802 which becomes “T” when φ ₂ =1, and is held in the write latch circuit 802 which becomes “T” when φ _{2 =1} .
1, data is written into the reference register selected by the address signal of the reference register group 570.
Also, the read data read to the CPU 114 is
The data is sent to the data bus 162 by the read bus 808 and the tri-state buffer circuit 804 enabled by the enable signal E=1 of the CPU 114, and is taken into the CPU 114. Further, the reference register group 570 and the output register group 574 are selected by an address signal from the CPU 114. As in the case of data, the timing of the register selection signal SEL differs between the reference register group 570 and the output register group 574. The reference register group 570 is held in an address latch circuit 902 which becomes "T" when φ ₂ =1, and then a chip select write is performed to determine whether write data or read data is generated by a signal on the control bus. The address latch circuit 902 is activated by the signal CSW and the chip select read signal CSR.
, or the address signal on the address bus 164. In the case of CSW, the output signal of the address latch circuit 902 is selected, and in the case of CSR, the address signal is selected. A register is selected by an address decoder 906 via this selection circuit 904. Furthermore, as described in FIGS. 1 and 3, since a controlled rectifier element is used in the inverter, the magnitude of the current in the element may become a problem, and the current may be further limited. Therefore, the input/output circuit 120 includes an A/D converter 124 to convert an analog quantity into a digital quantity. Other analog quantities required to control the electric motor include DC voltage and speed command. However, among the element current, DC voltage, speed command, etc., the most important analog quantity is the current of the control rectifier element.
Therefore, in FIG. 5, two A/D converters, an A/D converter 127 dedicated to the element current and an A/D converter 124 with a multiplexer 122, are connected to the input/output circuit 1.
20 have. Further, data converted into a digital amount by the current-only A/D converter 127 is stored in a digital 0 register 546, and data converted into a digital amount by the multiplexer-equipped A/D converter 124 is stored in a digital 1 register. 548
is maintained. However, digital 0 register 5
Since there is not enough time to process the current value of 46 by the CPU 114, the input/output circuit 1
Process within 20 seconds. Specifically, a process is performed to reduce the voltage applied to the current machine. The digital data of the digital 0 register 546, which holds the digital amount obtained by A/D conversion of the current, is compared with the reference data of the reference register group 570, which holds the data equivalent to the current limit value. However, the A/D converter 127 operates independently of the stage signal (E) in FIG. Therefore, each process generates a stage signal E in a certain order, and a processing stage is provided for comparing the current value with this stage signal. This is a type of stage interrupt function. The interrupt function to the stage is requested by the A/D conversion end signal (f) in FIG. 6, which is generated at the rising edge of _φ1 . At that time, the stage latch 674 does not hold the output signal of the stage decoder 672, but holds the A/D conversion end signal, and holds the digital data of the current value in the digital 0 register 546 and all current values. It is determined whether the current of the element has reached the limit value by comparing it with the reference data of the reference register group 570. At this time, the stage counter 670 does not count, and the stage _decoder 67
By holding the output signal No. 2 in the stage latch 674, the processing stages before the interrupt processing are performed, and each processing is subsequently performed in a certain fixed order. In addition, an A/D converter 124 with a multiplexer
The digital data converted by
The data is taken into the CPU 114 as data. The digital signal converted by the current-only A/D converter 540
Data is also taken into the CPU 114. The input/output circuit 120 includes a status register 550 that serves as an interrupt request signal to the CPU 114, and a mask register 552 that masks the interrupt request signal. Status register 55
0 holds the internal state of the motor and input/output circuit 120. The contents are shown in Table 1.

[Table] Figure 10 shows the status register 550, mask register 552, and interrupt controller 554.
shows. The status register 550 is the CPU 114
It serves as a read register for the CPU 114 in order to perform interrupt factor analysis. Further, the mask register 552 is a write register for designation from the CPU 114. The output signals of status register 550 and mask register 552 are annotated corresponding to each bit, and the output thereof becomes an interrupt request signal.
810 is a signal that causes an interrupt. Further, the registers for specifying the mode from the CPU 114 to the input/output circuit 120 include a mode 0 register 556, a mode 1 register 558, and a mode 2 register 560. The contents are shown in Table 2.

[Table] Mode 0 register 556, mode 1 register 558, mode 2 register 560 are all
It serves as a write register for specifying each mode from the CPU 114. The control signal generation circuit 591 generates a count signal, an increment/decrement function, and an increment/decrement function by an incrementer/decrementer controller 590 to control the increment/decrement function, non-increment/decrement function, and reset function, which are the functions of the incrementer/decrementer 578. Generates a decrement signal and a reset signal. The comparison controller 581 also controls the comparison circuit 58
This is for controlling the comparison result (≧,≦,=) of 0. The output controller 666 controls the maximum on time and minimum off time of the power element, and prevents lag between the P-side arm and the N-side arm, and protects and compensates the power element. Trigger counters 660 and 661 are counters for generating time for protection and compensation, trigger decoders 662 and 663 generate time for protection and compensation, and trigger latches 664 and 6
65 generates a trigger pulse. FIG. 11 shows a generation circuit for stage signal E.
When the clock signal φ ₁ from the non-overlap circuit 701 in FIG. 7 is 1, the stage counter 67
0 starts counting and its stage counter 67
0 outputs C ₀ to C ₉ and M ₂ of bit 2 of mode ₀ register 556 in FIG _.
Stage decoder 672 with T ₁ and T ₂ as input
added to. Stage decoder 672 generates signals O ₀ -O ₂₃ as outputs. This output signal
O ₀ to _{O 23} are input to a stage latch circuit 674, and the stage latch circuit 674 is set to "T" by clock signal φ ₂ =1 to hold the outputs O ₀ to O ₂₃ of the stage decoder 672. In addition, the reset input R of the stage latch circuit 674 receives the _M0 signal of bit 0 of the mode 0 register 556 in FIG. 5, and when _M0 = 0, all outputs of the stage latch circuit 674 are input. becomes "0" (low level), and all processing operations are stopped. On the other hand, the mode 0 register 556
When the signal M ₀ of bit 0 becomes 1, stage signals are output in a certain order, and processing is performed based on this. The stage decoder 672 can be easily realized by using a read-only memory or the like, and can also be implemented using a micro-programming method. In addition, the interrupt function to the stage is
This is done by the latch 1102 of the stage latch circuit 674 which outputs CMT-P. First, all the latch groups 1104 other than the latch 1102 of the stage latch circuit 674 are reset with the A/D conversion end signal, and operations other than interrupt operations are stopped. and,
Latch 110 the A/D conversion end signal (FIG. 6 F)
2 and performs an interrupt operation. Table 3 shows detailed processing contents of the stage signal output from the stage latch circuit 674.

【table】

[Table] Next, the stage signal and stage counter 67
0 and the outputs of registers 556 and 558 are shown in Table 4.

【table】

[Table] First, the general reset signal GR is input to the reset terminal of the stage counter 670 shown in FIG. 11, so that the counter outputs C ₀ to _{C 9} all become 0. This general reset signal GR is sent from the CPU 114 when this control circuit is activated.
In this state, the counter of the stage counter 670
C ₀ to C ₃ are 0, and when T ₀ of bit 0, T ₁ of bit 1, and T ₂ of bit 2 of the mode 1 register are all 0, when clock signal φ ₂ is input, φ ₂ At the rising edge of , the PWM8-P stage signal is output.
PWM 8 processing is performed using this stage signal. Next, the stage counter 670 counts by one when the clock signal φ ₁ =1, and furthermore, the next stage signal PN-P is outputted at the rising edge of the clock signal φ ₂ , and the processing of PN is performed by this stage signal. It will be done. In this way, the stage counter 6
When 70 continues counting with φ ₁ =1, a stage signal is output at the rising edge of φ ₂ and processing is performed according to this signal. C ₀ to _{C 9} of stage counter 670 are all 1
Then, the stage signal PGN-P is output (however, when M ₂ = 0 in the mode 0 register),
PGN processing is performed, and all the processing in Table 4 is completed. When the next clock signal φ ₁ =1, all C ₀ to C ₉ of the stage counter 670 become 0, and if the output of the mode 1 register 558 is 0, the stage signal PWM8-P is output when the clock signal φ ₂ =1. and PWM processing is performed. In this way, the processing in Table 4 is repeated. Therefore, the system flow of the input/output circuit 120 is shown in FIG. The register group and stage counter 670 are all set to 0 by the general reset signal GR=0. When the general reset signal GR becomes 1, it first sets bit 0 of the mode 0 register 556, that is, commands to start/stop the input/output circuit 120.
It is determined whether M ₀ is 1, and when M ₀ =0, the input/output circuit 120 is in a stopped state until M ₀ =1. With M ₀ = 1, stage counter 6
The output of 70 is 0, that is, the n=0th stage signal is generated. From here, the actual processing begins. First, when M ₀ =1, the nth stage signal is held in the stage latch circuit 674 and at the same time the following operation occurs. (i) The output signal of the first comparison output latch group 602 is held in the second comparison output latch group 604. (ii) The contents of the instantaneous register selected from the instantaneous register group 572 by the stage signal are held in the latch circuit 576. Next, it is determined whether the transfer signal MOVE is 0 or 1, and if MOVE=0, the stage counter 6
70 is counted, and the output of the latch circuit 576 is passed through an incrementer/decrementer 578.
The output is written to the selected instantaneous register and at the same time is compared with a reference register selected by the stage signal from the reference register group 570;
The comparison result is set in the first comparison output latch selected from the first comparison output latch group 602 by the stage signal. After that, A/D conversion end signal
Determine ADE. Also, the transfer signal MOVE=1
At the same time as the stage counter 670 counts, the contents of the instantaneous register are transferred from the output register group 574 to the output register selected by the stage signal, and all instantaneous registers are set to 0. Depending on whether the A/D conversion end signal ADE is 0 or 1, an interrupt to the stage is requested. ADE
When = 0, it returns to the original state and performs the next process, but when ADE = 1, mode 0 register 5
It is determined whether M ₃ of bit 3 of 56, that is, the interrupt mask bit to the stage, is 0 or 1, and when M ₃ =0, the process returns to the original state and performs the next process. When M ₃ =1, interrupt processing to the stage is performed. For this purpose, the A/D conversion end signal ADE is held in the stage latch circuit 674, and the stage signal CMT-
P, compares the contents of the digital 0 register with the contents of the current-related reference register of the reference register group 570, and sets the comparison result in the current-related first comparison output latch of the first comparison output latch group 602; The process returns to the original state and the processing before interrupting the stage is performed thereafter. The flow at the upper right of FIG. 12 is the flow when M ₀ =0 in mode 0 register 556, and at the same time as the input/output circuit 120 stops operating, M ₀ =0.
It will wait until the activation command becomes 1. Next, a circuit diagram for synchronizing the contents and operations of external pulse signals PU, PV, and PW is shown in FIG. 13, and timing is shown in FIG. 14. Output of stage latch circuit 674 in FIG.
Using STAGE3-P and STAGE2-P, enable signal E and the above external pulse signals PU, PV,
Generates a signal synchronized with PW (Fig. 14). External pulse signal PU for motor phase detector, etc.
PV and PW are connected to the latch circuit 130 in Fig. 13 by a signal that is a combination of STAGE3-P and _φ2 in Fig. 11.
2, 1304, and 1306, respectively. In Fig. 14, B is the clock signal φ ₂ , C is the clock signal φ ₁ , ta is the external pulse signal PU, PV, PW,
Re and G are stage signals STAGE3-P, STAGE
2-P. This stage signal is generated in synchronization with φ ₂ =1, as explained in FIG. The external pulse signal T and the stage signals R and S have no relationship in terms of time. Now, as shown in FIG. 14, the external pulse signal is connected to the latch circuits 1302, 1304, 130 in FIG.
Assuming that it is input to 6, the stage signal
AND signal of STAGE3-P and clock signal _φ2
STAGE3-P and _φ2 are respectively latched. Therefore, latch circuits 1302, 1304,
The output signals PU1, PV1, and PW1 of 1306 are the first
The result will be as shown in Figure 4 (Na). Latch circuit 130
8, 1310, 1312 are output signals PU1, PV
1, PW1 as stage signal STAGE2-P
AND signal STAGE2- with clock signal _φ2
The latch circuit 130 is used to latch with P・_φ2 pin.
8, 1310, 1312 output signals PU2, PV
2. PW2 becomes as shown in A of Fig. 14. Exclusive OR circuit 1314, 1316, 1318
are the signals PU1 and PU2, and the signals PV1 and PV, respectively.
2. Signals PW1 and PW2 are input, and the rising and falling detection signals of external pulse signals PU, PV, and PW are detected.
PUS, PVS, and PWS are generated, and the pulse width becomes the stage signal STAGE3-P to STAGE2-P in FIG. According to the synchronization circuit 680 in FIG. 13, the rise and fall of the external pulse signal can be detected as pulses with a constant width, and this pulse width is determined by the stage signal.
It is determined by the time difference between STAGE3-P and STAGE2-P. Therefore, latch circuits 1302, 1304, 13
By changing the stage signals input to 06, 1308, 1310, and 1312, the pulse width can be adjusted and changed. This pulse width is determined in relation to the stage signal assignments in Table 4. That is, in addition to STAGE2-P, which does not require an external pulse signal for processing, detection signals for the rising and falling edges of external pulses are established. This detection signal is the incrementer/decrementer controller 59.
The control signal becomes 0. Furthermore, the external pulse signals PU, PV, and PW of the synchronization circuit 680 shown in FIG. By inputting 60 to the 3-input OR circuit 1320 and inputting its output to the NOT circuit 1322,
You can get a pulse of 100 degrees. Furthermore, instead of using three inputs, the output of the pulse generator 152 can be input to any one of the external pulse signals PU, PV, and PW of the synchronization circuit 680 as shown in FIG. The number of rotations can be detected. In addition, synchronization is reliably applied to external pulse signals from phase detectors, etc., and synchronization pulses PUS, PVS,
In order to reliably generate PWS, it is necessary that the output from the phase detector and the like has a pulse width of 8 μs or more. (In this embodiment, the enable signal E from the CPU 114 is assumed to be 1 μs, and the stage signals PG-P and PULS-P in Table 4 are output every 8 μs.) If a pulse generator that outputs pulses is input to this synchronization circuit 608, the number of revolutions at which the pulse width is 8 μs is 7500 revolutions/minute. In order to follow higher rotational speeds, it is necessary to shorten this 8μs. Table 5 shows the detailed contents of the reference register group 570, which holds reference data corresponding to each pulse output that receives input data from an electric motor, etc., and is processed in the CPU 114. Further, its configuration diagram is shown in FIG. 15.

【table】

[Table] Table 6 shows the detailed contents of the instantaneous register group 572 that holds the instantaneous state of the electric motor etc. and has a counter function. Its configuration diagram is shown in FIG.

【table】

[Table] Table 7 shows detailed contents of the output register group 574 holding measured data. Its configuration diagram is shown in FIG.

[Table] First comparison output latch group 602 and second comparison output latch group 60 that hold the comparison output of comparison circuit 580
The detailed contents of 4 are shown in Table 8, and its configuration diagram is shown in FIG.

【table】

[Table] FIG. 16 is a diagram illustrating the generation of a pulse width modulation signal, which is the gate signal of the inverter of the motor with a phase detector (non-commutator motor) shown in FIG. The carrier wave PWM of the pulse width modulation signal is generated by processing the stage signal PWM-P. The carrier wave is PWMT of instantaneous register group 572, REG732
and P0 REG702 of the reference register group 570,
Made by P1 REG704. When processing stage signal PWM-P, PWMT REG73
2 is an unconditional incrementer/decrementer 57
Incremented or decremented by 8. Further, the output signals PU, PV, and PW of the phase detector 150 are inputted to the input/output circuit 120 as external pulse signals, and the synchronized external pulse signal PS indicating their rising and falling edges is " 1”, PWMT REG 732 is reset. Increment and decrement control is performed by the second
Comparison output latch group 604 P0 BE910 and P
1BF912. DEC/ of the output of a flip-flop (not shown) which is reset when P0 BF=1 and reset when P1 BF=1.
When INC is “0”, PWMT REG732 is incremented, and when DFC/INC is “1”,
PWMT REG 732 is decremented. Also, when decremented, P0
It is compared with REG702, and if the held data of P0 REG702 satisfies the condition that it is greater than or equal to the held data of PWMT REG732, the first comparison output latch group 6
Latch “1” to P0 FF754 of 02.
Furthermore, P0 of the second comparison output latch group 604
BF910 latches the output of P0 FF754,
The output of P0 BF910 becomes "1". When incremented, P1 REG7
04, and if the data held in the P1 REG 704 satisfies the condition below the data held in the PWMT REG 732, “1” is latched in the P1 FF 756 of the first comparison output latch group 602. moreover,
P1 BF912 of second comparison output latch group 604
latches the output of P1 FF756, and P1 BF
The output of 912 becomes "1". As shown in FIG. 19, the data held in the PWMT REG 732 changes with time. Next, the PN-P process of counting the number of pulses of the pulse modulation signal is performed by the instantaneous register group 572.
PNC REG734 is incremented when P0 BE910 is “1”, and when the synchronized external pulse signal PS is “1”, the data held in PNC REG734 is incremented by CPN REG of output register group 574.
Transferred to 752 (Fig. 19A), written, and PNC
REG 734 is reset. Therefore CPU11
4 can read the number of pulses. When processing stage signal OP-P, PWMT
REG732 is unconditionally non-incremented,
It is compared with D2 REG708 of the reference register group 570, and the data held in D2 REG708 is
When the following conditions are satisfied for the data held in PWMT REG 732, the first comparison output latch group 574
UP FF760, VP FF762, WP FF764,
UN FF766, VN FF768, WN FF770
is selected by the selection circuit shown in FIG. 20, and "1" is latched in the first comparison output latch group 602. Furthermore, the UP BF916 of the second comparison output latch group 604,
VP BF918, WP BF920, UN BF92
2. VN BF924 and WN BF926 are each
UP FF760, VP FF762, WP FF764,
UN FF766, VN FF768, WN FF770
Latch the output of Also, when processing the stage signal DP-P,
PWMT REG 732 is unconditionally non-incremented and D1 REG of reference register group 570
706, and when the data held in D1 REG 706 satisfies the condition that is greater than or equal to the data held in PWMT REG 732, the first comparison output latch group 57
4 UP FF760, VP FF762, WP FF7
64, UN FF766, VN FF768, WN FF
770 using the selection circuit shown in Figure 20, and the first
“1” is latched in the comparison output latch group 602.
UP BF916 of the second comparison output latch group 604,
VP BF918, WP BF920, UN BF92
2. VN BF924 and WN BF926 are respectively
UP FF760, VP FF762, WP FF764,
UN FF766, VN FF768, WN FF770
Latch the output of UP BF916, VP BF918, WP BF92
0, UN BF922, VN BF924, WN BF
The output signal of 926 becomes a pulse width modulation signal for each arm. FIG. 20 shows a selection circuit for the first comparison output latch group 602 necessary for processing the stage signals OP-P and DP-P using signals PU1, PV1, and PW1 that are synchronized with the phase detection signals shown in FIG. show. Also,
Table 9 is a selection table for the first comparison output latch group 602 according to the phase modes of PU1, PV1, and PW1.

[Table] Figure 20 shows the signal obtained by latching the phase detection signal, which is an external pulse signal, with STAGE3-P・φ ₂ =1.
Using PU1, PV1, and PW1 as input, the phase signals shown in Table 9, PHASE0, PHASE1,
PHASE2, PHASE3, PHASE4, PHASE
5. PHASE6, PHASE7 as phase decoder 30
2. Generated through the phase latch circuit 304.
The latches selected in the first comparative output latch group are shown in Table 9 as OP-P and DP-P in accordance with the phase signal.
selected for each process. Here, PHASE0,
The state of PHASE7 is a failure of the phase detector 150 and is an impossible state. like this
In PHASE0 and PHASE7, all arms are blocked and protected. FIG. 20 has a failure diagnosis function for the phase detector 150. Also,
In PHASE0 and PHASE7, “1” is written to bit 4 _S4 of status register 550,
This serves as an interrupt request signal to the CPU 114, making it possible to protect the power device. FIG. 21 is a diagram illustrating generation of a pulse modulation signal PWM, which is a gate signal of an inverter of unequal pulses in a motor (induction motor) without a phase detector as shown in FIG. The carrier wave PWM of the pulse width modulation signal is generated by processing the stage signal PWM-P. The carrier wave PWM is the PWMT of the instantaneous register group 572,
REG732 and P0 of reference register group 570
REG702, P1 Created by REG704. When processing the stage signal PWM-P,
PWMT REG 732 is unconditionally incremented or decremented by incrementer/decrementer 578. Increment and decrement control is performed by the second comparison output latch group 6.
This is done by P0 BF910 and P1 BF912 of 04. P0 Reset when BF=1, P1
When DEC/INC of the output of the flip-flop (not shown) which is reset by BF=1 is “0”, PWMT REG732 is incremented,
When DEC/INC is “1”, PWMT REG73
2 is decremented. Also, when decremented, P0
REG702, and if the held data of P0 REG702 satisfies the condition that is greater than or equal to the held data of PWMT REG732, the first comparison output latch group 6
Latch “1” to P0 FF754 of 02.
Furthermore, P0 of the second comparison output latch group 604
BF910 latches the output of P0 FF754,
The output of P0 BF910 becomes "1". When incremented, P1 REG7
04, and if the held data of P1 REG 704 satisfies the condition below the held data of PWNT REG, P1 of the first comparison output latch group 602
Latch “1” to FF756. Furthermore, the second
P1 of comparison output latch group 604 BF912 is P
1 Latch the output of FF756, P1 BF91
The output of 2 becomes "1". As shown in Figure 21
The data held in the PWMT REG 732 changes over time. Next, bit 4 of mode 0 register 556
Control of the number of unequal pulses when M ₄ is set to "1" will be explained. PN that counts the number of pulses in a pulse modulation signal
-P processing is the PNC of the instantaneous register group 572.
REG734 is incremented when P0 BF910 is “1”, and PN of reference register group 570 is incremented.
REG720, and if the held data of PN REG720 satisfies the condition below the held data of PNC REG734, the first comparison output latch group 574
Latch “1” to PN FF758. moreover,
PN BF912 of the second comparison output latch group 604 is
Latch the output of PN FF758 and PN BF912
The output of is "1". Also, PNC REG734
is reset when the output of PN BF912 is "1". The number of pulses is controlled by this PN BF912. FIG. 22 shows the phase detection signal of the phase detector 150.
Signals PU1, PV1, corresponding to PU, PV, PW
The phase generation circuit 306 of PW1 is shown. The phase generation circuit 306 is a three-stage shift register,
PNBF1 is shifted one stage at a time, and the shift status is shown in Table 10. There are 6 phase modes,
PHASE1, PHASE2, PHASE3, PHASE
4, PHASE5, PHASE6.

[Table] Next, the pulse width modulation signals of each arm of the unequal pulse are the stage signals UTM-P, VTM-P, WTM.
- This is done by processing P. During UTM-P processing, PWMT REG732 is unconditionally non-incremented, and the reference register group 5 in FIG.
70 selection circuit reference register selection latch 312
A register (D1) related to the modulated wave selected by
REG706,D2 REG708,D3 REG
710, D4 REG712, D5 REG714,
D6 REG716, D7 REG718) are compared with the data held therein, and the comparison result is the comparison output (reference register≦instantaneous register, reference register≧instantaneous register, phase signal) selected by comparison result selection latch 310 in FIG. is latched to the UP FF760 of the first comparison output latch group 602, and at the same time, the inverted signal of the comparison output is latched to the UN FF766 of the first comparison output latch group 602, and further, the UP BF91 of the second comparison output latch group 604 is latched.
6, UP FF760 to UN BF922,
UN Latch the output of FF766. Furthermore, the processing of stage signals VTM-P; WTM-P operates similarly. FIG. 23 shows a pulse width modulation control circuit. P
0 BF910 output is counted as “1” and PN
The outputs SC ₀ , SC ₁ , SC ₂ , of the PN stage counter 314 are reset when the output of the BF 914 is “1”.
A pulse width modulation decoder 308 receiving SC ₃ and phase signals PU1, PV1, and PW1 selects a reference register of the reference register group 570 and selects a comparison result. Stage signal UTM−
The reference register selection latch 312 and comparison result selection latch 310 latched by P, VTM-P, and WTM-P generate the reference register selection signal D1 REG SEL, D2 REG SEL, D3 shown in Table 11.
REG SEL, D4 REG SEL, D5 REG
SEL, D6 REG SEL, D7 REG SEL and comparison result selection signal GE SEL (data held in the reference register ≦ data held in the instantaneous register), LESEL (data held in the reference register ≧ data held in the instantaneous register), PHASE SEL (phase signal ) occurs.

【table】

【table】

[Table] The results shown in Figure 21 are UP BF916,
VPBF918, WP BF920, UN BF922,
VN BF924, WN BF926 signals are created,
A gate signal is provided to each arm. 15 shown in Figure 21
A pulse width modulated signal of unequal pulses can be generated. In addition, the nine unequal pulses and the three unequal pulses are also input to the PN REG of the reference register group 570.
This is possible by changing the data of 720 from the CPU 114, and it is preferable to change it according to the frequency of the inverter. Furthermore, for equal pulses, by setting M4 of bit ₄ of mode 0 register 556 to “0”, D1 REG7 of reference register 570 is set to “0”.
This is possible by selecting only 06. Also, bit 6 of mode 0 register 556
When M ₆ is set to "0", the pulse width modulation signal is generated in the motor with phase detector (non-commutator motor) shown in Figure 19, and when M ₆ is set to "1", the pulse width modulation signal is generated in the induction motor shown in Figure 21. This results in the generation of a pulse width modulated signal. FIG. 24 is a diagram illustrating the generation of the chopper signal CH. The chopper signal CH performs duty control. The reference register group 570 includes a CHP REG 724 that holds synchronous data as shown in FIG.
and CHD REG72 that holds on-time data
There are 6. Also, as a timer, instantaneous register group 5
Made by CHT REG740 of 72. When processing stage signal CHP-P, CHT
REG740 is unconditionally incremented and also compared with CHP REG724, and CHP REG72
When the held data of CHT REG 740 satisfies the following conditions, the CHP FF 774 of the first comparison output latch group 602 is latched to “1”. Furthermore, the second comparison output latch group 604
CHP BF930 latches the output of CHP FF774, and the output of CHP BF930 becomes "1". When processing stage signal CHD-P, CHT
REG740 is unconditionally non-incremented. Also, the output of CHP BF930 is “1”.
CHT REG 740 is reset. In this process, the data held in CHD REG726 is
When the following conditions are satisfied for the held data of REG740, CHD FF of the first comparison output latch group 602
CHD FF 776 is latched to "1", and CHD BF 932 of the second comparison output latch group 604 latches the output of CHD FF 776, and the output of CHD BF 932 becomes "1". The inverted output of this CHD BF932 is the chopper signal CH. Figure 25 shows the synchronized external pulse signal PS
There are two processes to measure the pulse time width: PG process,
FIG. 7 is a diagram illustrating the state of PGN processing when M ₂ =0 in the mode 0 register 556. The measurement method is a synchronized external pulse signal PS
Measurement starts when =1. The time width to be measured is determined by PG REG 738 of instantaneous register group 572. PG REG738 is the PGT REG73 of the instantaneous register group 572 when processing the stage signal PG-P.
8 is unconditionally incremented. However, if the pulse time width of the synchronized external pulse signal PS becomes longer, the PGT REG 738 will overflow (point B in FIG. 25). Therefore, P.G.T.
There is a stage signal PGN-P process that counts the number of overflows of REG738. Also, the data held in PGT REG 738 is compared with the data held in P0 REG 702 of the reference register group 570 (normally all 0), and P0
When the data held in REG 702 satisfies a condition that is greater than or equal to the data held in PGT REG 738, PG FF 780 of first comparison output latch group 602 is latched to “1”. Furthermore, the second comparison output latch group 60
4 PG BF936 latches the output of PG FF780, and the output of PG BF780 becomes “1”,
It can be seen that PGT REG738 has overflowed. Further, in processing the stage signal PGN-P for counting the number of overflows, PGNCREG 740 of the instantaneous register group 572 is incremented under the condition that PG BF indicating an overflow is "1". With the synchronized external pulse signal PS=1,
By processing stage signal PG-P, PGT REG73
PG of the register group 574 outputs the retained data of 8.
Transfer to REG748 (Figure 25C) and write PG
REG 738 is reset. In addition, in processing the stage signal PGN-P, the data held in the PGNC REG740 is transferred to the PGN of the output register group 574.
Transfer to REG750 (Fig. 25D), write,
PGNC REG 740 is reset. PG REG748 of output register group 574 and
It is possible to measure the pulse time width of the external pulse signal PS synchronized with the data held by each PGN REG750. FIG. 26 shows M=1 in mode 0 register 556.
FIG. 3 is a diagram illustrating a method and process for counting synchronized external pulse signals PS within a certain time width in the state of FIG. of the instantaneous register group 572 that measures the time width.
PULSWT REG736 is a stage signal
It is unconditionally incremented by PULSW-P, and PULSW BF of the second comparison output latch group 604
It is reset when 928 is "1". In addition, the data held in PULSW REG 722 of the reference register group 570 and the data of the instantaneous register group 572 are
Compared with the data held by PULSWTREG736,
The data held in PULSWREG722 is PULSWT
When the following conditions are satisfied for the held data of REG736, the PULSW of the first comparison output latch group 602
Latch “1” to FF722. Furthermore, the second
PULSW BF928 of comparison output latch group 604 is
Latch the output of PULSW FF772, and
The output of the FF928 becomes "1", and a certain time width can be obtained. PULSWD showing the rise of PULSW BF928
=1, the data held in the PULSW REG738 of the instantaneous register group 572 that counted the external pulse signal PS synchronized by the processing of the stage signal PULS-P is output to the PULS REG74 of the register group 574.
8 (Fig. 26E) and write. Also,
When PULSW BF928 is “1”, PULSC
REG 738 is reset and a count of synchronized external pulse signals PS within a certain time width is obtained. The PG-P, PGN-P processing in Figure 25 and the PULS-P processing in Figure 26 both indicate the rotational speed of the motor, and the PG-P, PGN-P processing with good accuracy at low speeds.
PULS-P processing has good accuracy at high speed.
Mode 0 in Table 2 written by CPU114
Switched by register _M2 . Figure 27 shows a stage signal that operates as a timer and requests an interrupt to the CPU 114 at certain intervals.
It is a figure explaining the processing of INTV-P. of the instantaneous register group 572 that measures the time width.
INTVT REG742 is the stage signal INTV-
It is unconditionally incremented by the processing of P, and
INTV BF934 of second comparison output latch group 604
It is reset when is "1". In addition, the data held in INTV REG 728 of the reference register group 570 and the INTVT-REG 744 of the instantaneous register group 572 are
is compared, and the retained data of INTV REG728 is
When the following conditions are satisfied for the data held in INTV REG 744, the first comparison output latch group 602
Latch “1” to INTV FF778. Furthermore, INTV BF9 of the second comparison output latch group 604
34 latches the output of INTV FF778,
The output of INTV BF934 becomes "1". INTVD indicating the rise of this INTV BF934
= 1 and bit 5 of status register 550 S ₅
By writing 1 to , it becomes an interrupt request signal to the CPU 114 . FIG. 28 is a diagram illustrating an interrupt to a stage for current limitation. The stage signal CMT-P is not processed after a certain period of time, but by the current-only A/D converter 546.
This is generated by the A/D conversion end signal ADE=1. Stage signal CMT-P is processed by current-only A/
The DGTLO REG 546 holding the A/D converted digital data of the D converter 546 is compared with the data held in the CMT REG 730 of the reference register group 570, and the condition that the data held in the CMT REG 730 ≦ the data held in the DGTLO REG 546 is satisfied. When the first comparison output latch group 602
Latch “1” to CMT FF782. Furthermore, CMT BF9 of the second comparison output latch group 604
37 latches the output of CMT FF782 and
The output of BF937 becomes "1". CMTD= which shows the rise of this CMT BF937
By writing 1 to S3, bit ₃ of the status register 550, it becomes an interrupt request signal to the CPU 114. Also, when CMTD=1, the output pulse is turned off. FIG. 29 shows trigger pulse signals TRG0-P and TRG1 for controlling the output controller 666.
-P is a detailed circuit diagram for generating. These trigger pulse signals TRG0-P and TRG1
-P is used to protect the power elements of each arm of the inverter. The output controller 666 has a protection function of compensating for the minimum on time and minimum off time of the power devices, and preventing overlap between the power devices of the P side arm and the power device of the N side arm of the inverter. Trigger 0 counter 660 counts with stage signal STAGE3-P・φ ₁ =1, and its output is
_{Output signals TRG0-8 , _ _ _ _}
TRG0-16, TRG0-32, TRG0-64,
TRG0-128 is created. Table 12 shows the contents of trigger 0 decoder 662. Output signal TRG
0-8, TRG0-16, TRG0-32, TRG
0-64, TRG0-128 are passed through a 5-input NOR circuit 412, the output of the NOR circuit 412 is latched by the latch circuit 664 which becomes "T" when φ ₂ =1, and the clock signal φ ₂ and the latch circuit 664 are The output of the NOR circuit 420 whose input is the output of TRG0-
It becomes P.

【table】

[Table] TRG1-P is also output by the trigger 1 decoder 663 as shown in Table 13.
This is the same operation as TRG0-P. Also, TRG0-8, TRG1-8 every 8μs,
TRG0-16, TRG1-16 every 16μs, TRG
0-32, TRG1-32 every 32μs, TRG0-6
4, TRG1-64 every 64μs, TRG0-128,
It is a pulse that occurs every TRG1-128μs,
In order to generate fine pulses, it is also possible to provide TRG0-P and TRG1-P in the stage signals. This time span becomes the time for compensation and protection. FIG. 30 is a detailed circuit diagram of the output controller 666, and FIG. 31 is its timing diagram. Two of the pulse width modulated signals of the second comparison output latch group 604, UP BF 916 and UP BF 922, will be described. The output signal of the UP BF916 is input to the latch circuit 430 which becomes "Through" when the trigger 0 and pulse signal TRG0-P=1. The output signal UPS1 of the latch circuit 430 has a waveform as shown in FIG. Since it is shorter than the pulse width of TRG0-P of the output signal α of the UP BF916, it does not appear as a pulse in the UPS1.
Here, compensation for the minimum on-time of the power element can be performed. The output signal of UN BF 922 is the input to latch circuit 432, which operates in the same manner as latch circuit 430. The output signal of the latch circuit 432
UNS1 also has a waveform as shown in FIG. 31.
Similar to UPS1, this UNS1 also does not have a pulse corresponding to α. Here, compensation for the minimum on-time of the power element can be performed. Furthermore, trigger 1/pulse signal TRG1-P=
The output signal UPS1 of the latch circuit 430 is the input to the latch circuit 442 which becomes "1" when the signal is "1".
The output signal becomes UPS2. UPS1 and UPS2
The output signal of the AND circuit 466 inputting is U ⁺ . In addition, trigger 1/pulse signal TRG1-P
The output signal UNS1 of the latch circuit 432 is input to the latch circuit 444, which becomes "T" when =1, and becomes the output signal UNS2. UNS1 and
The output signal of the AND circuit 468 which receives UNS2 as an input is U ^- . U ⁺ serves as the gate signal for the P-side arm of the inverter, and serves as the gate signal for the N-side arm.
As shown in Figure 31, U ^- has a non-overlap of time γ _Lag , and when the U ^- off signal is input and time γ _Lag has elapsed, the power element on the N side arm is completely turned off. Therefore, an on signal is generated at U ⁺ , which turns on the power element of the P side arm. Also, VP BF918 of the second comparison output latch group
The relationship between and VN BP924, and WP BF920
The relationship with WN BF926 is UP BF916 and UN
It's the same with my relationship with BF. Furthermore, the relationship between the output of CHD BF932 and the signal CHOP is UP.The output of BF918 and the latch circuit 430
Same as the relationship with the output signal UPS1, it is possible to compensate for the minimum on time and minimum off time. Selectors 458, 460, 46 in Figure 30
2,464 is controlled by bit 7 of mode 0 register 556, _M7 . When M ₇ = 0
U ⁺ and U ^- have the outputs of UP BF916 and UN BF922, and W ⁺ and W ^- have the outputs of WP BF920 and WN.
The output of BF926 is involved, and the motor rotates in the normal direction.
However, when M ₇ = 1, for U ⁺ and U ^- , WP BF
The outputs of UP BF916 and UN BF922 are related to W ⁺ and W ^- , and the motor is reversed. In this way, the gate signals U ⁺ , U ^- , V ⁺ , V ^- , W ⁺ , W ^- of the pulse width modulation of the output pulse signal and the chopper signal CHOP are completely compensated and protected before being applied to the gate driver. 130. Next, a method for setting reference data in the reference register group 570 will be explained. For example, in order to generate the pulse width modulation signal shown in Fig. 4, the speed command S _P is A/D converted and the CPU
Based on the data, the effective voltage applied to the motor 152 and the number of unequal pulses are obtained by calculation processing or from information stored in a map form with respect to the frequency from the speed command _SP . P0 RE702, P1 REG704 for frequency
Further, data is set in PN REG 720 which is the number of pulses and D1 to D7 REGs 706 to 718 of modulated waves which determine the effective voltage. Once these data are set,
The pulse width modulated signal of FIG. 4 is generated. moreover,
When changing the effective voltage to the electric motor 152, the CPU
Calculate and process D1 to D7 REG706 to 71
By setting the data of 8, a pulse width modulation signal is generated. As shown in FIG. 24, the chopper signal CHOP outputs cycle and on-time data obtained from calculation processing in the CPU 114 or based on map-like information according to the state of the motor, respectively, to CHP REG.
724 and CHD REG 726, a signal is generated to control the energization time of the power element. FIG. 25 and FIG. 26 show the measurement of the rotational speed. Figure 25 shows the case where the motor is running at a low speed, and the time width of the external pulse signal is measured, and the output register group is
Data is held in PG REG 748 and PGN REG 750 and taken into CPU 114. Time width T T = (PGN REG750 retained data) ×
It is calculated as 2048μs + (PG REG748 retention data) x 8μs, and the rotation speed can be measured. In FIG. 26, the number of external pulses within a certain time width is counted, the data is held in the PULS REG 748, and is taken into the CPU 114. Further, the time width is determined by setting data to the PULSW REG 722. A timer interrupt request from the CPU 114 is used when a timer is required in program creation, and an interrupt request is generated by setting data of the necessary time in INTV REG 728. Current limiting is performed by interrupting the stage and by setting limit value data in CMT REG 730. Furthermore, an interrupt to the stage occurs after the A/D conversion is completed. As described above, according to the embodiment of the present invention, since the external pulse signal input irregularly is synchronized with the stage signal, not only accurate detection is possible, but also the order of the stages can be adjusted according to the accuracy. This allows the detection stage to be shortened, and since the synchronization signal is included in each process, accurate detection is possible even when the motor is rotating at high speed. As described above, the present invention provides a speed command means for giving a speed command to an electric motor, a plurality of detection means for detecting the speed of the motor or the position of a rotor, and output signals of these plurality of detection means as digital control variables. a digital arithmetic circuit that performs arithmetic processing as a digital arithmetic circuit; a pulse input/output circuit that converts the output of the digital arithmetic circuit into a predetermined pulse output; In the device comprising a control means, a reference register group for holding the output of the digital arithmetic circuit, an instantaneous register group for holding the detection signals of the plurality of detection means, and sampling the output of the instantaneous register group. A comparison circuit that compares the data held in each register selected from the output register group and the reference register group and instantaneous register group, and a comparison output latch group that holds the output of the comparison circuit, and each process is time-divided. A stage counter for controlling and data held in the instantaneous register group are selected by a stage signal of the stage counter, and the selected held data is held in the instantaneous register again via an incrementer/decrementer. First, the comparison output latch group includes a first comparison output latch group and a second comparison output latch group that holds the output of the first comparison output latch group, and the second comparison output latch group holds the output of the first comparison output latch group. The output signal of the output latch group is outputted as a control signal for the electric motor, and the output signal of one of the second comparison latch groups selected according to the stage signal of each stage is applied to the incrementer/decrementer controller. Second, since a data latch circuit for holding the instantaneous data of the instantaneous register group is provided between the instantaneous register group and the incrementer/decrementer, in particular, the first comparison output latch group and Second
Since the comparison output latch group in the first embodiment cuts off the loop-around of counting conditions, and the latter data latch circuit also cuts off the loop-around on data, a malfunction of the counter function is prevented, and a motor control device that does not impair controllability is provided. It is possible.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the circuit configuration of a control device for a motor with a phase detector (non-commutator motor) in one embodiment of the present invention, and Fig. 2 shows a pulse width modulated wave of each phase in Fig. 1. Figure 3 is a circuit configuration diagram of a control device for a motor without a phase detector (induction motor), Figure 4 is a diagram explaining the pulse width modulation waves of each phase in Figure 3, and Figure 5 is a diagram explaining the pulse width modulation wave of each phase in Figure 3. A detailed circuit diagram of the input/output circuit, Figure 6 is a timing diagram of the input/output circuit, Figure 7 is a non-overlap circuit diagram, Figure 8 is a block diagram of the data bus, and Figure 9 is a diagram of the address bus. Block configuration diagram, Figure 10 is an explanatory diagram of the status register and mask register, Figure 11 is a stage signal generation circuit diagram, Figure 12 is a system flow diagram of the input/output circuit, and Figure 13 is an external pulse synchronization diagram. Figure 14 is the timing diagram of Figure 13, and the first
Figure 5 is a detailed register configuration diagram of the reference register group, Figure 16 is a detailed register configuration diagram of the instantaneous register group,
FIG. 17 is a detailed register configuration diagram of the output register group, FIG. 18 is a latch configuration diagram of the first and second comparison output latch groups, and FIG. 19 is a timing diagram of the pulse width modulation signal generation process in FIG. 2. Figure 20 is the first
Fig. 9 is a selection circuit diagram of the first comparison output latch group, Fig. 21 is a timing diagram of the generation processing of the unequal pulse width modulation signal of Fig. 4, Fig. 22 is a phase generation circuit diagram, and Fig. 23 is a pulse width modulation signal diagram. Control circuit diagram, No. 24
The figure is a timing diagram of the chipping signal generation process, the second
Figure 5 is a timing diagram for measuring the pulse time width of an external pulse signal, Figure 26 is a timing diagram for counting pulses within a certain time width, Figure 27 is a timing diagram for timer interrupt generation processing, and Figure 28 is for current limiting. 29 is a signal generation circuit diagram of the output controller, FIG. 30 is a detailed circuit diagram of the output controller, and FIG. 31 is a timing diagram of FIG. 30. 100...Motor with phase detector (non-commutator motor), 102...Motor without phase detector (induction motor), 104...Temperature sensor, 114...
CPU, 116...RAM, 118...ROM, 1
20... Input/output circuit, 122... Multiplexer, 123... Interface circuit, 12
4,127...analog-digital conversion circuit,
125...Discrete input/output circuit, 126...
...Pulse output circuit, 128...Pulse input circuit,
130...Gate driver, 131-134
...Amplifier, 135 ...Smoothing capacitor, 136
...Shunt resistor, 137,138...Voltage dividing resistor, 150...Phase detector, 152...Pulse
Generator, 160... Inverter, 162...
...Data bus, 164 ...Address bus, 1
66... Control bus, 175... Rectifier circuit, 176-179... Diode, 181...
Resistor, 185... Power supply, 186-191... Thyristor, 192-197... Diode, 198
... Thyristor, 302 ... Phase decoder, 30
4... Phase latch circuit, 306... Phase generation circuit, 308... Pulse width modulation decoder, 310...
...Comparison result selection latch, 312...Reference register selection latch, 314...PN stage counter, 412, 414...NOR circuit, 420, 4
22...NOR circuit, 430, 432, 434,
436, 438, 440, 442, 444, 44
6,448,450,452,454...Latch, 456...NOT gate, 458,460,
462,464...AND-OR gate, 466,
468,470,472,474,476...
AND circuit, 500... Incrementer/decrementer control bus, 540, 542...
Analog-digital conversion circuit, 544...Multiplexer, 546, 548...Digital register, 550...Status register, 552...Mask register, 554...Interrupt controller, 556...Mode 0 register, 558...Mode 1 register, 560...
Mode 2 register, 570...Reference register group, 572...Momentary register group, 574...Output register group, 576...Latch circuit, 578...
Incrementer/decrementer, 580... Comparison circuit, 581... Comparison result controller, 590
... Incrementer/decrementer controller, 591 ... Control signal generation circuit, 60
2...First comparison output latch group, 604...Second comparison output latch group, 660, 661...Trigger counter, 662, 663...Trigger decoder,
664, 665...Latch, 666...Output controller, 670...Stage counter, 67
2... Stage decoder, 674... Stage latch circuit, 680... Synchronization circuit, 701
...Non-overlap circuit, 702, 704,
706, 708, 710, 712, 714, 71
6,718,720,722,724,726,
728, 730, 732, 734, 736, 73
8,740,742,744,746,748,
750,752...Register, 754,756,
758, 760, 762, 764, 766, 76
8,770,772,774,776,778,
780,782...Latch, 802...Data
Latsuchi, 804...Tri-state buffer,
806...Write bus, 808...Read bus, 810...Interrupt factor signal, 902...Address latch circuit, 904...Address selector, 906...Address decoder, 910,
912,914,916,918,920,92
2,924,926,928,930,932,
934,936,938...Ratsuchi, 1102,
1104...Latch circuit, 1302, 1304,
1306, 1308, 1310, 1312... Latch, 1314, 1316, 1318...
EXCLUSIVE OR circuit, 1320...NOR circuit, 1322...NOT circuit.

Claims (1)

[Claims] 1. A speed command means for giving a speed command to the electric motor, a plurality of detection means for detecting the speed of the motor or the position of the rotor, and output signals of these plurality of detection means as digital control variables. A digital arithmetic circuit that performs arithmetic processing, a pulse input/output circuit that converts the output of the digital arithmetic circuit into a predetermined pulse output, and control for controlling a plurality of digital control amounts of the electric motor based on the output of the pulse input/output circuit. A reference register group for holding the output of the digital arithmetic circuit, an instantaneous register group for holding the detection signals of the plurality of detection means, and an output for sampling the output of the instantaneous register group. A comparison circuit that compares the data held in each register selected from the reference register group and instantaneous register group with the register group, a comparison output latch group that holds the output of the comparison circuit, and time-division control of each process. A stage counter for the purpose of the present invention and data held in the instantaneous register group are selected by a stage signal of the stage counter, the selected held data is held in the instantaneous register again via an incrementer/decrementer, and the comparison output is The latch group includes a first comparison output latch group and a second comparison output latch group that holds the output of the first comparison output latch group, and outputs the output signal of the second comparison output latch group to the electric motor. The control signal is output as a control signal for the incrementer/decrementer controller, and the output signal of one of the second comparison latch groups selected according to the stage signal of each stage is applied to the incrementer/decrementer controller. A control device for an electric motor. 2. A speed command means that gives a speed command to the electric motor, a plurality of detection means that detects the speed of the motor or the position of the rotor, etc., and a digital calculation circuit that processes the output signals of these plurality of detection means as digital control variables. , a pulse input/output circuit for converting the output of the digital arithmetic circuit into a predetermined pulse output, and a control means for controlling a plurality of digital control amounts of the electric motor based on the output of the pulse input/output circuit. , a reference register group for holding the output of the digital arithmetic circuit, an instantaneous register group for holding the detection signals of the plurality of detection means, an output register group for sampling the output of the instantaneous register group, and the above-mentioned standard. A comparison circuit that compares the data held in each register selected from the register group and the instantaneous register group, a comparison output latch group that holds the output of the comparison circuit, and a stage counter for time-division control of each process. , selects the data held in the instantaneous register group by a stage signal of a stage counter, holds the selected held data in the instantaneous register again via an incrementer/decrementer, and connects the instantaneous register group and the incrementer/decrementer. 1. A control device for an electric motor, characterized in that a data latch circuit for holding instantaneous data of the instantaneous register group is provided between the instantaneous registers.